[all-commits] [llvm/llvm-project] c6ca13: [RISCV] Lower interleave + deinterleave for zvfhmi...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c6ca13db41e135d593e33f85cf955d2c041580c3
      https://github.com/llvm/llvm-project/commit/c6ca13db41e135d593e33f85cf955d2c041580c3
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-13 (Fri, 13 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

  Log Message:
  -----------
  [RISCV] Lower interleave + deinterleave for zvfhmin and zvfbfmin (#108404)

Fortunately f16 and bf16 are always < EEW, so we can always lower via
widening or narrowing. This means we don't need to add patterns for
vrgather_vv_vl just yet.



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