[all-commits] [llvm/llvm-project] ecf260: [RISCV] Merge bf16 tests into respective tests. NFC

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ecf260e1dd8fb1c3d81e6f8af99907ae250058cb
      https://github.com/llvm/llvm-project/commit/ecf260e1dd8fb1c3d81e6f8af99907ae250058cb
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-12 (Thu, 12 Sep 2024)

  Changed paths:
    R llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
    R llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
    R llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode-bf16.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll

  Log Message:
  -----------
  [RISCV] Merge bf16 tests into respective tests. NFC

I added these in #108245, but given the sheer number of tests that
will need to be added to cover bf16 promotion to f32 it seems better
to keep them in one place to avoid an explosion of files.


  Commit: 89c10e27d8b4d5f44998aad9abd2590d9f96c5df
      https://github.com/llvm/llvm-project/commit/89c10e27d8b4d5f44998aad9abd2590d9f96c5df
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-12 (Thu, 12 Sep 2024)

  Changed paths:
    M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
    M llvm/test/Analysis/CostModel/RISCV/fp-min-max-abs.ll
    M llvm/test/Analysis/CostModel/RISCV/fround.ll
    M llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll
    M llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-broadcast.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-transpose.ll
    M llvm/test/Analysis/CostModel/RISCV/splice.ll

  Log Message:
  -----------
  [RISCV] Add zvfhmin cost model test coverage. NFC

This adds tests coverage for zvfhmin and halfs in general in the cost
model tests.

Some existing half tests were split into separate functions so that if
the check prefixes diverge it won't affect the rest of the non-half
instructions.

Whilst we're here, also remove the redundant
-riscv-vector-bits-min=128 and declares.


Compare: https://github.com/llvm/llvm-project/compare/adde85e7c3ad...89c10e27d8b4

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