[all-commits] [llvm/llvm-project] 480f07: [RISCV] Add fixed length vector patterns for vfwma...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 480f07ff6c7ac2d928b6f1862698dbd51069735c
      https://github.com/llvm/llvm-project/commit/480f07ff6c7ac2d928b6f1862698dbd51069735c
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-12 (Thu, 12 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll

  Log Message:
  -----------
  [RISCV] Add fixed length vector patterns for vfwmaccbf16.vv (#108204)

This adds VL patterns for vfwmaccbf16.vv so that we can handle fixed
length vectors.

It does this by teaching combineOp_VLToVWOp_VL to emit
RISCVISD::VFWMADD_VL for bf16. The change in getOrCreateExtendedOp is
needed because getNarrowType is based off of the bitwidth so returns
f16. We need to explicitly check for bf16.

Note that the .vf patterns don't work yet, since the build_vector splat
gets lowered to a (vmv_v_x_vl (fmv_x_anyexth x)) instead of a vfmv.v.f,
which SplatFP doesn't pick up, see #106637.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications