[all-commits] [llvm/llvm-project] 35e27c: [AMDGPU][True16][MC] 16bit vsrc and vdst support i...

[Brox Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 35e27c0ee51f2822415c050c1cc4a73dfaa171d7
      https://github.com/llvm/llvm-project/commit/35e27c0ee51f2822415c050c1cc4a73dfaa171d7
  Author: Brox Chen <guochen2 at amd.com>
  Date:   2024-09-11 (Wed, 11 Sep 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
    A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-fake16.mir
    A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
    M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
    M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
    M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt

  Log Message:
  -----------
  [AMDGPU][True16][MC] 16bit vsrc and vdst support in MC (#104510)

This is a large patch includes the MC level support for V_CVT_F16_F32,
V_CVT_F32_F16 and V_LDEXP_F16 in true16 format.

This patch includes the asm/disasm changes to encode/decode the 16bit
vsrc, vdst and src modifieres for vop and dpp format. This patch is a
dependency for many 16 bit instructions while only three instructions
are updated to make it easier to review.

There will be another patch to support these three instructions in the
codeGen level, this patch just replaces these two instructions with its
fake16 format.



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