[all-commits] [llvm/llvm-project] a794ee: [VPlan] Add VPValue for VF, use it for VPWidenIntO...

[Florian Hahn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a794ee455999ed02671808c2c0ef08d753e811a1
      https://github.com/llvm/llvm-project/commit/a794ee455999ed02671808c2c0ef08d753e811a1
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-09-10 (Tue, 10 Sep 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
    M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
    M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
    M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
    M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll

  Log Message:
  -----------
  [VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

Similar to VFxUF, also add a VF VPValue to VPlan and use it to get the
runtime VF in VPWidenIntOrFpInductionRecipe. Code for VF is only
generated if there are users of VF, to avoid unnecessary test changes.

PR: https://github.com/llvm/llvm-project/pull/95305



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications