[all-commits] [llvm/llvm-project] bf6948: [VectorCombine] Add type shrinking and zext propag...

[Igor Kirillov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bf694841f5b986f677e4fbe2a7ee93c77690d765
      https://github.com/llvm/llvm-project/commit/bf694841f5b986f677e4fbe2a7ee93c77690d765
  Author: Igor Kirillov <igor.kirillov at arm.com>
  Date:   2024-09-10 (Tue, 10 Sep 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
    A llvm/test/Transforms/VectorCombine/AArch64/shrink-types.ll

  Log Message:
  -----------
  [VectorCombine] Add type shrinking and zext propagation for fixed-width vector types (#104606)

Check that `binop(zext(value)`, other) is possible and profitable to transform
into: `zext(binop(value, trunc(other)))`.
When CPU architecture has illegal scalar type iX, but vector type <N * iX> is
legal, scalar expressions before vectorisation may be extended to a legal
type iY. This extension could result in underutilization of vector lanes,
as more lanes could be used at one instruction with the lower type.
Vectorisers may not always recognize opportunities for type shrinking, and
this patch aims to address that limitation.



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