[all-commits] [llvm/llvm-project] 111932: [RISCV] Fix same mask vmerge peephole discarding f...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 111932d5cae0199d9c59669b37232a011f8b8757
      https://github.com/llvm/llvm-project/commit/111932d5cae0199d9c59669b37232a011f8b8757
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-09 (Mon, 09 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir

  Log Message:
  -----------
  [RISCV] Fix same mask vmerge peephole discarding false operand (#107827)

This fixes the issue raised in
https://github.com/llvm/llvm-project/pull/106108#discussion_r1749677510

True's passthru needs to be equivalent to vmerge's false, but we also
allow true's passthru to be undef.

However if it's undef then we need to replace it with false, otherwise
we end up discarding the false operand entirely.

The changes in fixed-vectors-strided-load-store-asm.ll undo the changes
in #106108 where we introduced this miscompile.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications