[all-commits] [llvm/llvm-project] a96e1a: Don't add 5/6 to AllowedTailExpansions for RV32

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-add-initial-support-of-memcmp-expansion
  Home:   https://github.com/llvm/llvm-project
  Commit: a96e1aaf9a4cbe8e8dd09f4f4b1260b5c63541df
      https://github.com/llvm/llvm-project/commit/a96e1aaf9a4cbe8e8dd09f4f4b1260b5c63541df
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-09-09 (Mon, 09 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

  Log Message:
  -----------
  Don't add 5/6 to AllowedTailExpansions for RV32

Created using spr 1.3.6-beta.1



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