[all-commits] [llvm/llvm-project] 65dc53: [RISCV] Rematerialize vmv.v.i (#107550)

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65dc53baca60b7dd59de36c21f5f5176ea4f2be1
      https://github.com/llvm/llvm-project/commit/65dc53baca60b7dd59de36c21f5f5176ea4f2be1
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-09 (Mon, 09 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/remat.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll

  Log Message:
  -----------
  [RISCV] Rematerialize vmv.v.i (#107550)

This continues the line of work started in #97520, and gives a 2.5%
reduction in the number of spills on SPEC CPU 2017.


    Program            regalloc.NumSpills               
                       lhs                rhs      diff 
             605.mcf_s   141.00             141.00  0.0%
             505.mcf_r   141.00             141.00  0.0%
             519.lbm_r    73.00              73.00  0.0%
             619.lbm_s    68.00              68.00  0.0%
       631.deepsjeng_s   354.00             353.00 -0.3%
       531.deepsjeng_r   354.00             353.00 -0.3%
            625.x264_s  1896.00            1886.00 -0.5%
            525.x264_r  1896.00            1886.00 -0.5%
            508.namd_r  6665.00            6598.00 -1.0%
             644.nab_s   761.00             753.00 -1.1%
             544.nab_r   761.00             753.00 -1.1%
         638.imagick_s  4287.00            4181.00 -2.5%
         538.imagick_r  4287.00            4181.00 -2.5%
             602.gcc_s 12771.00           12450.00 -2.5%
             502.gcc_r 12771.00           12450.00 -2.5%
          510.parest_r 43876.00           42740.00 -2.6%
       500.perlbench_r  4297.00            4179.00 -2.7%
       600.perlbench_s  4297.00            4179.00 -2.7%
         526.blender_r 13503.00           13103.00 -3.0%
          511.povray_r  2006.00            1937.00 -3.4%
         620.omnetpp_s   984.00             946.00 -3.9%
         520.omnetpp_r   984.00             946.00 -3.9%
              657.xz_s   302.00             289.00 -4.3%
              557.xz_r   302.00             289.00 -4.3%
           541.leela_r   378.00             356.00 -5.8%
           641.leela_s   378.00             356.00 -5.8%
       623.xalancbmk_s  1646.00            1548.00 -6.0%
       523.xalancbmk_r  1646.00            1548.00 -6.0%
    Geomean difference                             -2.5%


I initially held off submitting this patch because it surprisingly
introduced a lot of spills in the test diffs, but after #107290 the
vmv.v.is that caused them are now gone.

The gist is that marking vmv.v.i as spillable decreased its spill
weight, which actually resulted in more m8 registers getting evicted and
spilled during register allocation.

The SPEC results show this isn't an issue in practice though, and I plan
on posting a separate patch to explain this in more detail.



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