[all-commits] [llvm/llvm-project] 307713: [AArch64] Do not generate uitofp(ld4) where and/sh...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 307713aafc011844acdcb18ca6acbf3f2de29f5f
      https://github.com/llvm/llvm-project/commit/307713aafc011844acdcb18ca6acbf3f2de29f5f
  Author: David Green <david.green at arm.com>
  Date:   2024-09-07 (Sat, 07 Sep 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/zext-shuffle.ll

  Log Message:
  -----------
  [AArch64] Do not generate uitofp(ld4) where and/shift can be used. (#107538)

After #107201 and #107367 the codegen for zext(ld4) can use and / shift
to extract the lanes out of the original vectors elements. This avoids
the need for the expensive ld4 operations, so can lead to performance
improvements over using the interleaving loads and ushll.

This patch stops the generation of ld4 for uitofp(ld4) that would become
uitofp(zext(ld4)). It doesn't handle zext yet to make sure that widening
instructions like mull and addl are not adversely affected.



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