[all-commits] [llvm/llvm-project] 41b550: DAG: Change round-mode operand type to i32 for FPT...
Mircea Trofin via All-commits
all-commits at lists.llvm.org
Fri Sep 6 17:38:16 PDT 2024
Branch: refs/heads/users/bogner/sprmain.directx-lower-llvmdxtypedbufferload-to-dxil-ops
Home: https://github.com/llvm/llvm-project
Commit: 41b55071a13374654a290c01224eb066c38dc87a
https://github.com/llvm/llvm-project/commit/41b55071a13374654a290c01224eb066c38dc87a
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
DAG: Change round-mode operand type to i32 for FPTRUNC_ROUND (#106424)
We need this immediate type to be consistent. This is the pre-commit for
https://github.com/llvm/llvm-project/pull/105761
Commit: b5977b5318a0d4a926977b40b2e438ccd04d74f2
https://github.com/llvm/llvm-project/commit/b5977b5318a0d4a926977b40b2e438ccd04d74f2
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[gn build] Port 71ede8d83159
Commit: 5a5cf51161865f501ced8e50436773bd96ce7d07
https://github.com/llvm/llvm-project/commit/5a5cf51161865f501ced8e50436773bd96ce7d07
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port 7a4013f029c4
Commit: efbafbc5f28d9ef5a6cea277c8bc71d451e68bbb
https://github.com/llvm/llvm-project/commit/efbafbc5f28d9ef5a6cea277c8bc71d451e68bbb
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/MIR/BUILD.gn
Log Message:
-----------
[gn build] Port f9ad24946026
Commit: 3cf1018f4c66ecd1f98fa6c90c2c4167efc6c9dc
https://github.com/llvm/llvm-project/commit/3cf1018f4c66ecd1f98fa6c90c2c4167efc6c9dc
Author: vporpo <vporpodas at google.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Add test that checks if classof() is missing. (#106313)
Forgetting to implement an `<Instruction Subclass>::classof()` function
does not cause any failures because it falls back to
Instruction::classof(). This patch adds an explicit check for all
instruction classes to confirm that they have a classof implementation.
Commit: 7912abe149c4ba64895a622715fee559d2fda19a
https://github.com/llvm/llvm-project/commit/7912abe149c4ba64895a622715fee559d2fda19a
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
A llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
Log Message:
-----------
[LV] Add extra tests with interleave groups and different insert pos.
Add additional test coverage for interleave groups with different insert
positions.
Commit: b978bcc0f6c598b34f9920a1803e9bba7dff7f94
https://github.com/llvm/llvm-project/commit/b978bcc0f6c598b34f9920a1803e9bba7dff7f94
Author: Connie Zhu <60797237+connieyzhu at users.noreply.github.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M compiler-rt/test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c
Log Message:
-----------
[compiler-rt][test] Rewrote test to remove curly braces (#105696)
This patch removes curly braces from a test, as lit's internal shell
implementation does not support curly brace syntax.
Fixes https://github.com/llvm/llvm-project/issues/102382.
Commit: e03669af239a41f9bec97ac53e46c1b2b72bbe52
https://github.com/llvm/llvm-project/commit/e03669af239a41f9bec97ac53e46c1b2b72bbe52
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M compiler-rt/test/profile/Posix/instrprof-dlopen-norpath.test
Log Message:
-----------
[profile][test] Build Posix/instrprof-dlopen-norpath.test objects as PIC (#106406)
`Profile-x86_64 :: Posix/instrprof-dlopen-norpath.test` `FAILs` on
Solaris/amd64 and similarly on Solaris/sparcv9:
```
RUN: at line 10: ./a.out 2>&1 | FileCheck compiler-rt/test/profile/Posix/instrprof-dlopen-norpath.test -check-prefix=CHECK-FOO
+ ./a.out
+ FileCheck compiler-rt/test/profile/Posix/instrprof-dlopen-norpath.test -check-prefix=CHECK-FOO
compiler-rt/test/profile/Posix/instrprof-dlopen-norpath.test:24:12: error: CHECK-FOO: expected string not found in input
CHECK-FOO: foo:
^
<stdin>:1:1: note: scanning from here
unable to lookup symbol 'foo': ld.so.1: a.out: invalid handle: 0x0
```
The problem turned out to be two-fold: `OPEN_AND_RUN` didn't check the
`dlopen` return value and the objects linked into the shared objects to
be `dlopen`ed aren't built as PIC.
This patch fixes the latter.
Tested on `amd64-pc-solaris2.11`, `sparcv9-sun-solaris2.11`, and
`x86_64-pc-linux-gnu`.
Commit: c43190f99445b1b76d06b650247d72fc109b5d4b
https://github.com/llvm/llvm-project/commit/c43190f99445b1b76d06b650247d72fc109b5d4b
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
Log Message:
-----------
[RISCV] Add cost model coverage for insert/extract element w/ 2^N - 1 types
We currently return costs which are too low for these.
Commit: 2d1fba67c54b7c6b7f57635f863d4e1cd5fcc048
https://github.com/llvm/llvm-project/commit/2d1fba67c54b7c6b7f57635f863d4e1cd5fcc048
Author: Denis.G <34353767+DenisGZM at users.noreply.github.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsNVPTX.def
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/__clang_cuda_device_functions.h
M clang/test/CodeGen/builtins-nvptx.c
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
A llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
[NVPTX] Support __usAtomicCAS builtin (#99646)
Supported `__usAtomicCAS` builtin originally defined in
`/usr/local/cuda/inlcude/crt/sm_70_rt.hpp`
---------
Co-authored-by: Denis Gerasimov <Denis.Gerasimov at baikalelectronics.ru>
Co-authored-by: Gonzalo Brito Gadeschi <gonzalob at nvidia.com>
Co-authored-by: Denis.Gerasimov <dengzmm at gmail.com>
Commit: e61d6066e2678b1244b1bcbd59a154a82acf1eb8
https://github.com/llvm/llvm-project/commit/e61d6066e2678b1244b1bcbd59a154a82acf1eb8
Author: Kazu Hirata <kazu at google.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/FunctionImport.h
Log Message:
-----------
[LTO] Turn ImportListsTy into a proper class (NFC) (#106427)
This patch turns ImportListsTy into a class that wraps
DenseMap<StringRef, ImportMapTy>.
Here is the background. I'm planning to reduce the memory footprint
of ThinLTO indexing. Specifically, ImportMapTy, the list of imports
for a given destination module, will be a hash set of integer IDs
indexing into a deduplication table of pairs (SourceModule, GUID),
which is a lot like string interning. I'm planning to put this
deduplication table as part of ImportListsTy and have each instance of
ImportMapTy hold a reference to the deduplication table.
Another reason to wrap the DenseMap is that I need to intercept
operator[]() so that I can construct an instance of ImportMapTy with a
reference to the deduplication table. Note that the default
implementation of operator[]() would default-construct ImportMapTy,
which I am going to disable.
Commit: aa7497a66c4272669fa63f7ec61a3f01aa9dabaf
https://github.com/llvm/llvm-project/commit/aa7497a66c4272669fa63f7ec61a3f01aa9dabaf
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/CodeCompletion/variadic-template.cpp
M clang/test/Index/complete-call.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
A clang/test/SemaTemplate/GH18291.cpp
M clang/test/SemaTemplate/cwg2398.cpp
M clang/test/SemaTemplate/temp_arg_nontype.cpp
M clang/test/SemaTemplate/temp_arg_type.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
Log Message:
-----------
[clang] check deduction consistency when partial ordering function templates (#100692)
This makes partial ordering of function templates consistent with other
entities, by implementing [temp.deduct.type]p1 in that case.
Fixes #18291
Commit: 6b4b8dc4a45dccec43a9c0d76a80ebae50df55b0
https://github.com/llvm/llvm-project/commit/6b4b8dc4a45dccec43a9c0d76a80ebae50df55b0
Author: aws-taylor <57725958+aws-taylor at users.noreply.github.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/include/llvm/ADT/STLExtras.h
M llvm/unittests/ADT/STLExtrasTest.cpp
Log Message:
-----------
[ADT] Relax iterator constraints on all_equal (#106400)
The previous `all_equal` implementation contained `Begin + 1`, which
implicitly requires `Begin` to model the
[random_access_iterator](https://en.cppreference.com/w/cpp/iterator/random_access_iterator)
concept due to the usage of the `+` operator. By swapping this out with
`std::next`, this method can be used with weaker iterator concepts, such
as
[forward_iterator](https://en.cppreference.com/w/cpp/iterator/forward_iterator).
---------
Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
Commit: ec360d6523f029c406aee6a8b4325b941ea417ac
https://github.com/llvm/llvm-project/commit/ec360d6523f029c406aee6a8b4325b941ea417ac
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Add getValueType function and use instead of complex scalar type analysis
Commit: 898d52b819496ba70d0ca29cc7b60237108ae2b4
https://github.com/llvm/llvm-project/commit/898d52b819496ba70d0ca29cc7b60237108ae2b4
Author: Chris Apple <cja-private at pm.me>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors.cpp
Log Message:
-----------
[compiler-rt][rtsan] Fix failing file permissions test by checking umask (#106095)
This reverts:
d8d8d659685b114f31d1c42d6d18c3bc6d98b171
Commit: e99aa4a500b0f271b327432d404a9c1f72c6850a
https://github.com/llvm/llvm-project/commit/e99aa4a500b0f271b327432d404a9c1f72c6850a
Author: Amr Hesham <amr96 at programmer.net>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl
M clang/test/CodeGenHLSL/builtins/all.hlsl
M clang/test/CodeGenHLSL/builtins/any.hlsl
M clang/test/CodeGenHLSL/builtins/frac.hlsl
M clang/test/CodeGenHLSL/builtins/lerp.hlsl
M clang/test/CodeGenHLSL/builtins/normalize.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
M clang/test/CodeGenHLSL/semantics/DispatchThreadID.hlsl
Log Message:
-----------
[clang][HLSL] Update DXIL/SPIRV hybird CodeGen tests to use temp var (#105930)
Update all hybird DXIL/SPIRV codegen tests to use temp variable
representing interchange target
Fixes: #105710
Commit: 17b7a9da46cef85b1a00b574c18c5f8cd5a761e1
https://github.com/llvm/llvm-project/commit/17b7a9da46cef85b1a00b574c18c5f8cd5a761e1
Author: Angel Zhang <angel.zhang at amd.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
A mlir/test/mlir-vulkan-runner/argmax.mlir
M mlir/tools/mlir-vulkan-runner/CMakeLists.txt
M mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][spirv] Add an argmax integration test with `mlir-vulkan-runner` (#106426)
This PR adds an integration test for an argmax kernel with
`mlir-vulkan-runner`. This test exercises the `convert-to-spirv` pass
(landed in #95942) and demonstrates that we can use SPIR-V ops as
"intrinsics" among higher-level dialects.
The support for `index` dialect in `mlir-vulkan-runner` is also added.
Commit: 38b252aa45abad53d7c07c666569b174a215d94d
https://github.com/llvm/llvm-project/commit/38b252aa45abad53d7c07c666569b174a215d94d
Author: jeffreytan81 <jeffreytan at meta.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M lldb/include/lldb/Target/ThreadPlan.h
M lldb/include/lldb/Target/ThreadPlanStepOverBreakpoint.h
M lldb/source/Target/ThreadPlanSingleThreadTimeout.cpp
M lldb/source/Target/ThreadPlanStepOverBreakpoint.cpp
Log Message:
-----------
Disable ThreadPlanSingleThreadTimeout during step over breakpoint (#104532)
This PR fixes another race condition in
https://github.com/llvm/llvm-project/pull/90930. The failure was found
by @labath with this log: https://paste.debian.net/hidden/30235a5c/:
```
dotest_wrapper. < 15> send packet: $z0,224505,1#65
...
b-remote.async> < 22> send packet: $vCont;s:p1dcf.1dcf#4c
intern-state GDBRemoteClientBase::Lock::Lock sent packet: \x03
b-remote.async> < 818> read packet: $T13thread:p1dcf.1dcf;name:a.out;threads:1dcf,1dd2;jstopinfo:5b7b226e616d65223a22612e6f7574222c22726561736f6e223a227369676e616c222c227369676e616c223a31392c22746964223a373633317d2c7b226e616d65223a22612e6f7574222c22746964223a373633347d5d;thread-pcs:0000000000224505,00007f4e4302119a;00:0000000000000000;01:0000000000000000;02:0100000000000000;03:0000000000000000;04:9084997dfc7f0000;05:a8742a0000000000;06:b084997dfc7f0000;07:6084997dfc7f0000;08:0000000000000000;09:00d7e5424e7f0000;0a:d0d9e5424e7f0000;0b:0202000000000000;0c:80cc290000000000;0d:d8cc1c434e7f0000;0e:2886997dfc7f0000;0f:0100000000000000;10:0545220000000000;11:0602000000000000;12:3300000000000000;13:0000000000000000;14:0000000000000000;15:2b00000000000000;16:80fbe5424e7f0000;17:0000000000000000;18:0000000000000000;19:0000000000000000;reason:signal;#b9
```
It shows an async interrupt "\x03" was sent immediately after `vCont;s`
single step over breakpoint at address `0x224505` (which was disabled
before vCont). And the later stop was still at the original PC
(0x224505) not moving forward.
The investigation shows the failure happens when timeout is short and
async interrupt is sent to lldb-server immediately after vCont so
ptrace() resumes and then async interrupts debuggee immediately so
debuggee does not get a chance to execute and move PC. So it enters stop
mode immediately at original PC. `ThreadPlanStepOverBreakpoint` does not
expect PC not moving and reports stop at the original place.
To fix this, the PR prevents `ThreadPlanSingleThreadTimeout` from being
created during `ThreadPlanStepOverBreakpoint` by introduces a new
`SupportsResumeOthers()` method and `ThreadPlanStepOverBreakpoint`
returns false for it. This makes sense because we should never resume
threads during step over breakpoint anyway otherwise it might cause
other threads to miss breakpoint.
---------
Co-authored-by: jeffreytan81 <jeffreytan at fb.com>
Commit: 0281339159e6ef0c30acbf146e9c3b06482191c1
https://github.com/llvm/llvm-project/commit/0281339159e6ef0c30acbf146e9c3b06482191c1
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
Log Message:
-----------
Revert "[CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC)" (#106451)
Reverts llvm/llvm-project#106404
Breaks:
https://lab.llvm.org/buildbot/#/builders/169/builds/2590
https://lab.llvm.org/buildbot/#/builders/164/builds/2454
Commit: 53d95f3056199b4a9668104c63080d4c94926162
https://github.com/llvm/llvm-project/commit/53d95f3056199b4a9668104c63080d4c94926162
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
R llvm/test/CodeGen/AMDGPU/fail.llvm.fptrunc.round.ll
A llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
Log Message:
-----------
AMDGPU: Rename fail.llvm.fptrunc.round.ll to llvm.fptrunc.round.err.ll (#106452)
Also correct the suffix of the intrinsic
Commit: eb9c49c900f43aa79811f80847c97c6596197430
https://github.com/llvm/llvm-project/commit/eb9c49c900f43aa79811f80847c97c6596197430
Author: Kazu Hirata <kazu at google.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/FunctionImport.h
M llvm/lib/Transforms/IPO/FunctionImport.cpp
Log Message:
-----------
[LTO] Make getImportType a proper function (NFC) (#106450)
I'm planning to reduce the memory footprint of ThinLTO indexing by
changing ImportMapTy. A look-up of the import type will involve data
private to ImportMapTy, so it must be done by a member function of
ImportMapTy. This patch turns getImportType into a member function so
that a subsequent "real" change will just have to update the
implementation of the function in place.
Commit: 26c582bb452eadc3870c56e8eae24feb354a2edf
https://github.com/llvm/llvm-project/commit/26c582bb452eadc3870c56e8eae24feb354a2edf
Author: Greg Roth <grroth at microsoft.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M clang/lib/Basic/Targets/DirectX.h
A clang/test/CodeGenHLSL/static-local-ctor.hlsl
Log Message:
-----------
[DXIL] Don't generate per-variable guards for DirectX (#106096)
Thread init guards are generated for local static variables when using
the Microsoft CXX ABI. This ABI is also used for HLSL generation, but
DXIL doesn't need the corresponding _Init_thread_header/footer calls and
doesn't really have a way to handle them in its output targets.
This modifies the language ops when the target is DXIL to exclude this
so that they won't be generated and an alternate guardvar method is used
that is compatible with the usage.
Done to facilitate testing for #89806, but isn't really related
Commit: 18c79ca3607bfe9cc6fd083186f3b462f5abff7e
https://github.com/llvm/llvm-project/commit/18c79ca3607bfe9cc6fd083186f3b462f5abff7e
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV][NFC] Remove unnecessary space in comment
Commit: 1bc7057a8eb7400dfbb1fc8335efa41abab9884e
https://github.com/llvm/llvm-project/commit/1bc7057a8eb7400dfbb1fc8335efa41abab9884e
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
R mlir/test/mlir-vulkan-runner/argmax.mlir
M mlir/tools/mlir-vulkan-runner/CMakeLists.txt
M mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Revert "[mlir][spirv] Add an argmax integration test with `mlir-vulkan-runner`" (#106457)
Reverts llvm/llvm-project#106426.
This caused failures on nvidia:
https://lab.llvm.org/buildbot/#/builders/138/builds/2853
Commit: ee0d70633872a30175cf29f81de7b2dbf771d708
https://github.com/llvm/llvm-project/commit/ee0d70633872a30175cf29f81de7b2dbf771d708
Author: yronglin <yronglin777 at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
A clang/test/AST/ByteCode/constexpr-vectors.cpp
Log Message:
-----------
[clang][bytecode] Implement constexpr vector unary operators +, -, ~, ! (#105996)
Implement constexpr vector unary operators +, -, ~ and ! .
- Follow the current constant interpreter. All of our boolean operations
on vector types should be '-1' for the 'truth' type.
- Move the following functions from `Sema` to `ASTContext`, because we
used it in new interpreter.
```C++
QualType GetSignedVectorType(QualType V);
QualType GetSignedSizelessVectorType(QualType V);
```
---------
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: 13fa78c86d6b7ffcd9b7e21bbe9529f57efc3278
https://github.com/llvm/llvm-project/commit/13fa78c86d6b7ffcd9b7e21bbe9529f57efc3278
Author: Mike Rice <michael.p.rice at intel.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M clang/lib/Parse/ParseOpenMP.cpp
Log Message:
-----------
[OpenMP][NFC] Remove executable cases from declaration switch (#106438)
The executable directives are handled earlier.
Commit: 431db183e86b5adc72d0d2aad3ced239b4c94a60
https://github.com/llvm/llvm-project/commit/431db183e86b5adc72d0d2aad3ced239b4c94a60
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
Log Message:
-----------
[RISCV] Remove effectively duplicate RUN lines form fixed-vectors-fp.ll. NFC
We had RUN lines with +v,+f and +v,+f,+d. +v implies +f and +d so
these are equivalent.
Commit: a7ba73bf614f6d147bd1cdaddee156bd85e31703
https://github.com/llvm/llvm-project/commit/a7ba73bf614f6d147bd1cdaddee156bd85e31703
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
Log Message:
-----------
[RISCV] Fix conflicting CHECK prefixes in fixed-vectors-fp.ll. NFC
Commit: 75e9d191f52b047ea839f75ab2a7a7d9f8c6becd
https://github.com/llvm/llvm-project/commit/75e9d191f52b047ea839f75ab2a7a7d9f8c6becd
Author: William Junda Huang <williamjhuang at google.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-profdata.rst
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/include/llvm/ProfileData/SampleProfWriter.h
M llvm/lib/ProfileData/SampleProfReader.cpp
M llvm/lib/ProfileData/SampleProfWriter.cpp
A llvm/test/tools/llvm-profdata/Inputs/split-layout.profdata
A llvm/test/tools/llvm-profdata/sample-split-layout.test
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[llvm-profdata] Enabled functionality to write split-layout profile (#101795)
Using the flag `-split_layout` in llvm-profdata merge, the output
profile can write profiles with and without inlined function into two
different extbinary sections (and their FuncOffsetTable too). The
section without inlined functions are marked with `SecFlagFlat` and is
skipped by ThinLTO because it provides no useful info.
The split layout feature was already implemented in SampleProfWriter but
previously there is no way to use it from llvm-profdata.
Commit: b75fe11fd6fe751157012a8881ece2f247bd3887
https://github.com/llvm/llvm-project/commit/b75fe11fd6fe751157012a8881ece2f247bd3887
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/tools/llvm-pdbutil/ExplainOutputStyle.cpp
M llvm/utils/TableGen/IntrinsicEmitter.cpp
M mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp
M mlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
Log Message:
-----------
[NFC] Fix formatv() usage in preparation of validation (#106454)
Fix several uses of formatv() that would be flagged as invalid by an
upcoming change that will add additional validation to formatv().
Commit: 3a5c5789662d50814e1867ac7c196dd7e7ac782c
https://github.com/llvm/llvm-project/commit/3a5c5789662d50814e1867ac7c196dd7e7ac782c
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/MachineLoopInfo.cpp
M llvm/test/CodeGen/X86/code-align-loops.ll
Log Message:
-----------
[MachineLoopInfo] Fix getLoopID to handle multi latches. (#106195)
This patch also fixed `CodegenPrepare` to preserve loop metadata when
merging blocks.
This fixes issue #102632
Commit: 8927576b8f6442bb6129bda597efee46176f8aec
https://github.com/llvm/llvm-project/commit/8927576b8f6442bb6129bda597efee46176f8aec
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M .github/workflows/release-binaries.yml
M clang/cmake/caches/Release.cmake
Log Message:
-----------
workflows/release-binaries: Enable flang builds on Windows (#101344)
Flang for Windows depends on compiler-rt, so we need to enable it for
the stage1 builds. This also fixes failures building the flang tests on
macOS.
Fixes #100202.
Commit: 438ad9f2bf25575c474313de4ad85a5da6f69e4c
https://github.com/llvm/llvm-project/commit/438ad9f2bf25575c474313de4ad85a5da6f69e4c
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Revert "[clang-format][NFC] Delete TT_LambdaArrow (#70… (#105923)
…519)"
This reverts commit e00d32afb9d33a1eca48e2b041c9688436706c5b and adds a
test for lambda arrow SplitPenalty.
Fixes #105480.
Commit: 87c86aa6b93aea3d1603c1759a17fb6b5ba6e814
https://github.com/llvm/llvm-project/commit/87c86aa6b93aea3d1603c1759a17fb6b5ba6e814
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SimplifyCFGOptions.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Other/new-pm-print-pipeline.ll
A llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops-with-cf.ll
A llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
Log Message:
-----------
[X86,SimplifyCFG] Support hoisting load/store with conditional faulting (Part I) (#96878)
This is simplifycfg part of
https://github.com/llvm/llvm-project/pull/95515
In this PR, we support hoisting load/store with conditional faulting in
`SimplifyCFGOpt::speculativelyExecuteBB` to eliminate conditional
branches.
This is for cases like
```
void test (int a, int *b) {
if (a)
*b = a;
}
```
In the following patches, we will support the hoist in
`SimplifyCFGOpt::hoistCommonCodeFromSuccessors`.
That is for cases like
```
void test (int a, int *c, int *d) {
if (a)
*c = a;
else
*d = a;
}
```
Commit: 121fb2c2ccc9db33278160b485ff0e9d09be9827
https://github.com/llvm/llvm-project/commit/121fb2c2ccc9db33278160b485ff0e9d09be9827
Author: tcwzxx <tcwzxx at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/insertelement-across-zero.ll
Log Message:
-----------
[SLP] Fix the Vec lane overridden by the shuffle mask (#106341)
Currently, SLP uses shuffle for the external user of `InsertElementInst`
and iterates through the `InsertElementInst` chain to fill the mask with
constant indices. However, it may override the original Vec lane. Using
the original Vec lane is sufficient.
Commit: ee6961dbf13167bf09b602b136d72f72d7c8ff0c
https://github.com/llvm/llvm-project/commit/ee6961dbf13167bf09b602b136d72f72d7c8ff0c
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M clang-tools-extra/clangd/CollectMacros.cpp
M clang-tools-extra/clangd/CollectMacros.h
M clang-tools-extra/clangd/ParsedAST.cpp
M clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
Log Message:
-----------
[clangd] Do not collect macros when clang-tidy checks call into the preprocessor (#106329)
Fixes https://github.com/llvm/llvm-project/issues/99617
Commit: 82ebd333a889d2372c8445dc3d5d527ec48537db
https://github.com/llvm/llvm-project/commit/82ebd333a889d2372c8445dc3d5d527ec48537db
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py
Log Message:
-----------
[LLDB][Minidumps] Read x64 registers as 64b and handle truncation in the file builder (#106473)
This patch addresses a bug where `cs`/`fs` and other segmentation flags
were being identified as having a type of `32b` and `64b` for `rflags`.
In that case the register value was returning the fail value `0xF...`
and this was corrupting some minidumps. Here we just read it as a 64b
value and truncate it.
In addition to that fix, I added comparing the registers from the live
process to the loaded core for the generic minidump test. Prior only
being ARM register tests. This explains why this was not detected
before.
Commit: 8bf69ceb00bb56dd5c7357f192846518a6893f3c
https://github.com/llvm/llvm-project/commit/8bf69ceb00bb56dd5c7357f192846518a6893f3c
Author: Christopher Bate <cbate at nvidia.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M mlir/lib/Conversion/AffineToStandard/CMakeLists.txt
M mlir/lib/Conversion/ComplexToLLVM/CMakeLists.txt
M mlir/lib/Conversion/ControlFlowToSCF/CMakeLists.txt
M mlir/lib/Conversion/SCFToControlFlow/CMakeLists.txt
M mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt
M mlir/lib/Conversion/VectorToSCF/CMakeLists.txt
M mlir/lib/Dialect/Affine/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Complex/IR/CMakeLists.txt
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
M mlir/lib/Dialect/MemRef/IR/CMakeLists.txt
M mlir/lib/Dialect/MemRef/TransformOps/CMakeLists.txt
M mlir/lib/Dialect/MemRef/Transforms/CMakeLists.txt
M mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Tensor/IR/CMakeLists.txt
Log Message:
-----------
Reapply "[mlir] NFC: fix dependence of (Tensor|Linalg|MemRef|Complex) dialects on LLVM Dialect and LLVM Core in CMake build (#104832)" (#105703)
Reapply the commit 43b508566799751aa180f1eaaafc5be693f2f1ae with
additional fixes for building with
BUILD_SHARED_LIBS=ON.
Commit: 55cdb3c785ad688054493bb82c0cf3b9d7ccea07
https://github.com/llvm/llvm-project/commit/55cdb3c785ad688054493bb82c0cf3b9d7ccea07
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/Type.h
M clang/include/clang/Sema/ExternalSemaSource.h
M clang/include/clang/Sema/MultiplexExternalSemaSource.h
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/Sema/MultiplexExternalSemaSource.cpp
M clang/lib/Serialization/ASTReader.cpp
A clang/test/Modules/pr102721.cppm
Log Message:
-----------
[C++20] [Modules] Merge lambdas in source to imported lambdas (#106483)
Close https://github.com/llvm/llvm-project/issues/102721
Generally, the type of merged decls will be reused in ASTContext. But
for lambda, in the import and then include case, we can't decide its
previous decl in the imported modules so that we can't assign the
previous decl before creating the type for it. Since we can't decide its
numbering before creating it. So we have to assign the previous decl and
the canonical type for it after creating it, which is unusual and
slightly hack.
Commit: 619efd75da77415e016c79c37a0fabe573ce1845
https://github.com/llvm/llvm-project/commit/619efd75da77415e016c79c37a0fabe573ce1845
Author: Luke Lau <luke at igalia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
A llvm/test/CodeGen/RISCV/rvv/pr106109.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
Log Message:
-----------
[RISCV] Fix v[f]slide1down.vx having VL changed (#106110)
v[f]slide1down.vx uses VL to determine where the element is inserted
into, so changing the VL changes the result.
This fixes this by setting ActiveElementsAffectsResult, but it's overly
conservative. We should relax this later by modelling that it's ok to
change the mask, just not VL.
Fixes #106109
Commit: 051054e6f74303bc880221e88671745f363964cc
https://github.com/llvm/llvm-project/commit/051054e6f74303bc880221e88671745f363964cc
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
Log Message:
-----------
[clang][RISCV] Remove `experimental` for vector crypto intrinsics (#106359)
The C intrinsic spec is ratified:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234.
Commit: 572d2fd327b3a55fe57f712813321a3c40c895cd
https://github.com/llvm/llvm-project/commit/572d2fd327b3a55fe57f712813321a3c40c895cd
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
A llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
Log Message:
-----------
[Attributor] Fix an issue that could potentially cause `AccessList` and `OffsetBins` out of sync (#106187)
The implementation of `AAPointerInfo::RangeList::set_difference` doesn't
consider the case where two ranges have the same offset but different
sizes.
This could cause `AccessList` and `OffsetBins` out of sync because a
range has
been already updated in `AccessList` but missing in `ToRemove`.
I do have a reproducer but the reproducer itself is 248kb. `llvm-reduce`
can't
further reduce it. Not sure how I can make a smaller reproducer.
Fixes: SWDEV-479757.
Commit: 9d81e7e36e33aecdee05fef551c0652abafaa052
https://github.com/llvm/llvm-project/commit/9d81e7e36e33aecdee05fef551c0652abafaa052
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
Log Message:
-----------
workflows/release-tasks: Pass required secrets to all called workflows (#106286)
Called workflows don't have access to secrets by default, so we need to
explicitly pass secrets that we use.
Commit: 95361cf3306760378c4798963405ed4cd6410f15
https://github.com/llvm/llvm-project/commit/95361cf3306760378c4798963405ed4cd6410f15
Author: Christopher Bate <cbate at nvidia.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M mlir/lib/Conversion/SCFToControlFlow/CMakeLists.txt
Log Message:
-----------
[mlir] fix missing LLVMDialect dependency for MLIRSCFToControlFlow
This is a fix-forward for 8bf69ceb00bb56dd5c7357f192846518a6893f3c.
The SCF-to-ControlFlow pass has an explicit LLVMDialect dependency.
Commit: 62c5de36e8a523cc81950a782a4b6182393681c4
https://github.com/llvm/llvm-project/commit/62c5de36e8a523cc81950a782a4b6182393681c4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Log Message:
-----------
[RISCV] Fix a place that convert an immediate to MCRegister and back to immediate.
This dropped the upper 32 bits of the immediate, but I'm not sure
it is ever non-zero.
Commit: 2adc94cd6c3dd1fc713a6ba8301fc04f21908700
https://github.com/llvm/llvm-project/commit/2adc94cd6c3dd1fc713a6ba8301fc04f21908700
Author: Akshat Oke <76596238+Akshat-Oke at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
A llvm/lib/Target/AMDGPU/SIFoldOperands.h
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
M llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
Log Message:
-----------
AMDGPU/NewPM: Port SIFoldOperands to new pass manager (#105801)
Commit: 3b64ede096ce0a0230c4d3f77782e6fa18f2943a
https://github.com/llvm/llvm-project/commit/3b64ede096ce0a0230c4d3f77782e6fa18f2943a
Author: Luke Lau <luke at igalia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
Log Message:
-----------
[RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv (#104574)
As far as I'm aware, vrgather.vv is quadratic in LMUL on most
microarchitectures today due to each output register needing to read
from each input register in the group.
For example, the reciprocal throughput for vrgather.vv on the
spacemit-x60 is listed on
https://camel-cdr.github.io/rvv-bench-results/bpi_f3 as:
LMUL1 LMUL2 LMUL4 LMUL8
4.0 16.0 64.0 256.1
Vector reverses are commonly emitted by the loop vectorizer and are
lowered as vrgather.vvs, but since the loop vectorizer uses LMUL 2 by
default they end up being quadratic.
The output registers in a reverse only need to read from one input
register though, so we can decompose this into LMUL * M1 vrgather.vvs to
get linear performance.
This gives a 0.43% runtime improvement on 526.blender_r at rva22u64_v O3
on the Banana Pi F3.
Commit: 8f96be921c1a97594ee94c2789cee9b131525f63
https://github.com/llvm/llvm-project/commit/8f96be921c1a97594ee94c2789cee9b131525f63
Author: Lang Hames <lhames at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/tools/bugpoint/CMakeLists.txt
Log Message:
-----------
[bugpoint] Fix bugpoint for LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES=Off.
Building with -DLLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES=Off should not
prevent use of bugpoint plugins.
This fix uses the approach implemented in
https://github.com/llvm/llvm-project/pull/101741.
Commit: c7a4efa4294789b1116f0c4a320c16fcb27cb62c
https://github.com/llvm/llvm-project/commit/c7a4efa4294789b1116f0c4a320c16fcb27cb62c
Author: Patryk Wychowaniec <pwychowaniec at pm.me>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
A llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
A llvm/test/CodeGen/AVR/std-immediate-overflow.ll
Log Message:
-----------
[AVR] Fix 16-bit LDDs with immediate overflows (#104923)
16-bit loads are expanded into a pair of 8-bit loads, so the maximum
offset of such 16-bit loads must be 62, not 63.
Commit: 7f59264d469d690fcd1cead0a2dfc02739d17db4
https://github.com/llvm/llvm-project/commit/7f59264d469d690fcd1cead0a2dfc02739d17db4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/test/Transforms/SCCP/pointer-nonnull.ll
M llvm/test/Transforms/SCCP/range-attribute.ll
Log Message:
-----------
[IPSCCP] Intersect attribute info for interprocedural args (#106397)
IPSCCP can currently return worse results than SCCP for arguments that
are tracked interprocedurally, because information from attributes is
not used for them.
Fix this by intersecting in the attribute information when propagating
lattice values from calls.
Commit: c954306ef763eb25f06432324889bde98735963d
https://github.com/llvm/llvm-project/commit/c954306ef763eb25f06432324889bde98735963d
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_console.py
Log Message:
-----------
[lldb][lldb-dap][test] Enable more tests on Windows
These tests "just work" on our Windows On Arm machine.
Commit: 47615ff2347a8be429404285de3b1c03b411e7af
https://github.com/llvm/llvm-project/commit/47615ff2347a8be429404285de3b1c03b411e7af
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/pr106483.cppm
Log Message:
-----------
[C++20] [Modules] Don't insert class not in named modules to PendingEmittingVTables (#106501)
Close https://github.com/llvm/llvm-project/issues/102933
The root cause of the issue is an oversight in
https://github.com/llvm/llvm-project/pull/102287 that I didn't notice
that PendingEmittingVTables should only accept classes in named modules.
Commit: e5b55e606796bac0e28e2f0fdc6fb39a419f6b15
https://github.com/llvm/llvm-project/commit/e5b55e606796bac0e28e2f0fdc6fb39a419f6b15
Author: Lang Hames <lhames at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/tools/clang-repl/CMakeLists.txt
Log Message:
-----------
[clang-repl] Fix clang-repl for LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES=Off.
clang-repl should stil work when LLVM is built with
-DLLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES=Off.
This fix uses the approach implemented in
https://github.com/llvm/llvm-project/pull/101741.
rdar://134910110
Commit: 2eeeff842f993a694159183a2834b4d305549cad
https://github.com/llvm/llvm-project/commit/2eeeff842f993a694159183a2834b4d305549cad
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/test/Modules/no-local-decl-in-reduced-bmi.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview-std.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview.cppm
M clang/test/Modules/unreached-static-entities.cppm
Log Message:
-----------
[C++20] [Modules] Embed all source files for C++20 Modules (#102444)
Close https://github.com/llvm/llvm-project/issues/72383
The implementation rationale is, I don't want to pass
`-fmodules-embed-all-files` all the time since we can't test it in lit
tests (we're using `clang_cc1`). So I tried to set it in FrontendActions
for modules.
Commit: b822b69ff54bcd2f08445bd02b8dad0584422874
https://github.com/llvm/llvm-project/commit/b822b69ff54bcd2f08445bd02b8dad0584422874
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
M clang/test/Driver/print-multi-selection-flags.c
Log Message:
-----------
[Driver] Add -mbranch-protection to ARM and AArch64 multilib flags (#106391)
This adds the `-mbranch-protection` command line option to the set of
flags used by the multilib selection for ARM and AArch64 targets.
Commit: b7981a78f0aaea1500d79a519c0be03c69d9b1ac
https://github.com/llvm/llvm-project/commit/b7981a78f0aaea1500d79a519c0be03c69d9b1ac
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/MeshShardingInterfaceImpl.cpp
Log Message:
-----------
[mlir] Apply ClangTidyPerformance finding (NFC).
Use const reference for loop variable.
Commit: efad561890ad3584c38adae913f9939384eb804c
https://github.com/llvm/llvm-project/commit/efad561890ad3584c38adae913f9939384eb804c
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/Chunks.h
M lld/COFF/Writer.cpp
A lld/test/COFF/arm64ec-range-thunks.s
Log Message:
-----------
[LLD][COFF] Add support for range extension thunks for ARM64EC targets. (#106289)
Thunks themselves are the same as regular ARM64 thunks; they just need
to report the correct machine type. When processing the code, we also
need to use the current chunk's machine type instead of the global one:
we don't want to treat x86_64 thunks as ARM64EC, and we need to report
the correct machine type in hybrid binaries.
Commit: f9ee9f5b39b3840e5fd6bb54ebb7830a98f8f0af
https://github.com/llvm/llvm-project/commit/f9ee9f5b39b3840e5fd6bb54ebb7830a98f8f0af
Author: VisdaVokhshoori <31481804+VisdaVokhshoori at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/docs/TestSuiteGuide.md
Log Message:
-----------
[llvm][Docs] Update TestSuiteGuide.md (#79613)
Update svn to git & virtualenv to venv
Commit: ae34257e9015a366ea63cd461535b35bc9837c57
https://github.com/llvm/llvm-project/commit/ae34257e9015a366ea63cd461535b35bc9837c57
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
Log Message:
-----------
[lldb][lldb-dap][test] Skip logpoint test on Windows again
This one snuck into the previous patch. The test program needs
updating if it's ever going to work on Windows.
Commit: c9b6e01b2e4fc930dac91dd44c0592ad7e36d967
https://github.com/llvm/llvm-project/commit/c9b6e01b2e4fc930dac91dd44c0592ad7e36d967
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize-with-call.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize.ll
R llvm/test/tools/llvm-split/AMDGPU/debug-name-hiding.ll
R llvm/test/tools/llvm-split/AMDGPU/debug-non-kernel-root.ll
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-alias-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-cost-ranking.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-external.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-overridable.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables-noexternal.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependency-indirect.ll
A llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
A llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
Log Message:
-----------
[AMDGPU] Graph-based Module Splitting Rewrite (#104763)
Major rewrite of the AMDGPUSplitModule pass in order to better support
it long-term.
Highlights:
- Removal of the "SML" logging system in favor of just using CL options
and LLVM_DEBUG, like any other pass in LLVM.
- The SML system started from good intentions, but it was too flawed and
messy to be of any real use. It was also a real pain to use and made the
code more annoying to maintain.
- Graph-based module representation with DOTGraph printing support
- The graph represents the module accurately, with bidirectional, typed
edges between nodes (a node usually represents one function).
- Nodes are assigned IDs starting from 0, which allows us to represent a
set of nodes as a BitVector. This makes comparing 2 sets of nodes to
find common dependencies a trivial task. Merging two clusters of nodes
together is also really trivial.
- No more defaulting to "P0" for external calls
- Roots that can reach non-copyable dependencies (such as external
calls) are now grouped together in a single "cluster" that can go into
any partition.
- No more defaulting to "P0" for indirect calls
- New representation for module splitting proposals that can be graded
and compared.
- Graph-search algorithm that can explore multiple branches/assignments
for a cluster of functions, up to a maximum depth.
- With the default max depth of 8, we can create up to 256 propositions
to try and find the best one.
- We can still fall back to a greedy approach upon reaching max depth.
That greedy approach uses almost identical heuristics to the previous
version of the pass.
All of this gives us a lot of room to experiment with new heuristics or
even entirely different splitting strategies if we need to. For
instance, the graph representation has room for abstract nodes, e.g. if
we need to represent some global variables or external constraints. We
could also introduce more edge types to model other type of relations
between nodes, etc.
I also designed the graph representation & the splitting strategies to
be as fast as possible, and it seems to have paid off. Some quick tests
showed that we spend pretty much all of our time in the CloneModule
function, with the actual splitting logic being >1% of the runtime.
Commit: e37d6d2a74d76fdc95f5c5d625e282ce600aad55
https://github.com/llvm/llvm-project/commit/e37d6d2a74d76fdc95f5c5d625e282ce600aad55
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir
M mlir/test/Dialect/ArmSME/tile-zero-masks.mlir
Log Message:
-----------
[mlir][ArmSME] Merge consecutive `arm_sme.intr.zero` ops (#106215)
This merges consecutive SME zero intrinsics within a basic block, which
avoids the backend eventually emitting multiple zero instructions when
it could just use one.
Note: This kind of peephole optimization could be implemented in the
backend too.
Commit: 31684c676a9983277666df2ac845a563f4d68e19
https://github.com/llvm/llvm-project/commit/31684c676a9983277666df2ac845a563f4d68e19
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
R llvm/test/tools/llvm-split/AMDGPU/declarations-debug.ll
Log Message:
-----------
[AMDGPU][llvm-split] Remove declarations-debug
Test didn't have a FileCheck line and is obsolete after #104763
Commit: b9f4afa1674fe6f101b298d4893cde2ab2d16877
https://github.com/llvm/llvm-project/commit/b9f4afa1674fe6f101b298d4893cde2ab2d16877
Author: Daniel Grumberg <dgrumberg at apple.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/ExtractAPI/API.h
M clang/lib/ExtractAPI/API.cpp
Log Message:
-----------
[clang][ExtractAPI] Fix iteration order of TopLevelRecords (#106411)
Fixes #106355
Commit: 575be3efb056b298bd4cbf9a04c324893e208488
https://github.com/llvm/llvm-project/commit/575be3efb056b298bd4cbf9a04c324893e208488
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
Log Message:
-----------
[AMDGPU][llvm-split] Make declarations test more stable
Delete the previous files if present, to ensure it won't fail if the output directory of the tests wasn't cleared.
Commit: fdca2c33a1f33f4886d969ea0f0219764c7b6b59
https://github.com/llvm/llvm-project/commit/fdca2c33a1f33f4886d969ea0f0219764c7b6b59
Author: Akshat Oke <76596238+Akshat-Oke at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
A llvm/lib/Target/AMDGPU/GCNDPPCombine.h
M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
Log Message:
-----------
AMDGPU/NewPM Port GCNDPPCombine to NPM (#105816)
Co-authored-by: Akshat Oke <Akshat.Oke at amd.com>
Commit: 60e9fb9dae0e041cb468210f5795e9d59e70cccf
https://github.com/llvm/llvm-project/commit/60e9fb9dae0e041cb468210f5795e9d59e70cccf
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
Log Message:
-----------
[Flang][OpenMP] Don't expect block arguments using early privatization (#105842)
There are some spots where all symbols to privatize collected by a
`DataSharingProcessor` instance are expected to have corresponding entry
block arguments associated regardless of whether delayed privatization
was enabled.
This can result in compiler crashes if a `DataSharingProcessor` instance
created with `useDelayedPrivatization=false` is queried in this way. The
solution proposed by this patch is to provide another public method to
query specifically delayed privatization symbols, which will either be
empty or point to the complete set of symbols to privatize accordingly.
Commit: c28b84e30b7bb5816c71c72546a8e4167d1e1b5d
https://github.com/llvm/llvm-project/commit/c28b84e30b7bb5816c71c72546a8e4167d1e1b5d
Author: JoelWee <32009741+JoelWee at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Update BUILD.bazel after e37d6d2a74d7
Commit: 2505546aee8b35d03d7755b0f8e6cd960295928e
https://github.com/llvm/llvm-project/commit/2505546aee8b35d03d7755b0f8e6cd960295928e
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/riscv.c
Log Message:
-----------
[compiler-rt][RISCV][NFC] Update code_model with latest spec (#106498)
The spec could be found here
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74
This patch updates the following symbol:
```
mVendorID -> mvendorid
mArchID -> marchid
mImplID -> mimpid
```
Commit: 911b96058a94a10a3897a56af703992c4509965b
https://github.com/llvm/llvm-project/commit/911b96058a94a10a3897a56af703992c4509965b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
PPC: Custom lower ppcf128 is_fpclass if is_fpclass is custom (#105540)
Unfortunately expandIS_FPCLASS is called directly in SelectionDAGBuilder
depending on whether IS_FPCLASS is custom or not. This helps avoid ppc test
regressions in a future patch where the custom lowering would be bypassed.
Commit: 7b7b0b95b2bb8e72fb60438409b12d8eabf484a2
https://github.com/llvm/llvm-project/commit/7b7b0b95b2bb8e72fb60438409b12d8eabf484a2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/PowerPC/is_fpclass.ll
Log Message:
-----------
DAG: Check if is_fpclass is custom, instead of isLegalOrCustom (#105577)
For some reason, isOperationLegalOrCustom is not the same as
isOperationLegal || isOperationCustom. Unfortunately, it checks
if the type is legal which makes it uesless for custom lowering
on non-legal types (which is always ppcf128).
Really the DAG builder shouldn't be going to expand this in the
builder, it makes it difficult to work with. It's only here to work
around the DAG requiring legal integer types the same size as
the FP type after type legalization.
Commit: fcb3a0485857c749d04ea234a8c3d629c62ab211
https://github.com/llvm/llvm-project/commit/fcb3a0485857c749d04ea234a8c3d629c62ab211
Author: Luke Shingles <luke.shingles at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Support/Z3Solver.cpp
Log Message:
-----------
[analyzer] Add missing include <unordered_map> to llvm/lib/Support/Z3Solver.cpp (#106410)
Resolves #106361. Adding #include <unordered_map> to
llvm/lib/Support/Z3Solver.cpp fixes compilation errors for homebrew
build on macOS with Xcode 14.
https://github.com/Homebrew/homebrew-core/actions/runs/10604291631/job/29390993615?pr=181351
shows that this is resolved when the include is patched in (Linux CI
failure is due to unrelated timeout).
Commit: 36b7c30b292f853c09b80f8bc2c5f233f68c9e7b
https://github.com/llvm/llvm-project/commit/36b7c30b292f853c09b80f8bc2c5f233f68c9e7b
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
A llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
M llvm/utils/TableGen/X86DisassemblerTables.cpp
Log Message:
-----------
[X86, MC] Recognize OSIZE=64b when EVEX.W = 1, EVEX.pp = 01 (#103816)
In the legacy space, if both the 66 prefix and REX.W=1 are present, the
REX.W=1 takes precedence and makes OSIZE=64b. EVEX map 4 inherits this
convention, with EVEX.pp=01 and EVEX.W playing the roles of the 66
prefix and REX.W. So if EVEX.pp=00, the OSIZE can only be 64b or 32b,
depending on whether EVEX.W=1 or not. But if EVEX.pp=01, then OSIZE is
either 64b or 16b depending on whether EVEX.W=1 or not.
Commit: ddbc8f331a708dacfbf0a41e8ae6b8f6d9605407
https://github.com/llvm/llvm-project/commit/ddbc8f331a708dacfbf0a41e8ae6b8f6d9605407
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
R llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred-parent.ll
R llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-sindle-bv.ll
R llvm/test/Transforms/SLPVectorizer/X86/arith-div-undef.ll
R llvm/test/Transforms/SLPVectorizer/X86/bool-logical-op-reduction-with-poison.ll
R llvm/test/Transforms/SLPVectorizer/X86/buildvector-insert-mask-size.ll
R llvm/test/Transforms/SLPVectorizer/X86/buildvector-nodes-dependency.ll
R llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/catchswitch.ll
R llvm/test/Transforms/SLPVectorizer/X86/crash_exceed_scheduling.ll
R llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast.ll
A llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
A llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
A llvm/test/Transforms/SLPVectorizer/arith-div-undef.ll
A llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
A llvm/test/Transforms/SLPVectorizer/buildvector-insert-mask-size.ll
A llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
A llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/catchswitch.ll
A llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
A llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
Log Message:
-----------
[SLP] Move some of X86 tests to common directory (#106401)
Some of the tests from X86 directory can be generalized for AArch64 to
improve its coverage.
Commit: 3ef37e2f8f672393ee409fde8309198df0981735
https://github.com/llvm/llvm-project/commit/3ef37e2f8f672393ee409fde8309198df0981735
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/CodeGen/Thumb2/pr52817.ll
M llvm/test/CodeGen/X86/fsafdo_test1.ll
M llvm/test/CodeGen/X86/fsafdo_test4.ll
A llvm/test/DebugInfo/Generic/is_stmt-at-block-start.ll
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
M llvm/test/DebugInfo/X86/discriminator.ll
Log Message:
-----------
[DebugInfo][DWARF] Set is_stmt on first non-line-0 instruction in BB (#105524)
Fixes: https://github.com/llvm/llvm-project/issues/104695
This patch adds the is_stmt flag to line table entries for the first
instruction with a non-0 line location in each basic block, to ensure
that it will be used for stepping even if the last instruction in the
previous basic block had the same line number; this is important for
cases where the new BB is reachable from BBs other than the preceding
block.
Commit: 2784060c167d86a05f20a0ab1892f96e69a2da20
https://github.com/llvm/llvm-project/commit/2784060c167d86a05f20a0ab1892f96e69a2da20
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[MLIR][Flang][OpenMP] Remove omp.parallel from loop wrapper ops (#105833)
This patch updates the `omp.parallel` operation according to the results
of the discussion in [this
RFC](https://discourse.llvm.org/t/rfc-disambiguation-between-loop-and-block-associated-omp-parallelop/79972).
It is removed from the set of loop wrapper operations, changing the
expected MLIR representation for composite `distribute parallel do/for`
into the following:
```mlir
omp.parallel {
...
omp.distribute {
omp.wsloop {
omp.loop_nest ... { ... }
omp.terminator
}
omp.terminator
}
...
omp.terminator
}
```
MLIR verifiers for operations impacted by this representation change are
updated, as well as related tests. The `LoopWrapperInterface` is also
updated, since it's no longer representing an optional "role" of an
operation but a mandatory set of restrictions instead.
Commit: 0f206b19c3303aeb8e527b4977da2bd301464a9b
https://github.com/llvm/llvm-project/commit/0f206b19c3303aeb8e527b4977da2bd301464a9b
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
Log Message:
-----------
[Flang][OpenMP] Move loop privatization out of dispatch (#106066)
This patch moves the creation of `DataSharingProcessor` instances for
loop constructs out of `genOMPDispatch()` and into their corresponding
codegen functions. This is a necessary first step to enable a proper
handling of privatization on composite constructs.
Some tests are updated due to a change of order between clause
processing and privatization.
Commit: 113806d187901ec3ca202ffa22ef94c80770a760
https://github.com/llvm/llvm-project/commit/113806d187901ec3ca202ffa22ef94c80770a760
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes-cvt.ll
Log Message:
-----------
[AArch64] optimise SVE cvt intrinsics with no active lanes (#104809)
This patch extends https://github.com/llvm/llvm-project/pull/73964 and
optimises SVE cvt intrinsics away when predicate is zero.
Commit: 9c8ce5fac8a05e27cca832fb3913ec986b120211
https://github.com/llvm/llvm-project/commit/9c8ce5fac8a05e27cca832fb3913ec986b120211
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/distribute-parallel-do.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-compound.f90
Log Message:
-----------
[Flang][OpenMP] DISTRIBUTE PARALLEL DO lowering (#106207)
This patch adds PFT to MLIR lowering support for `distribute parallel
do` composite constructs.
Commit: 57726c440c30b3f0b5ebfaf345b0237df4430259
https://github.com/llvm/llvm-project/commit/57726c440c30b3f0b5ebfaf345b0237df4430259
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-compound.f90
Log Message:
-----------
[Flang][OpenMP] DISTRIBUTE PARALLEL DO SIMD lowering (#106211)
This patch adds PFT to MLIR lowering support for `distribute parallel do
simd` composite constructs.
Commit: fdf72c992b2781de3f6c78698164e55a031a268e
https://github.com/llvm/llvm-project/commit/fdf72c992b2781de3f6c78698164e55a031a268e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/cmp-in-bv-node-type-cost.ll
Log Message:
-----------
[SLP]Fix a crash when requestin the cost for buildvector cmp nodes types.
Need to use original cmp type i1 when estimating the cost for the
buildvector node, not its operand types to prevent compiler crash upon
TTI cost estimation.
Commit: c3cb27370af40e491446164840766478d3258429
https://github.com/llvm/llvm-project/commit/c3cb27370af40e491446164840766478d3258429
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
Log Message:
-----------
Fix MSVC "not all control paths return a value" warning. NFC.
Commit: 616f7d3d4f6d9bea6f776e357c938847e522a681
https://github.com/llvm/llvm-project/commit/616f7d3d4f6d9bea6f776e357c938847e522a681
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
R llvm/test/DebugInfo/Generic/is_stmt-at-block-start.ll
A llvm/test/DebugInfo/X86/is_stmt-at-block-start.ll
Log Message:
-----------
[DebugInfo][NFC] Make is_stmt-at-block-start test X86-specific
Fixes failure on the llvm-clang-aarch64-darwin buildbot:
https://lab.llvm.org/buildbot/#/builders/190/builds/4660/
The test mentioned does not rely on any unique property of X86, but does
rely on the layout of the basic blocks produced by llc, which varies
between targets. Although the test could be duplicated for other targets,
it seems unnecessary since the behaviour being tested is not
target-specific.
Commit: 0a272d3a1703415abca42dc2e2cc2b57cb30734e
https://github.com/llvm/llvm-project/commit/0a272d3a1703415abca42dc2e2cc2b57cb30734e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
Log Message:
-----------
[LV] Use SCEV to analyze second operand for cost query.
Improve operand analysis using SCEV for cost purposes. This fixes a
divergence between legacy and VPlan-based cost-modeling after
533e6bbd0d34.
Fixes https://github.com/llvm/llvm-project/issues/106248.
Commit: 926f0979af4f6172d4ed3dea5603aa97c800bef1
https://github.com/llvm/llvm-project/commit/926f0979af4f6172d4ed3dea5603aa97c800bef1
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/CodeGen/Thumb2/pr52817.ll
M llvm/test/CodeGen/X86/fsafdo_test1.ll
M llvm/test/CodeGen/X86/fsafdo_test4.ll
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
M llvm/test/DebugInfo/X86/discriminator.ll
R llvm/test/DebugInfo/X86/is_stmt-at-block-start.ll
Log Message:
-----------
Revert "[DebugInfo][DWARF] Set is_stmt on first non-line-0 instruction in BB (#105524)"
Reverted (along with the NFC followup fix) due to buildbot failure:
https://lab.llvm.org/buildbot/#/builders/160/builds/4142
This reverts commit 3ef37e2f8f672393ee409fde8309198df0981735, and commit
616f7d3d4f6d9bea6f776e357c938847e522a681.
Commit: 606a9342f1083eef1475c2a97eabb04db9338bdd
https://github.com/llvm/llvm-project/commit/606a9342f1083eef1475c2a97eabb04db9338bdd
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
A llvm/test/Analysis/LoopAccessAnalysis/evaluate-at-symbolic-max-backedge-taken-count-may-wrap.ll
Log Message:
-----------
[LAA] Add test cases where evaluating AddRecs at symbolic max BTC wraps.
The underlying issue was discovered by an assert added in
a80053322b765eec939 by a test case provided by @mstorsjo.
Commit: 50515db57f1a8b3d7fd61c1df946a29971f65428
https://github.com/llvm/llvm-project/commit/50515db57f1a8b3d7fd61c1df946a29971f65428
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Format canVectorizeLoads after previous NFC patches.
Commit: 9167667b5c3cd1b166452c984f0c6448688c22a0
https://github.com/llvm/llvm-project/commit/9167667b5c3cd1b166452c984f0c6448688c22a0
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
M llvm/test/Transforms/SLPVectorizer/arith-div-undef.ll
M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-insert-mask-size.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
M llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/catchswitch.ll
M llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
Log Message:
-----------
[SLP] Fix REQUIRES line for failing tests (#106531)
Commit: cb608cc5f62baa01fe106a14ef41971337c2c030
https://github.com/llvm/llvm-project/commit/cb608cc5f62baa01fe106a14ef41971337c2c030
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
A clang/test/AST/ByteCode/cxx11-pedantic.cpp
Log Message:
-----------
[clang][bytecode] Properly diagnose non-const reads (#106514)
If the global variable is constant (but not constexpr), we need to
diagnose, but keep evaluating.
Commit: 25c9410fed7da0bc83bb0390f6e8d83470536fa0
https://github.com/llvm/llvm-project/commit/25c9410fed7da0bc83bb0390f6e8d83470536fa0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
Log Message:
-----------
[InstCombine][X86] Add vpermilpd/vpermilps test coverage for #106413
Commit: d57c04647e6f0a6f0cd79e280c257f570e8f30f4
https://github.com/llvm/llvm-project/commit/d57c04647e6f0a6f0cd79e280c257f570e8f30f4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
Log Message:
-----------
[InstCombine][X86] Only demand used bits for VPERMILPD/VPERMILPS mask values
VPERMILPS lower bits0-3 (to index per-lane i32/f32 0-3)
VPERMILPD uses bit1 (to index per-lane i64/f64 0-1)
Use SimplifyDemandedBits to ignore anything touching the remaining bits.
Part of #106413
Commit: 2a28df66dc3f7ff5b6233241837854acefb68d77
https://github.com/llvm/llvm-project/commit/2a28df66dc3f7ff5b6233241837854acefb68d77
Author: Hans <hans at hanshq.net>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/utils/release/build_llvm_release.bat
Log Message:
-----------
Restrict LLVM_TARGETS_TO_BUILD in Windows release packaging (#106059)
When including all targets, some files become too large for the NSIS
installer to handle.
Fixes #101994
Commit: b2a820faea960e99123f309d6a7bccb3cd1bcc12
https://github.com/llvm/llvm-project/commit/b2a820faea960e99123f309d6a7bccb3cd1bcc12
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/launch/main.c
Log Message:
-----------
[lldb][lldb-dap][test] Enable Launch tests
Add Windows include equivalents for includes and shell command.
Commit: 0a484820e1d34b051831624cbe237bba578ac2d8
https://github.com/llvm/llvm-project/commit/0a484820e1d34b051831624cbe237bba578ac2d8
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/docs/CodeOfConduct.rst
Log Message:
-----------
Restore missing link in CodeOfConduct.rst (#106385)
Link restored from the original policy outlined here
https://discourse.llvm.org/t/code-of-conduct-changes-related-to-llvm-project-policy-changes/64197
Commit: 73ef397fcba35b7b4239c00bf3e0b4e689ca0add
https://github.com/llvm/llvm-project/commit/73ef397fcba35b7b4239c00bf3e0b4e689ca0add
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libc/src/string/memory_utils/x86_64/inline_memcpy.h
Log Message:
-----------
[libc][x86] Use prefetch for write for memcpy (#90450)
Currently when `LIBC_COPT_MEMCPY_X86_USE_SOFTWARE_PREFETCHING` is set we
prefetch memory for read on the source buffer. This patch adds prefetch
for write on the destination buffer.
Commit: acff429191a27a164a0941346ce0c73e953d4638
https://github.com/llvm/llvm-project/commit/acff429191a27a164a0941346ce0c73e953d4638
Author: kadir çetinkaya <kadircet at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang-tools-extra/include-cleaner/lib/WalkAST.cpp
M clang-tools-extra/include-cleaner/unittests/WalkASTTest.cpp
Log Message:
-----------
[include-cleaner] Mark RecordDecls referenced in UsingDecls as explicit (#106430)
We were reporting ambigious references from using declarations as user
can be depending on different overloads of a function just because they
are visible in the TU.
This doesn't apply to records, or primary templates as declaration being
referenced in such cases is unambigious, the ambiguity applies to
specializations though.
Hence this patch returns an explicit reference to record decls and
primary templates of those.
Commit: 7955760bc82c792b84a4d97913f5b8e0f4902108
https://github.com/llvm/llvm-project/commit/7955760bc82c792b84a4d97913f5b8e0f4902108
Author: Koakuma <koachan at protonmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/Sparc/SparcInstrAliases.td
M llvm/test/MC/Sparc/sparc-misc-instructions.s
Log Message:
-----------
[SPARC][IAS] Add `illtrap` alias for `unimp` (#105928)
This follows Solaris behavior of allowing both mnemonics all the time.
Fixes https://github.com/llvm/llvm-project/issues/105639.
Commit: ba52a09abe3f3a2323dd7df3fe1739630e054077
https://github.com/llvm/llvm-project/commit/ba52a09abe3f3a2323dd7df3fe1739630e054077
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/SCCP/pointer-nonnull.ll
Log Message:
-----------
[IPSCCP] Add test for returning nonnull pointer (NFC)
Commit: 43661a1214353ea1773a711f403f8d1118e9ca0f
https://github.com/llvm/llvm-project/commit/43661a1214353ea1773a711f403f8d1118e9ca0f
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
Log Message:
-----------
[RemoveDIs] Fix spliceDebugInfo splice-to-end edge case (#105671)
Fix #105571 which demonstrates an end() iterator dereference when
performing a non-empty splice to end() from a region that ends at
Src::end().
Rather than calling Instruction::adoptDbgRecords from Dest, create a marker
(which takes an iterator) and absorbDebugValues onto that. The "absorb" variant
doesn't clean up the source marker, which in this case we know is a trailing
marker, so we have to do that manually.
Commit: 1f8f2ed66ab742a1fbb4a84411e656cb8324e107
https://github.com/llvm/llvm-project/commit/1f8f2ed66ab742a1fbb4a84411e656cb8324e107
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
Log Message:
-----------
[NFC][AMDGPU] Autogenerate tests for uniform i32 promo in ISel (#106382)
Many tests were easy to update, but these are quite big and I think it's
better to autogenerate them to see the difference well.
Commit: df11ee213e43ae373d1357939cf14ea37d547110
https://github.com/llvm/llvm-project/commit/df11ee213e43ae373d1357939cf14ea37d547110
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBlock.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Diagnose member calls on deleted blocks (#106529)
This requires a bit of restructuring of ctor calls when checking for a
potential constant expression.
Commit: c57abc66e223393cda27760e3f2409f4a1aa895e
https://github.com/llvm/llvm-project/commit/c57abc66e223393cda27760e3f2409f4a1aa895e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
Log Message:
-----------
[LoopVectorize][X86] amdlibm-calls.ll - cleanup test checks for 2/4/8/16 vector widths
This cleans up the existing tests and shows the gaps in the test checks (for instance we're often testing VF4 + VF16 but not VF8 even though amdlibm supports it).
Commit: 2f95298727bc9b682ad2d058119862ee8b0d8ec2
https://github.com/llvm/llvm-project/commit/2f95298727bc9b682ad2d058119862ee8b0d8ec2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
Log Message:
-----------
[LoopVectorize][X86] amdlibm-calls.ll - add additional 2/4/8/16 vector widths test checks
This should cover most amdlibm functions, but still not added every VF combo (e.g. 2f32/16f64 often vectorises to the llvm intrinsic for that vector type)
Commit: f7d6dfa005ac3d136e38658f25b8c54daa1ef08c
https://github.com/llvm/llvm-project/commit/f7d6dfa005ac3d136e38658f25b8c54daa1ef08c
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/console/TestDAP_redirection_to_console.py
M lldb/test/API/tools/lldb-dap/coreFile/TestDAP_coreFile.py
Log Message:
-----------
[lldb][lldb-dap] Enable more tests on Windows
These few worked without changes.
Commit: 56152fa377302fd8124e8be2a02dcb927a041f0a
https://github.com/llvm/llvm-project/commit/56152fa377302fd8124e8be2a02dcb927a041f0a
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Analysis/CMakeLists.txt
Log Message:
-----------
[Analysis] Guard logf128 cst folding (#106543)
LLVM has a CMake variable to control whether to consider logf128
constant folding which libAnalysis ignores. This patch changes the
logf128 check to rely on the global LLVM_HAS_LOGF128 setting made in
config-ix.cmake.
Commit: 5fef40c2c477e92187bd4e5c18091eca6b8465cc
https://github.com/llvm/llvm-project/commit/5fef40c2c477e92187bd4e5c18091eca6b8465cc
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/CodeGen/Thumb2/pr52817.ll
M llvm/test/CodeGen/X86/fsafdo_test1.ll
M llvm/test/CodeGen/X86/fsafdo_test4.ll
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
M llvm/test/DebugInfo/X86/discriminator.ll
A llvm/test/DebugInfo/X86/is_stmt-at-block-start.ll
Log Message:
-----------
Reapply "[DebugInfo][DWARF] Set is_stmt on first non-line-0 instruction in BB (#105524)"
Fixes the previous buildbot error by adding an explicit triple to the test,
ensuring that llc can produce a valid object file.
This reverts commit 926f0979af4f6172d4ed3dea5603aa97c800bef1.
Commit: 8ae877a089d9c2ca5315d3b2e0144c4d9f82cf5c
https://github.com/llvm/llvm-project/commit/8ae877a089d9c2ca5315d3b2e0144c4d9f82cf5c
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/include/flang/Tools/TargetSetup.h
M flang/module/ieee_arithmetic.f90
M flang/test/CMakeLists.txt
M flang/test/Evaluate/fold-out_of_range.f90
M flang/test/Evaluate/folding07.f90
M flang/test/Lower/Intrinsics/ieee_class_queries.f90
M flang/test/Lower/Intrinsics/ieee_unordered.f90
M flang/test/Lower/common-block.f90
M flang/test/Semantics/kinds03.f90
M flang/test/Semantics/modfile26.f90
M flang/test/Semantics/realkinds-aarch64-01.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/f18/CMakeLists.txt
Log Message:
-----------
Revert "[flang] Warn when F128 is unsupported" (#106561)
Reverts llvm/llvm-project#102147
It seems some systems which should support F128 are wrongly detected as
not supporting.
This might be due to checking `LDBL_MANT_DIG` instead of
`__LDBL_MANT_DIG__`. I will investigate.
Commit: 9edd998e10fabfff067b9e6e5b044f85a24d0dd5
https://github.com/llvm/llvm-project/commit/9edd998e10fabfff067b9e6e5b044f85a24d0dd5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
A llvm/test/Transforms/LoopUnroll/X86/runtime-unroll-addrec-cost.ll
Log Message:
-----------
[LoopUnroll] Add test for #53205 (NFC)
Commit: fc110202dffa06950716e0cc4535b07aaa2c439c
https://github.com/llvm/llvm-project/commit/fc110202dffa06950716e0cc4535b07aaa2c439c
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/FormatVariadicBM.cpp
M llvm/include/llvm/Support/FormatVariadic.h
M llvm/lib/Support/FormatVariadic.cpp
M llvm/unittests/Support/FormatVariadicTest.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[Support] Validate number of arguments passed to formatv() (#105745)
Change formatv() to validate that the number of arguments passed matches
number of replacement fields in the format string, and that the replacement
indices do not contain holes.
To support cases where this cannot be guaranteed, introduce a formatv()
overload that allows disabling validation with a bool flag as its first argument.
Commit: 025f03f01e8584140b7ac27422cea0c0ef7ef6c1
https://github.com/llvm/llvm-project/commit/025f03f01e8584140b7ac27422cea0c0ef7ef6c1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++][NFC] Remove unused struct in <string> (#106527)
Commit: a705e8cb5b071b3bf6d1d55629f18f6b7b9699ac
https://github.com/llvm/llvm-project/commit/a705e8cb5b071b3bf6d1d55629f18f6b7b9699ac
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libcxx/include/cmath
M libcxx/include/complex
M libcxx/test/libcxx/numerics/c.math/constexpr-fns.pass.cpp
Log Message:
-----------
[libc++][NFC] Remove __constexpr_is{nan,finite} (#106205)
They're never used in `constexpr` functions, so we can simply use
`std::isnan` and `std::isfinite` instead.
Commit: 032c3283ab419377a1230a32d98693b528f63134
https://github.com/llvm/llvm-project/commit/032c3283ab419377a1230a32d98693b528f63134
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/TableGen/intrinsic-attrs.td
M llvm/utils/TableGen/IntrinsicEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Refactor IntrinsicEmitter code (#106479)
- Use formatv() and raw string literals to simplify emission code.
- Use range based for loops and structured bindings to simplify loops.
- Use const Pointers to Records.
- Rename `ComputeFixedEncoding` to `ComputeTypeSignature` to reflect
what the function actually does, cnd change it to return a vector.
- Use reverse() and range based for loop to pack 8 nibbles into 32-bits.
- Rename some variables to follow LLVM coding standards.
- For function memory effects, print human readable effects in comment.
Commit: 4ee2ad259812159c4f51bf2d8edcf0376302b2c3
https://github.com/llvm/llvm-project/commit/4ee2ad259812159c4f51bf2d8edcf0376302b2c3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
R llvm/test/CodeGen/AArch64/atomicrmw-fadd-fp-vector.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
AArch64: Add tests for atomicrmw fp operations (#103701)
There were only codegen tests for the fadd vector case,
so round out the test coverage for the scalar cases
and all the other operations.
Commit: 5048fabb0579f1417f69cde49221b5b9e9c15414
https://github.com/llvm/llvm-project/commit/5048fabb0579f1417f69cde49221b5b9e9c15414
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/unittests/Support/FormatVariadicTest.cpp
Log Message:
-----------
[Support] Delete FormatVariadicTest Validate sub-test (#106570)
- The subtest, if enabled correctly, will fail with assert in Debug
builds and validation is disabled in Release builds.
- Hence deleting the test to fix test failures in CI.
Commit: 26c3a8404f1b3327a0982faeeaee94b08d1ee481
https://github.com/llvm/llvm-project/commit/26c3a8404f1b3327a0982faeeaee94b08d1ee481
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
AArch64: Use consistent atomicrmw expansion for FP operations (#103702)
Use LLSC or cmpxchg in the same cases as for the unsupported
integer operations. This required some fixups to the LLSC
implementatation to deal with the fp128 case.
The comment about floating-point exceptions was wrong,
because floating-point exceptions are not really exceptions at all.
Commit: b5a1b45fe321cdf57d1b6155ecbbc18b6f95502f
https://github.com/llvm/llvm-project/commit/b5a1b45fe321cdf57d1b6155ecbbc18b6f95502f
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Early return in getReorderingData [nfc]
Commit: a9ffb719bc323588b6b60fbf227db8104a81310e
https://github.com/llvm/llvm-project/commit/a9ffb719bc323588b6b60fbf227db8104a81310e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
Log Message:
-----------
[RISCV] Don't promote f16 FNEG/FABS with Zfhmin/Zhinxmin. (#106474)
fneg/fabs are not supposed to canonicalize nans. Promoting to f32 will
go through an fp_extend which will canonicalize. The generic Promote
handler needs to be removed from LegalizeDAG.
We need to use integer bit manip to clear the bit instead.
Unfortunately, this is going through the stack due to i16 not being a
legal type. Fixing that will require custom legalization or some other
generic SelectionDAG change.
Commit: e05c22484efb5c767115525adfa4273e48b1ae26
https://github.com/llvm/llvm-project/commit/e05c22484efb5c767115525adfa4273e48b1ae26
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
Log Message:
-----------
AArch64: Delete tests of fp128 atomicrmw fmin/fmax
These are getting different output on some build hosts for some reason.
The stack offsets of temporaries are different.
Commit: c08c6a71cfc536e22fb7ad733fb8181a9e84e62a
https://github.com/llvm/llvm-project/commit/c08c6a71cfc536e22fb7ad733fb8181a9e84e62a
Author: Hongtao Yu <hoy at meta.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/test/Dialect/SCF/loop-unroll.mlir
Log Message:
-----------
[mlir][scf] Allow unrolling loops with integer-typed IV. (#106164)
SCF loops now can operate on integer-typed IV, thus I'm changing the
loop unroller correspondingly.
Commit: 115b87636b9f84cf145c0c96859f8e9f5e76c7a1
https://github.com/llvm/llvm-project/commit/115b87636b9f84cf145c0c96859f8e9f5e76c7a1
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Support/ModRef.cpp
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/ModRefTest.cpp
Log Message:
-----------
[NFC][Support] Eliminate ',' at end of MemoryEffects print (#106545)
- Eliminate comma at end of a MemoryEffects print.
- Added basic unit test to validate that.
Commit: 81acc84997d6d5d5c7f8e3b3e6d8d01d567d0e1c
https://github.com/llvm/llvm-project/commit/81acc84997d6d5d5c7f8e3b3e6d8d01d567d0e1c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
Log Message:
-----------
[LoopVectorize][X86] amdlibm-calls.ll - add 2/4/8/16 vector widths test checks for fallback to llvm intrinsics
Check for cases where there isn't a amdlib call but it still vectorises the math call
Commit: a777a93118a0ca71e19ac764a57a94f1be227dbb
https://github.com/llvm/llvm-project/commit/a777a93118a0ca71e19ac764a57a94f1be227dbb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/utils/TableGen/IntrinsicEmitter.cpp
Log Message:
-----------
Fix MSVC "not all control paths return a value" warning. NFC.
Commit: bd6531b9508624df83f84d9bc687a7339df452e9
https://github.com/llvm/llvm-project/commit/bd6531b9508624df83f84d9bc687a7339df452e9
Author: Kazu Hirata <kazu at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/FunctionImport.h
M llvm/unittests/Transforms/IPO/CMakeLists.txt
A llvm/unittests/Transforms/IPO/ImportIDTableTests.cpp
Log Message:
-----------
[LTO] Introduce a new class ImportIDTable (#106503)
The new class implements a deduplication table to convert import list
elements:
{SourceModule, GUID, Definition/Declaration}
into 32-bit integers, and vice versa. This patch adds a unit test but
does not add a use yet.
To be precise, the deduplication table holds {SourceModule, GUID}
pairs. We use the bottom one bit of the 32-bit integers to indicate
whether we have a definition or declaration.
A subsequent patch will collapse the import list hierarchy --
FunctionsToImportTy holding many instances of FunctionsToImportTy --
down to DenseSet<uint32_t> with each element indexing into the
deduplication table above. This will address multiple sources of
space inefficiency.
Commit: 59f05b683def5ef728baf8c4ae8f846e957ad67f
https://github.com/llvm/llvm-project/commit/59f05b683def5ef728baf8c4ae8f846e957ad67f
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
Log Message:
-----------
[RISCV][TTI] Model cost for insert/extract into illegal types (#106440)
We'd previously just deferred to the base implementation, but that more
or less always returns 1. This underestimates the cost of the
insert/extract, biases the SLP vectorizer towards forming illegally
typed vectors, and underestimates the cost of scalarized operations
(like unaligned scatter/gather).
Commit: e5e38ddf1b8043324175868831da21e941c00aff
https://github.com/llvm/llvm-project/commit/e5e38ddf1b8043324175868831da21e941c00aff
Author: Ahmed Bougacha <ahmed at bougacha.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/test/CodeGen/aarch64-targetattr.c
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Make apple-m4 armv8.7-a again (from armv9.2-a). (#106312)
This is a partial revert of c66e1d6f3429. Even though that
allowed us to declare v9.2-a support without picking up SVE2
in both the backend and the driver, the frontend itself still
enabled SVE via the arch version's default extensions.
Avoid that by reverting back to v8.7-a while we look into
longer-term solutions.
Commit: 3d08ade7bd32f0296e0ca3a13640cc95fa89229a
https://github.com/llvm/llvm-project/commit/3d08ade7bd32f0296e0ca3a13640cc95fa89229a
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/Target.td
M llvm/lib/CodeGen/Analysis.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
A llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/CloneFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
M llvm/test/Analysis/ScalarEvolution/flags-from-poison-dbg.ll
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/LoongArch/O0-pipeline.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
A llvm/test/CodeGen/MIR/X86/fake-use-tailcall.mir
M llvm/test/CodeGen/PowerPC/O0-pipeline.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/X86/O0-pipeline.ll
A llvm/test/CodeGen/X86/fake-use-hpfloat.ll
A llvm/test/CodeGen/X86/fake-use-ld.ll
A llvm/test/CodeGen/X86/fake-use-scheduler.mir
A llvm/test/CodeGen/X86/fake-use-simple-tail-call.ll
A llvm/test/CodeGen/X86/fake-use-suppress-load.ll
A llvm/test/CodeGen/X86/fake-use-tailcall.ll
A llvm/test/CodeGen/X86/fake-use-vector.ll
A llvm/test/CodeGen/X86/fake-use-vector2.ll
A llvm/test/CodeGen/X86/fake-use-zero-length.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
A llvm/test/DebugInfo/AArch64/fake-use-global-isel.ll
A llvm/test/DebugInfo/Inputs/check-fake-use.py
A llvm/test/DebugInfo/X86/fake-use.ll
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
A llvm/test/Transforms/CodeGenPrepare/X86/fake-use-phi.ll
A llvm/test/Transforms/CodeGenPrepare/X86/fake-use-split-ret.ll
A llvm/test/Transforms/GVN/fake-use-constprop.ll
A llvm/test/Transforms/SROA/fake-use-escape.ll
A llvm/test/Transforms/SROA/fake-use-sroa.ll
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Log Message:
-----------
[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)
This patch is part of a set of patches that add an `-fextend-lifetimes`
flag to clang, which extends the lifetimes of local variables and
parameters for improved debuggability. In addition to that flag, the
patch series adds a pragma to selectively disable `-fextend-lifetimes`,
and an `-fextend-this-ptr` flag which functions as `-fextend-lifetimes`
for this pointers only. All changes and tests in these patches were
written by Wolfgang Pieb (@wolfy1961), while Stephen Tozer (@SLTozer)
has handled review and merging. The extend lifetimes flag is intended to
eventually be set on by `-Og`, as discussed in the RFC
here:
https://discourse.llvm.org/t/rfc-redefine-og-o1-and-add-a-new-level-of-og/72850
This patch implements a new intrinsic instruction in LLVM,
`llvm.fake.use` in IR and `FAKE_USE` in MIR, that takes a single operand
and has no effect other than "using" its operand, to ensure that its
operand remains live until after the fake use. This patch does not emit
fake uses anywhere; the next patch in this sequence causes them to be
emitted from the clang frontend, such that for each variable (or this) a
fake.use operand is inserted at the end of that variable's scope, using
that variable's value. This patch covers everything post-frontend, which
is largely just the basic plumbing for a new intrinsic/instruction,
along with a few steps to preserve the fake uses through optimizations
(such as moving them ahead of a tail call or translating them through
SROA).
Co-authored-by: Stephen Tozer <stephen.tozer at sony.com>
Commit: 74b4ec17e24a256b4aae5e53b855ba429af685bf
https://github.com/llvm/llvm-project/commit/74b4ec17e24a256b4aae5e53b855ba429af685bf
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/IR/VPIntrinsics.def
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/IR/IntrinsicInst.cpp
Log Message:
-----------
[VP] Remove VP_PROPERTY_REDUCTION and VP_PROPERTY_CMP [nfc] (#105551)
These lists are quite static and several of the parameters are actually
constant across all users. Heavy use of macros is undesirable, and not
idiomatic in LLVM, so let's just use the naive switch cases.
I'll probably continue with removing the other property macros. These
two just happened to be the two I actually had to figure out for an
unrelated change.
Commit: eed135fea72b544426349e6461a0ca142c27967e
https://github.com/llvm/llvm-project/commit/eed135fea72b544426349e6461a0ca142c27967e
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Analysis/CMakeLists.txt
Log Message:
-----------
Revert "[Analysis] Guard logf128 cst folding"
This reverts commit 42d3cccffd203ff6dc967d4243588ca466c0faf7 which
caused a test failure.
Commit: 178392454e076624674b4a7ddf3fc8bda2e94f0e
https://github.com/llvm/llvm-project/commit/178392454e076624674b4a7ddf3fc8bda2e94f0e
Author: Harini0924 <harinidonthula at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/utils/lit/lit/TestRunner.py
A llvm/utils/lit/tests/Inputs/shtest-env-negative/env-calls-cd.txt
A llvm/utils/lit/tests/Inputs/shtest-env-negative/env-calls-colon.txt
A llvm/utils/lit/tests/Inputs/shtest-env-negative/env-calls-echo.txt
A llvm/utils/lit/tests/Inputs/shtest-env-negative/env-calls-export.txt
A llvm/utils/lit/tests/Inputs/shtest-env-negative/env-calls-mkdir.txt
A llvm/utils/lit/tests/Inputs/shtest-env-negative/env-calls-not-builtin.txt
A llvm/utils/lit/tests/Inputs/shtest-env-negative/env-calls-rm.txt
A llvm/utils/lit/tests/Inputs/shtest-env-negative/lit.cfg
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env-args-last-is-assign.txt
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env-args-last-is-u-arg.txt
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env-args-last-is-u.txt
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env-args-nested-none.txt
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env-calls-env.txt
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env-no-subcommand.txt
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env-u.txt
A llvm/utils/lit/tests/Inputs/shtest-env-positive/env.txt
A llvm/utils/lit/tests/Inputs/shtest-env-positive/lit.cfg
A llvm/utils/lit/tests/Inputs/shtest-env-positive/mixed.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-args-last-is-assign.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-args-last-is-u-arg.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-args-last-is-u.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-args-nested-none.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-args-none.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-calls-cd.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-calls-colon.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-calls-echo.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-calls-env.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-calls-export.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-calls-mkdir.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-calls-not-builtin.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-calls-rm.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env-u.txt
R llvm/utils/lit/tests/Inputs/shtest-env/env.txt
R llvm/utils/lit/tests/Inputs/shtest-env/lit.cfg
R llvm/utils/lit/tests/Inputs/shtest-env/mixed.txt
R llvm/utils/lit/tests/Inputs/shtest-env/print_environment.py
A llvm/utils/lit/tests/shtest-env-negative.py
A llvm/utils/lit/tests/shtest-env-positive.py
R llvm/utils/lit/tests/shtest-env.py
Log Message:
-----------
[llvm-lit] Print environment variables when using env without subcommand (#98414)
This patch addresses an issue with lit's internal shell when env is
without any arguments, it fails with exit code 127 because `env`
requires a subcommand. This patch addresses the issue by encoding the
command to properly return environment variables even when no arguments
are provided.
The error occurred when running the command
` LIT_USE_INTERNAL_SHELL=1 ninja check-llvm`.
fixes: #102383
This is part of the test cleanups proposed in the RFC: [[RFC] Enabling
the Lit Internal Shell by
Default](https://discourse.llvm.org/t/rfc-enabling-the-lit-internal-shell-by-default/80179)
Commit: 2dc3b509879518340b991733bfde5c7a4becd559
https://github.com/llvm/llvm-project/commit/2dc3b509879518340b991733bfde5c7a4becd559
Author: Greg Roth <grroth at microsoft.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
A clang/test/CodeGenHLSL/implicit-norecurse-attrib.hlsl
M clang/test/CodeGenHLSL/this-assignment-overload.hlsl
M clang/test/CodeGenHLSL/this-assignment.hlsl
Log Message:
-----------
[HLSL] Apply NoRecurse attrib to all HLSL functions (#105907)
Previously, functions named "main" got the NoRecurse attribute
consistent with the behavior of C++, which HLSL largely follows.
However, standard recursion is not allowed in HLSL, so all functions
should really have this attribute. This doesn't prevent recursion, but
rather signals that these functions aren't expected to recurse.
Practically, this was done so that entry point functions named "main"
would have all have the same attributes as otherwise identical entry
points with other names.
This required small changes to the this assignment tests because they no
longer generate so many attribute sets since more of them match.
related to #105244
but done to simplify testing for #89806
Commit: ecd65e64e885b0fd2786ca99ea0c42d692275d91
https://github.com/llvm/llvm-project/commit/ecd65e64e885b0fd2786ca99ea0c42d692275d91
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/tools/dxil-dis/BasicIR.ll
M llvm/test/tools/dxil-dis/debug-info.ll
M llvm/test/tools/dxil-dis/opaque-gep.ll
M llvm/test/tools/dxil-dis/opaque-pointers.ll
Log Message:
-----------
[DXIL][test] Fix a few tests now that HLSL functions are internalized (#106437)
These tests have been failing since db279c72f2fe "[HLSL] Change default
linkage of HLSL functions to internal (#95331)". This presumably went
unnoticed because they're not run by default since they rely on an
external tool (dxil-dis).
Commit: 2ad782f49ff20d199f31cabc9baa46dba6047d8b
https://github.com/llvm/llvm-project/commit/2ad782f49ff20d199f31cabc9baa46dba6047d8b
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/IR/VPIntrinsics.def
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/unittests/IR/VPIntrinsicTest.cpp
Log Message:
-----------
[VP] Kill VP_PROPERTY_(MEMOP,CASTOP) and simplify _CONSTRAINEDFP [nfc] (#105574)
These lists are quite static. Heavy use of macros is undesirable, and
not idiomatic in LLVM, so let's just use the naive switch cases.
Note that the first two fields in the CONSTRAINEDFP property were
utterly unused (aside from a C++ test).
In the same vien as https://github.com/llvm/llvm-project/pull/105551.
Once both changes have landed, we'll be left with _BINARYOP which needs
a bit of additional untangling, and the actual opcode mappings.
Commit: 0a00d32c5f88fce89006dcde6e235bc77d7b495e
https://github.com/llvm/llvm-project/commit/0a00d32c5f88fce89006dcde6e235bc77d7b495e
Author: Jordan R AW <ajordanr at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/include/lldb/Utility/ArchSpec.h
M lldb/source/Utility/ArchSpec.cpp
Log Message:
-----------
[lldb] Add armv7a and armv8a ArchSpecs (#106433)
armv7a and armv8a are common names for the application subarch for arm.
These names in particular are used in ChromeOS, Android, and a few other
known applications. In ChromeOS, we encountered a bug where armv7a arch
was not recognised and segfaulted when starting an executable on an
arm32 device.
Google Issue Tracker:
https://issuetracker.google.com/361414339
Commit: ed37b5f6c341a2c72d1f5f0c016f0f8a41a9bf83
https://github.com/llvm/llvm-project/commit/ed37b5f6c341a2c72d1f5f0c016f0f8a41a9bf83
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M llvm/benchmarks/CMakeLists.txt
R llvm/benchmarks/FormatVariadicBM.cpp
M llvm/include/llvm/Support/FormatVariadic.h
M llvm/lib/Support/FormatVariadic.cpp
M llvm/unittests/Support/FormatVariadicTest.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
Revert "[Support] Validate number of arguments passed to formatv()" (#106589)
Reverts llvm/llvm-project#105745
Some bots are broken apparently.
Commit: 67ffd1438379ee43f678f3e7752f4ec5f777cee4
https://github.com/llvm/llvm-project/commit/67ffd1438379ee43f678f3e7752f4ec5f777cee4
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libcxx/test/libcxx/type_traits/is_specialization.verify.cpp
Log Message:
-----------
libcxx: [NFC] relax error expectation for clang diagnostics (#106591)
This is a split-off from #96023, where this change has already been
reviewed by libcxx maintainers.
This will prevent that PR from triggering libcxx-ci from now on.
Commit: 9ce4af5cadc24060f3c3674e01902d374afea983
https://github.com/llvm/llvm-project/commit/9ce4af5cadc24060f3c3674e01902d374afea983
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/FormatVariadicBM.cpp
M llvm/include/llvm/Support/FormatVariadic.h
M llvm/lib/Support/FormatVariadic.cpp
M llvm/unittests/Support/FormatVariadicTest.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
Revert "Revert "[Support] Validate number of arguments passed to formatv()"" (#106592)
Reverts llvm/llvm-project#106589
The fix for bot failures caused by the reverted commit was committed
already, so this revert is not needed.
Commit: 9a58b12fe7bf54c9433ec89bae2a2d6cfe489e75
https://github.com/llvm/llvm-project/commit/9a58b12fe7bf54c9433ec89bae2a2d6cfe489e75
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/CodeGen/MIR/X86/fake-use-tailcall.mir
M llvm/test/CodeGen/X86/fake-use-scheduler.mir
M llvm/test/CodeGen/X86/fake-use-tailcall.ll
M llvm/test/CodeGen/X86/fake-use-vector2.ll
M llvm/test/CodeGen/X86/fake-use-zero-length.ll
Log Message:
-----------
[ExtendLifetimes][NFC] Add explicit triple to new fake-use tests
Several tests for the new fake use intrinsic are failing on NVPTX
buildbots due to relying on behaviour for their expected triple;
this commit adds that triple to each of them to prevent failures.
Fixes commit 3d08ade (#86149).
Example buildbot failures:
https://lab.llvm.org/buildbot/#/builders/160/builds/4175
https://lab.llvm.org/buildbot/#/builders/180/builds/4173
Commit: 4bc7c74240b6f13bf421c1fef0155370b23d9fc8
https://github.com/llvm/llvm-project/commit/4bc7c74240b6f13bf421c1fef0155370b23d9fc8
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Extract isIdentityOrder to common routine [probably NFC] (#106582)
This isn't quite just code motion as the four different versions we had
of this routine differed in whether they ignored the "size" marker used
to represent undef. I doubt this matters in practice, but it is a
functional change.
---------
Co-authored-by: Alexey Bataev <a.bataev at gmx.com>
Commit: fd0dbc7f4d8a5900535aa87569fbc385b7c50ba6
https://github.com/llvm/llvm-project/commit/fd0dbc7f4d8a5900535aa87569fbc385b7c50ba6
Author: Xiang Li <python3kgae at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/ObjectYAML/DXContainerYAML.h
M llvm/lib/BinaryFormat/DXContainer.cpp
M llvm/lib/ObjectYAML/DXContainerYAML.cpp
M llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv0-amplification.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv0-compute.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv0-domain.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv0-geometry.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv0-hull.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv0-mesh.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv0-pixel.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv0-vertex.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-amplification.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-compute.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-domain.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-geometry.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-hull.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-mesh.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-pixel.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-vertex.yaml
M llvm/test/ObjectYAML/DXContainer/SigElements.yaml
M llvm/unittests/Object/DXContainerTest.cpp
Log Message:
-----------
[DirectX] add enum for PSV resource type/kind/flag. (#106227)
Add ResourceType, ResourceKind and ResourceFlag enum class for PSV
resource.
This is for #103275
Commit: 1ace91f925ad87c3e5eb836ad58fdffe60c4aea6
https://github.com/llvm/llvm-project/commit/1ace91f925ad87c3e5eb836ad58fdffe60c4aea6
Author: Job Henandez Lara <hj93 at protonmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h
M libc/test/src/math/performance_testing/CMakeLists.txt
M libc/test/src/math/performance_testing/fmod_perf.cpp
M libc/test/src/math/performance_testing/fmodf16_perf.cpp
M libc/test/src/math/performance_testing/fmodf_perf.cpp
A libc/test/src/math/performance_testing/fmul_perf.cpp
A libc/test/src/math/performance_testing/fmull_perf.cpp
M libc/test/src/math/performance_testing/hypot_perf.cpp
M libc/test/src/math/performance_testing/hypotf_perf.cpp
M libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
M libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
Log Message:
-----------
[libc][math] Add performance tests for fmul and fmull. (#106262)
Commit: 0a41c8e7a050c837c609cbcbc8342024701cd14b
https://github.com/llvm/llvm-project/commit/0a41c8e7a050c837c609cbcbc8342024701cd14b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
Log Message:
-----------
[flang][cuda] Avoid generating cuf.data_transfer in OpenACC region (#106435)
`cuf.data_transfer` will be converted to runtime calls to cuda runtime
api and these are not supported in device code. assignment in OpenACC
region will be handled by the OpenACC code gen so we avoid to generate
data transfer on them.
Commit: 6421dcc0a978900091cc7aa8fa443746602cb442
https://github.com/llvm/llvm-project/commit/6421dcc0a978900091cc7aa8fa443746602cb442
Author: Haopeng Liu <153236845+haopliu at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Log Message:
-----------
[NFC] [DSE] Refactor DSE (#100956)
Refactor DSE with MemoryDefWrapper and MemoryLocationWrapper.
Normally, one MemoryDef accesses one MemoryLocation. With "initializes"
attribute, one MemoryDef (like call instruction) could initialize
multiple MemoryLocations.
Refactor DSE as a preparation to apply "initializes" attribute in DSE in
a follow-up PR
(https://github.com/llvm/llvm-project/commit/58dd8a440343055b1a4929d72317218e912c16fd).
Commit: 22ba3511087c85e3b1d4cad686f8d9c3aa6f8088
https://github.com/llvm/llvm-project/commit/22ba3511087c85e3b1d4cad686f8d9c3aa6f8088
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
Log Message:
-----------
[RISCV][SLP] Test for <3 x Ty> reductions which require reordering
These tests show a vectorizable reduction where the order of the
reduction has been adjusted so that profitable vectorization requires
a reordering of the computation. We currently have no reordering
in SLP for non-power-of-two vectors, so this doesn't work.
Note that due to reassociation performed in the standard pipeline,
this is actually the canonical form for a reduction reaching SLP.
Commit: 26b0bef192be1a3adc250af460c2e728a1ca5a64
https://github.com/llvm/llvm-project/commit/26b0bef192be1a3adc250af460c2e728a1ca5a64
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
Log Message:
-----------
AMDGPU: Use pattern to select instruction for intrinsic llvm.fptrunc.round (#105761)
Use GCNPat instead of Custom Lowering to select instructions for
intrinsic llvm.fptrunc.round. "SupportedRoundMode : TImmLeaf" is used as
a predicate to select only when the rounding mode is supported.
"as_hw_round_mode : SDNodeXForm" is developed to translate the round
modes to the corresponding ones that hardware recognizes.
Commit: c1248c9d64e9210554571283980156b1d85cfe09
https://github.com/llvm/llvm-project/commit/c1248c9d64e9210554571283980156b1d85cfe09
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaCXX/vector.cpp
Log Message:
-----------
[Clang] prevent assertion failure when converting vectors to int/float with invalid expressions (#105727)
Fixes #105486
Commit: e9eaf19eb605c14bed7a0f76d206c13a8eaf842f
https://github.com/llvm/llvm-project/commit/e9eaf19eb605c14bed7a0f76d206c13a8eaf842f
Author: Dávid Ferenc Szabó <30732159+dfszabo at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
A llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
Log Message:
-----------
[CodeGen] Allow mixed scalar type constraints for inline asm (#65465)
GCC supports code like "asm volatile ("" : "=r" (i) : "0" (f))" where i
is integer type and f is floating point type. Currently this code
produces an error with Clang. The change allows mixed scalar types
between input and output constraints.
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: ff04c5b2e69481fc3b828bfcf32e05ff7a2c4b05
https://github.com/llvm/llvm-project/commit/ff04c5b2e69481fc3b828bfcf32e05ff7a2c4b05
Author: Dan Liew <dan at su-root.co.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaPseudoObject.cpp
M clang/lib/Sema/SemaStmt.cpp
Log Message:
-----------
[NFC][Sema] Move `Sema::AssignmentAction` into its own scoped enum (#106453)
The primary motivation behind this is to allow the enum type to be
referred to earlier in the Sema.h file which is needed for #106321.
It was requested in #106321 that a scoped enum be used (rather than
moving the enum declaration earlier in the Sema class declaration).
Unfortunately doing this creates a lot of churn as all use sites of the
enum constants had to be changed. Appologies to all downstream forks in
advanced.
Note the AA_ prefix has been dropped from the enum value names as they
are now redundant.
Commit: a0441ced7a770036e00610989e2fabba5caeb31b
https://github.com/llvm/llvm-project/commit/a0441ced7a770036e00610989e2fabba5caeb31b
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/test/SemaTemplate/temp_arg_nontype.cpp
Log Message:
-----------
[NFC] whitespace cleanup on clang/test/SemaTemplate/temp_arg_nontype.cpp
Commit: a87105121dd300752c19024ebaf93319c2781a8b
https://github.com/llvm/llvm-project/commit/a87105121dd300752c19024ebaf93319c2781a8b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libc/config/gpu/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-macros/stdlib-macros.h
M libc/include/stdlib.h.def
M libc/newhdrgen/yaml/stdlib.yaml
M libc/spec/stdc.td
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/strtod_l.cpp
A libc/src/stdlib/strtod_l.h
A libc/src/stdlib/strtof_l.cpp
A libc/src/stdlib/strtof_l.h
A libc/src/stdlib/strtol_l.cpp
A libc/src/stdlib/strtol_l.h
A libc/src/stdlib/strtold_l.cpp
A libc/src/stdlib/strtold_l.h
A libc/src/stdlib/strtoll_l.cpp
A libc/src/stdlib/strtoll_l.h
A libc/src/stdlib/strtoul_l.cpp
A libc/src/stdlib/strtoul_l.h
A libc/src/stdlib/strtoull_l.cpp
A libc/src/stdlib/strtoull_l.h
Log Message:
-----------
[libc] Implement locale variants for 'stdlib.h' functions (#105718)
Summary:
This provides the `_l` variants for the `stdlib.h` functions. These are
just copies of the same entrypoint and don't do anything with the locale
information.
Commit: 5c019bdb7a008cf6465972d4affd8b2802465722
https://github.com/llvm/llvm-project/commit/5c019bdb7a008cf6465972d4affd8b2802465722
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libc/config/gpu/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/string.h.def
M libc/newhdrgen/yaml/string.yaml
M libc/spec/stdc.td
M libc/src/string/CMakeLists.txt
A libc/src/string/strcoll_l.cpp
A libc/src/string/strcoll_l.h
A libc/src/string/strxfrm_l.cpp
A libc/src/string/strxfrm_l.h
Log Message:
-----------
[libc] Add support for 'string.h' locale variants (#105719)
Summary:
This adds the locale variants of the string functions. As previously,
these do not use the locale information at all and simply copy the
non-locale version which expects the "C" locale.
Commit: ba5e8fcecea20da0a796b85e20d6292eb1447b6c
https://github.com/llvm/llvm-project/commit/ba5e8fcecea20da0a796b85e20d6292eb1447b6c
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/unittests/Runtime/CommandTest.cpp
Log Message:
-----------
[flang] Adjust execute_command_line intrinsic return values for AIX (NFC) (#106472)
Commit: 74938ab84dbfdedc6af7a276ebd67201b5eb78e5
https://github.com/llvm/llvm-project/commit/74938ab84dbfdedc6af7a276ebd67201b5eb78e5
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] add true16/fake16 flag to gfx12 dasm tests (#106469)
add true16/fake16 flag to gfx12 dasm tests including vop1, vop1_dpp,
vop3_from_vop1 and vop3_from_vop1_dpp. This is a test only change.
Commit: 59762a0ecf64cbf6ac20c41ae75666cd87519f26
https://github.com/llvm/llvm-project/commit/59762a0ecf64cbf6ac20c41ae75666cd87519f26
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Log Message:
-----------
[RISCV] Add coverage for <3 x float> reduction with neutral start
We can do slightly better on the neutral value when we have nsz.
Commit: d5c292d8ef590f64d26c16d12afebb6ad7f50373
https://github.com/llvm/llvm-project/commit/d5c292d8ef590f64d26c16d12afebb6ad7f50373
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
M llvm/test/MachineVerifier/test_g_splat_vector.mir
Log Message:
-----------
[GISel][RISCV] Correctly handle scalable vector shuffles of pointer vectors in IRTranslator. (#106580)
Commit: aeedab77b596f858b0c53923657fc8c190d48ea8
https://github.com/llvm/llvm-project/commit/aeedab77b596f858b0c53923657fc8c190d48ea8
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/odd_store.ll
Log Message:
-----------
[SLP]Correctly decide if the non-power-of-2 number of stores can be vectorized.
Need to consider the maximum type size in the graph before doing attempt
for the vectorization of non-power-of-2 number of elements, which may be
less than MinVF.
Commit: f08f9cd9713332c939889ab34f5355b77f12f82b
https://github.com/llvm/llvm-project/commit/f08f9cd9713332c939889ab34f5355b77f12f82b
Author: Florian Mayer <fmayer at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
A llvm/test/Instrumentation/HWAddressSanitizer/attrinfer.ll
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll
M llvm/test/Instrumentation/HWAddressSanitizer/hwasan-pass-second-run.ll
M llvm/test/Instrumentation/HWAddressSanitizer/mem-attr.ll
Log Message:
-----------
[HWASan] remove incorrectly inferred attributes (#106565)
assume all functions used in a HWASan module potentially touch shadow
memory (and short granules).
Commit: 0141a3cde4d8f2c8ff9e957f981f37e65a69a325
https://github.com/llvm/llvm-project/commit/0141a3cde4d8f2c8ff9e957f981f37e65a69a325
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/stack-addr-ps.c
Log Message:
-----------
[analyzer] Fix nullptr dereference for symbols from pointer invalidation (#106568)
As reported in
https://github.com/llvm/llvm-project/pull/105648#issuecomment-2317144635
commit 08ad8dc7154bf3ab79f750e6d5fb7df597c7601a
introduced a nullptr dereference in the case when store contains a
binding to a symbol that has no origin region associated with it, such
as the symbol generated when a pointer is passed to an opaque function.
Commit: 66927fb95abef9327b453d7213c5df7d641269be
https://github.com/llvm/llvm-project/commit/66927fb95abef9327b453d7213c5df7d641269be
Author: Florian Mayer <fmayer at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
R llvm/test/Instrumentation/HWAddressSanitizer/attrinfer.ll
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll
M llvm/test/Instrumentation/HWAddressSanitizer/hwasan-pass-second-run.ll
M llvm/test/Instrumentation/HWAddressSanitizer/mem-attr.ll
Log Message:
-----------
Revert "[HWASan] remove incorrectly inferred attributes" (#106622)
Reverts llvm/llvm-project#106565
Broke clang tests
Commit: c4906588ce47de33d59bcd95f3e82ce2c3e61c23
https://github.com/llvm/llvm-project/commit/c4906588ce47de33d59bcd95f3e82ce2c3e61c23
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
Log Message:
-----------
[VPlan] Use skipCostComputation when pre-computing induction costs.
This ensures we skip any instructions identified to be ignored by the
legacy cost model as well. Fixes a divergence between legacy and
VPlan-based cost model.
Fixes https://github.com/llvm/llvm-project/issues/106417.
Commit: 1f0d545ec38ceaafa7ca94aa659be125bdcd721f
https://github.com/llvm/llvm-project/commit/1f0d545ec38ceaafa7ca94aa659be125bdcd721f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libcxx/include/__type_traits/make_unsigned.h
M libcxx/include/istream
Log Message:
-----------
[libc++] Fix wraparound issue with -fsanitize=integer in string operator>> (#106263)
Fixes #106261
rdar://133991190
Commit: 049b60c5bb7e774b74772c6b89c72593f73a89b0
https://github.com/llvm/llvm-project/commit/049b60c5bb7e774b74772c6b89c72593f73a89b0
Author: Tom Honermann <tom.honermann at intel.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
Log Message:
-----------
[NFC][Clang] Avoid potential null pointer dereferences in Sema::AddInitializerToDecl(). (#106235)
Control flow analysis performed by a static analysis tool revealed the
potential for null pointer dereferences to occur in conjunction with the
`Init` parameter in `Sema::AddInitializerToDecl()`. On entry to the
function, `Init` is required to be non-null as there are multiple
potential branches that unconditionally dereference it. However, there
were two places where `Init` is compared to null thus implying that
`Init` is expected to be null in some cases. These checks appear to be
purely defensive checks and thus unnecessary. Further, there were
several cases where code checked `Result`, a variable of type
`ExprResult`, for an invalid value, but did not check for a valid but
null value and then proceeded to unconditionally dereference the
potential null result. This change elides the unnecessary defensive
checks and changes some checks for an invalid result to instead branch
on an unusable result (either an invalid result or a valid but null
result).
Commit: 593526f3fb138069fc93b14d08320d0e3f67c707
https://github.com/llvm/llvm-project/commit/593526f3fb138069fc93b14d08320d0e3f67c707
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCExpr.h
Log Message:
-----------
[X86] Use MCRegister instead of int64_t in X86MCExpr. NFC (#106569)
Commit: 4ca817d0511b2c36b2f5d242e0c8f90a7a9c4f14
https://github.com/llvm/llvm-project/commit/4ca817d0511b2c36b2f5d242e0c8f90a7a9c4f14
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/scalablevec-combiner-crash.ll
Log Message:
-----------
[GlobalISel] Add bail outs for scalable vectors to some combines. (#106496)
These combines call getNumElements() which isn't valid for scalable
vectors.
Commit: 182708680bbe34b579a09b2dbc3215b519b2473f
https://github.com/llvm/llvm-project/commit/182708680bbe34b579a09b2dbc3215b519b2473f
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Add ExtractValueInst. (#106613)
Commit: 412e3e394dbd1b7d8655639e161ed4dbd5505c96
https://github.com/llvm/llvm-project/commit/412e3e394dbd1b7d8655639e161ed4dbd5505c96
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/CodeGen/X86/fake-use-hpfloat.ll
M llvm/test/CodeGen/X86/fake-use-vector.ll
M llvm/test/DebugInfo/X86/fake-use.ll
Log Message:
-----------
[ExtendLifetimes][NFC] Add explicit triple to remaining fake-use tests
One of the tests for the new fake use intrinsic are failing on darwin
buildbots due to relying on behaviour for their expected triple; this
commit adds explicit triples to the few remaining fake-use tests that
didn't have them.
Fixes commit 3d08ade (#86149).
Buildbot failures:
https://lab.llvm.org/buildbot/#/builders/23/builds/2505
Commit: 7284e0f3a4f8924a0f69f654db8c4b4d00d232cb
https://github.com/llvm/llvm-project/commit/7284e0f3a4f8924a0f69f654db8c4b4d00d232cb
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ItaniumMangle.cpp
A clang/test/CodeGenCXX/GH106182.cpp
A clang/test/SemaCXX/GH106182.cpp
Log Message:
-----------
[clang] mangle placeholder for deduced type as a template-prefix (#106335)
As agreed on https://github.com/itanium-cxx-abi/cxx-abi/issues/109 these
placeholders should be mangled as a `template-prefix` production.
```
<template-prefix> ::= <template unqualified-name> # global template
::= <prefix> <template unqualified-name> # nested template
::= <template-param> # template template parameter
::= <substitution>
```
Previous to this patch, the template template parameter case was not
handled, and template template parameters were incorrectly being handled
as unqualified-names.
Before #95202, DeducedTemplateType was not canonicalized correctly, so
that template template parameter declarations were retained
uncanonicalized.
After #95202, they are correctly canonicalized, but this now leads to
these TTPs being anonymous entities, where the mangling implementation
correctly doesn't expect an anonymous declaration of this kind, leading
to a crash.
Fixes #106182.
Commit: 4caf0196c042601b1c442a5726a157fead00ecc7
https://github.com/llvm/llvm-project/commit/4caf0196c042601b1c442a5726a157fead00ecc7
Author: Connie Zhu <60797237+connieyzhu at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
A clang/test/Modules/compare-file-size.py
M clang/test/Modules/reduced-bmi-size.cppm
Log Message:
-----------
[clang][test] Rewrote test using command substitution to work with lit internal shell syntax (#105902)
This patch rewrites a test that uses command substitution `$()` and the
`stat` command, which are not supported by lit's internal shell. Instead
of using this syntax to perform the file size comparison done in this
test, a Python script is used instead to perform the same operation.
Fixes https://github.com/llvm/llvm-project/issues/102384.
Commit: aa91d90cb07d72b32176a966fe798ab71ecb0a76
https://github.com/llvm/llvm-project/commit/aa91d90cb07d72b32176a966fe798ab71ecb0a76
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/test/CodeGen/PowerPC/fma-negate.ll
M llvm/test/CodeGen/PowerPC/fp-strict.ll
M llvm/test/CodeGen/PowerPC/vec_abs.ll
M llvm/test/CodeGen/PowerPC/vec_fneg.ll
Log Message:
-----------
[LegalizeVectorOps][PowerPC] Use xor to expand fneg. (#106595)
This preserves the semantis of fneg and matches what we do in
LegalizeDAG.
I kept the legal FSUB check to force unrolling for some targets that
don't have FSUB but have XOR. On Aarch64, using xor broke some tests that
expected to see a (v1f64 (fma (insertvector_elt (f64 (fneg
(extractvectorelt X)))))) pattern.
Commit: e51fc36c385d756ccbc2be8c47c52af207c3aead
https://github.com/llvm/llvm-project/commit/e51fc36c385d756ccbc2be8c47c52af207c3aead
Author: rjmansfield <rjmansfield at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M compiler-rt/test/lsan/TestCases/create_thread_leak.cpp
Log Message:
-----------
[lsan][test] Allow testcase to execute on remote targets without not utility (#87350)
Commit: cc943a67d114e28c28f561c3b1a48ff2003264ce
https://github.com/llvm/llvm-project/commit/cc943a67d114e28c28f561c3b1a48ff2003264ce
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
Log Message:
-----------
[SLP]Fix PR106626: trye several attempts for lookup values, if not found.
If the value is used in Scalar several times, the first attempt to find
its position in the node (if ReuseShuffleIndices and ReorderIndices not
empty) may fail. In this case need to find another copy of the same
value and try again.
Fixes https://github.com/llvm/llvm-project/issues/106626
Commit: a1441ca74708a557606bf68d42fca40bb03dbd74
https://github.com/llvm/llvm-project/commit/a1441ca74708a557606bf68d42fca40bb03dbd74
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M flang/lib/Frontend/FrontendActions.cpp
A flang/test/Driver/print-pipeline-passes.f90
Log Message:
-----------
[flang][Driver] Add support for -mllvm -print-pipeline-passes
The behavior deliberately mimics that of clang. Ideally, -print-pipeline-passes
should be a first-class driver option. Notes to this effect have been added in
the appropriate places in both flang and clang.
---------
Co-authored-by: Tarun Prabhu <tarun.prabhu at gmail.com>
Commit: dac1f7ba8eefb6931abb68a6aebb273de5a60f74
https://github.com/llvm/llvm-project/commit/dac1f7ba8eefb6931abb68a6aebb273de5a60f74
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
Log Message:
-----------
[NVPTX] fixup incorrect rounding mode for int to float conversion (#106600)
`uitofp` and `sitofp` instructions use the default rounding mode which
is defined as round-to-nearest.
Commit: ec68dc1ca4d967b599f1202855917d5ec9cae52f
https://github.com/llvm/llvm-project/commit/ec68dc1ca4d967b599f1202855917d5ec9cae52f
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M compiler-rt/lib/interception/interception.h
M compiler-rt/lib/interception/interception_type_test.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
Log Message:
-----------
[compiler-rt] Work around incompatible Windows definitions of (S)SIZE_T
The interceptor types are supposed to match size_t (and the non-Windows
ssize_t) exactly, but on 32-bit Windows `size_t` uses `unsigned int`
whereas `SIZE_T` is `unsigned long`. The current definition results in
`uptr` not matching `uintptr_t` since we otherwise get typedef
redefinition errors. Work around this by using a #define instead of
a typedef when defining SIZE_T.
It would probably be cleaner to stop using these uppercase types, but
that is a rather invasive change and this one is the minimal change to
allow uptr to match uintptr_t on Windows.
To ensure this compiles on Windows, we also remove the interceptor.h
defines of uptr (that do not always match __sanitizer::uptr) and rely
on __sanitizer::uptr instead. The interceptor types most likely predate
those other types so clean up the unnecessary definition while here.
This also reverts commit 18e06e3e2f3d47433e1ed323b8725c76035fc1ac and
commit bb27dd853a713866c025a94ead8f03a1e25d1b6e.
Reviewed By: mstorsjo, vitalybuka
Pull Request: https://github.com/llvm/llvm-project/pull/106311
Commit: 9df92cbd1addb03c7169f05cf3b628f88c610224
https://github.com/llvm/llvm-project/commit/9df92cbd1addb03c7169f05cf3b628f88c610224
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[compiler-rt] Remove duplicates of sanitizer_common functions
These functions in interception_win.cpp already exist in
sanitizer_common. Use those instead.
Reviewed By: mstorsjo
Pull Request: https://github.com/llvm/llvm-project/pull/106488
Commit: dbbfc952f0d4703b89fa238e2aba98f1229fb972
https://github.com/llvm/llvm-project/commit/dbbfc952f0d4703b89fa238e2aba98f1229fb972
Author: Luke Lau <luke at igalia.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
Log Message:
-----------
[RISCV] Separate ActiveElementsAffectResult into VL and Mask flags (#106517)
In #106110 we had to mark v[f]slide1down.vx as
ActiveElementsAffectResult since the elements in the body depend on VL.
However it doesn't depend on the mask, so this was overly conservative
and broke the vmerge peephole.
We can recover this by splitting up ActiveElementsAffectResult into VL
and Mask bits, so we can more accurately model v[f]slide1down.vx and
re-enable the peephole.
Commit: 034f2b380bd2d84e8cfbcb647b50602711d170c7
https://github.com/llvm/llvm-project/commit/034f2b380bd2d84e8cfbcb647b50602711d170c7
Author: vporpo <vporpodas at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
A llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/CMakeLists.txt
M llvm/lib/SandboxIR/SandboxIR.cpp
A llvm/lib/SandboxIR/Type.cpp
M llvm/unittests/SandboxIR/CMakeLists.txt
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
A llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[SandboxIR] Implement SandboxIR Type (#106294)
This patch implements sandboxir::Type, a thin wrapper of llvm::Type.
This is designed very similarly to sandbox::Value. Context owns all
sandboxir::Type objects and maintains a map between llvm::Type and
sandboxir::Type.
There are a couple of reasons for migrating from llvm::Type to
sandboxir::Type:
- Creating an llvm::Type from within SandboxIR-only code doesn't work
well because it requires you to pass llvm::Context to functions like
llvm::Type::getInt32Ty(C), but you wouldn't normally have access to
llvm::Context C. In unit tests this is not such a big deal because you
have access to both, but it will become an issue in SandboxIR-only code.
- Not being able to get the sandboxir::Context from llvm::Type results
in awkward sandboir APIs with additional sandboxir::Context arguments.
- llvm::Type::getContext() can basically give you access to the whole
LLVM IR, which we should try to avoid.
Commit: 46fe36a4295f05d5d3731762e31fc4e6e99863e9
https://github.com/llvm/llvm-project/commit/46fe36a4295f05d5d3731762e31fc4e6e99863e9
Author: Alex Richardson <alexrichardson at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
Revert "[compiler-rt] Remove duplicates of sanitizer_common functions"
This works for MinGW, but the MSVC linker apparently doens't pull in
those symbols. Reverting for now since I won't be able to reproduce it today.
https://lab.llvm.org/buildbot/#/builders/107/builds/2337
This reverts commit 9df92cbd1addb03c7169f05cf3b628f88c610224.
Commit: cdaebf6f0e2be65f55011ccb2f1bc3b9199b6285
https://github.com/llvm/llvm-project/commit/cdaebf6f0e2be65f55011ccb2f1bc3b9199b6285
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
A llvm/test/CodeGen/NVPTX/compute-ptx-value-vts.ll
A llvm/test/CodeGen/NVPTX/vector-returns.ll
Log Message:
-----------
[NVPTX] Fix crash caused by ComputePTXValueVTs (#104524)
When [lowering return
values](https://github.com/llvm/llvm-project/blob/99a10f1fe8a7e4b0fdb4c6dd5e7f24f87e0d3695/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp#L3422)
from LLVM IR to SelectionDAG, we check that [the number of values
`SelectionDAG` tells us to return is equal to the number of values that
`ComputePTXValueVTs()` tells us to
return](https://github.com/llvm/llvm-project/blob/99a10f1fe8a7e4b0fdb4c6dd5e7f24f87e0d3695/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp#L3441).
However, this check can fail on valid IR. For example:
```
define <6 x half> @foo() {
ret <6 x half> zeroinitializer
}
```
`ComputePTXValueVTs()` tells us to return ***3*** `v2f16` values, while
`SelectionDAG` tells us to return ***6*** `f16` values. Thus, the
compiler will crash.
`ComputePTXValueVTs()` [supports all `half` element vectors with an even
number of
elements](https://github.com/llvm/llvm-project/blob/99a10f1fe8a7e4b0fdb4c6dd5e7f24f87e0d3695/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp#L213).
Whereas `SelectionDAG` [only supports power-of-2 sized
vectors](https://github.com/llvm/llvm-project/blob/4e078e3797098daa40d254447c499bcf61415308/llvm/lib/CodeGen/TargetLoweringBase.cpp#L1580).
This is the root of the discrepancy.
Assuming that the developers who added the code to
`ComputePTXValueVTs()` overlooked this, I've restricted
`ComputePTXValueVTs()` to compute the same number of return values as
`SelectionDAG`, instead of extending `SelectionDAG` to support
non-power-of-2 sized vectors.
Commit: 1991aa6b48845f31ff4e69a960b04086ff68ce3e
https://github.com/llvm/llvm-project/commit/1991aa6b48845f31ff4e69a960b04086ff68ce3e
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/Analysis/FunctionPropertiesAnalysis.h
M llvm/lib/Analysis/FunctionPropertiesAnalysis.cpp
M llvm/lib/Analysis/MLInlineAdvisor.cpp
M llvm/unittests/Analysis/FunctionPropertiesAnalysisTest.cpp
Log Message:
-----------
Reapply "[nfc][mlgo] Incrementally update DominatorTreeAnalysis in FunctionPropertiesAnalysis (#104867) (#106309)
Reverts c992690179eb5de6efe47d5c8f3a23f2302723f2.
The problem is that if there is a sequence "{delete A->B} {delete A->B}
{insert A->B}" the net result is "{delete A->B}", which is not what we
want.
Duplicate successors may happen in cases like switch statements (as
shown in the unit test).
The second problem was that in `invoke` cases, some edges we speculate may get deleted don't, but are also not reachable from the inlined call site's basic block. We just need to check which edges are actually not present anymore.
The fix is to sanitize the list of deletes, just like we do for inserts.
Commit: 7579787e05966f21684dd4b4a15b9deac13d09e1
https://github.com/llvm/llvm-project/commit/7579787e05966f21684dd4b4a15b9deac13d09e1
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly identify token-pasted record names (#106484)
See
https://github.com/llvm/llvm-project/pull/89706#issuecomment-2315549955.
Commit: e29c5f387f4a4aff039c01bde9eedeb6bd97951f
https://github.com/llvm/llvm-project/commit/e29c5f387f4a4aff039c01bde9eedeb6bd97951f
Author: Elvis Wang <110374989+ElvisWang123 at users.noreply.github.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll
Log Message:
-----------
[RISCV][TTI] Add legality check of vector of address for gather/scatter. (#106481)
This patch add a legality check that checks if target machine support
vector of address in `isLegalMaskedGatherScatter()`.
Commit: 12b0257f5aa2966ebbd3c7e2a6c8a73f00dab3d3
https://github.com/llvm/llvm-project/commit/12b0257f5aa2966ebbd3c7e2a6c8a73f00dab3d3
Author: Florian Mayer <fmayer at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/test/CodeGen/address-safety-attr-flavors.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
A llvm/test/Instrumentation/HWAddressSanitizer/attrinfer.ll
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll
M llvm/test/Instrumentation/HWAddressSanitizer/hwasan-pass-second-run.ll
M llvm/test/Instrumentation/HWAddressSanitizer/mem-attr.ll
Log Message:
-----------
Reapply "[HWASan] remove incorrectly inferred attributes" (#106622) (#106624)
This reverts commit 66927fb95abef9327b453d7213c5df7d641269be.
Fixed clang tests
Commit: ca2351dd142bac574021f48f135a9f9383c41128
https://github.com/llvm/llvm-project/commit/ca2351dd142bac574021f48f135a9f9383c41128
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/skip-func-def-odr-with-pch.cppm
Log Message:
-----------
[C++20] [Modules] Skip checking ODR for merged context in GMF
Solve https://github.com/clangd/clangd/issues/2094
Due clangd will enable PCH automatically, the previous mechanism to skip
ODR check in GMF may be invalid. This patch fixes this for a case.
Commit: ddaf2e2d2946b4938512794f26cab3a3fe53b227
https://github.com/llvm/llvm-project/commit/ddaf2e2d2946b4938512794f26cab3a3fe53b227
Author: Florian Mayer <fmayer at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll
Log Message:
-----------
[HWASan] add OptimizationRemark for alloca safety (#105872)
Commit: e004566547bb13386ee30c78176dd7988c42860a
https://github.com/llvm/llvm-project/commit/e004566547bb13386ee30c78176dd7988c42860a
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAliasAnalysis.cpp
M llvm/test/CodeGen/NVPTX/nvptx-aa.ll
Log Message:
-----------
[NVPTX][AA] Traverse use-def chain to find non-generic addrspace (#106477)
Address space information may be encoded anywhere along the use-def
chain. Take advantage of this by traversing the chain until we find a
non-generic addrspace.
Commit: e00e9a3f8294c9b96cb0328bf136fab72aeec749
https://github.com/llvm/llvm-project/commit/e00e9a3f8294c9b96cb0328bf136fab72aeec749
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang-c/Index.h
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/ASTNodeTraverser.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Basic/TypeNodes.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Serialization/TypeBitCodes.def
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXType.cpp
Log Message:
-----------
[HLSL] Add HLSLAttributedResourceType (#106181)
Introducing `HLSLAttributedResourceType` - a new type that is similar to
`AttributedType` but with additional data specific to HLSL resources.
`AttributeType` currently only stores an attribute kind and no
additional data from the type attribute parameters. This does not really
work for HLSL resources since its type attributes contain non-boolean
values that need to be retained as well.
For example:
```
template <typename T> class RWBuffer {
__hlsl_resource_t [[hlsl::resource_class(uav)]] [[hlsl::is_rov]] handle;
};
```
The data `HLSLAttributedResourceType` needs to eventually store are:
- resource class (SRV, UAV, CBuffer, Sampler)
- texture dimension(1-3)
- flags is_rov, is_array, is_feedback and is_multisample
- contained type
All of these values except contained type will be stored in
`HLSLAttributedResourceType::Attributes` struct and accessed
individually via the fields. There is also `Data` alias that covers all
of these values as a `unsigned` which is used for hashing and the AST
type serialization.
During type attribute processing all HLSL type attributes will be
validated and collected by SemaHLSL (by
`SemaHLSL::handleResourceTypeAttr`) and in the end combined into a
single `HLSLAttributedResourceType` instance (in
`SemaHLSL::ProcessResourceTypeAttributes`). `SemaHLSL` will also need to
short-term store the `TypeLoc` information for the new type that will be
grabbed by `TypeSpecLocFiller` soon after the type is created.
Part 1/2 of #104861
Commit: d4c519e7b2ac21350ec08b23eda44bf4a2d3c974
https://github.com/llvm/llvm-project/commit/d4c519e7b2ac21350ec08b23eda44bf4a2d3c974
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
A flang/include/flang/Lower/Cuda.h
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/CUDA/cuda-allocatable.cuf
Log Message:
-----------
[flang][cuda] Do inline allocation/deallocation in device code (#106628)
ALLOCATE and DEALLOCATE statements can be inlined in device function.
This patch updates the condition that determined to inline these actions
in lowering.
This avoid runtime calls in device function code and can speed up the
execution.
Also move `isCudaDeviceContext` from `Bridge.cpp` so it can be used
elsewhere.
Commit: 24e791b4164986a1ca7776e3ae0292ef20d20c47
https://github.com/llvm/llvm-project/commit/24e791b4164986a1ca7776e3ae0292ef20d20c47
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Log Message:
-----------
[ARM] Use MCRegister instead of unsigned for RegisterReqs in ARMAsmParser.
Commit: b65fc7e91a20904a08e28a51fbf98137e94ae262
https://github.com/llvm/llvm-project/commit/b65fc7e91a20904a08e28a51fbf98137e94ae262
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/convert.fir
Log Message:
-----------
[flang][fir] allow fir.convert from and to !llvm.ptr type (#106590)
Allow some interaction between LLVM and FIR dialect by allowing
conversion between FIR memory types and llvm.ptr type.
This is meant to help experimentation where FIR and LLVM dialect
coexists, and is useful to deal with cases where LLVM type makes it
early into the MLIR produced by flang, like when inserting LLVM stack
intrinsic here:
https://github.com/llvm/llvm-project/blob/0a00d32c5f88fce89006dcde6e235bc77d7b495e/flang/lib/Optimizer/Transforms/StackReclaim.cpp#L57
Commit: a527248a3c2d638b0c92a06992f3f1c1f80842ad
https://github.com/llvm/llvm-project/commit/a527248a3c2d638b0c92a06992f3f1c1f80842ad
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Semantics/canonicalize-acc.cpp
M flang/lib/Semantics/canonicalize-directives.cpp
A flang/test/Lower/OpenACC/acc-loop-and-cpu-dir.f90
M flang/test/Semantics/loop-directives.f90
Log Message:
-----------
[flang][acc] allow and ignore DIR between ACC and loops (#106522)
The current pattern was failing OpenACC semantics in acc parse tree
canonicalization:
```
!acc loop
!dir vector aligned
do i=1,n
...
```
Fix it by moving the directive before the OpenACC construct node.
Note that I think it could make sense to propagate the $dir info to the
acc.loop, at least with classic flang, the $dir seems to make a
difference. This is not done here since few directives are supported
anyway.
Commit: 448d8fa880be5cae0f63c3b248f07f647013a5a4
https://github.com/llvm/llvm-project/commit/448d8fa880be5cae0f63c3b248f07f647013a5a4
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang-tools-extra/clangd/ModulesBuilder.cpp
Log Message:
-----------
[NFC] [clangd] [Modules] Extract ModuleFile class and IsModuleFileUpToDate function
This patch extracts ModuleFile class from StandalonePrerequisiteModules
so that we can reuse it further. And also we implement
IsModuleFileUpToDate function to implement
StandalonePrerequisiteModules::CanReuse. Both of them aims to ease the
future improvements to the support of modules in clangd. And both of
them should be NFC.
Commit: cd634f57c10dedbe4f908889dece2c4460b702c9
https://github.com/llvm/llvm-project/commit/cd634f57c10dedbe4f908889dece2c4460b702c9
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M compiler-rt/lib/builtins/aarch64/sme-abi-init.c
Log Message:
-----------
[compiler-rt][AArch64][Android] Use getauxval on Android. (#102979)
__getauxval is a libgcc function that doesn't exist on Android.
Also on Linux let's use getauxval as it is anyway used other places in compiler-rt.
Commit: d68059bcfd1cc27e378c43b1f16019c5baccb06d
https://github.com/llvm/llvm-project/commit/d68059bcfd1cc27e378c43b1f16019c5baccb06d
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang-tools-extra/clangd/ModulesBuilder.cpp
Log Message:
-----------
[NFC] [clangd] [Modules] Change the argument type of IsModuleFileUpToDate to reference
It is better to use references instead of pointers as the argument type
of IsModuleFileUpToDate. Since the PrerequisiteModules is always
expected to exist.
Commit: 8ca6401fdd36c17a8d68a8fb06b7d43c2540a027
https://github.com/llvm/llvm-project/commit/8ca6401fdd36c17a8d68a8fb06b7d43c2540a027
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-directive-structure.h
A flang/test/Lower/OpenACC/acc-shortloop-ignore.f90
M flang/test/Semantics/OpenACC/acc-routine-validity.f90
M llvm/include/llvm/Frontend/OpenACC/ACC.td
Log Message:
-----------
[flang][openacc] parse and ignore non-standard shortloop clause (#106564)
shortloop is a non standard OpenACC extension
(https://docs.nvidia.com/hpc-sdk/pgi-compilers/2015/pgirn157.pdf) that
can be found on loop directives.
f18 parser was choking when seeing it. Since it can be found in existing
apps and is mainly an optimization hint, parse it on loop directives and
ignore it with a warning.
For the records, here is shortloop meaning according to the manual linked above:
"If the shortloop clause appears on a loop directive with the vector clause, it tells the compiler that the
loop trip count is less than or equal to the number of vector lanes created for that loop. This means the
value of the vector() clause on the loop directive in a kernels region, or the value of the
vector_length() clause on the parallel directive in a parallel region will be greater than or
equal to the loop trip count. This allows the compiler to generate more efficient code for the loop"
Commit: 89e6a288674c9fae33aeb5448c7b1fe782b2bf53
https://github.com/llvm/llvm-project/commit/89e6a288674c9fae33aeb5448c7b1fe782b2bf53
Author: Daniil Fukalov <dfukalov at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/include/llvm/ADT/ConcurrentHashtable.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/ExecutorSharedMemoryMapperService.h
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/MemoryMapper.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/ExecutorSharedMemoryMapperService.cpp
M llvm/lib/ExecutionEngine/Orc/TaskDispatch.cpp
M llvm/lib/Support/BalancedPartitioning.cpp
M llvm/lib/Support/ErrorHandling.cpp
M llvm/lib/Support/LockFileManager.cpp
M llvm/lib/Support/RWMutex.cpp
M llvm/lib/Support/Unix/Process.inc
M llvm/tools/lli/ChildTarget/ChildTarget.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/Error.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/llvm-jitlink-executor.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-mt/llvm-mt.cpp
M llvm/tools/llvm-reduce/deltas/Delta.cpp
M llvm/unittests/Analysis/MLModelRunnerTest.cpp
M llvm/unittests/ExecutionEngine/Orc/SharedMemoryMapperTest.cpp
M llvm/unittests/ExecutionEngine/Orc/TaskDispatchTest.cpp
M llvm/unittests/Support/CrashRecoveryTest.cpp
M llvm/unittests/Support/ManagedStatic.cpp
M llvm/unittests/Support/MemoryBufferTest.cpp
M llvm/unittests/Support/ParallelTest.cpp
M llvm/unittests/Support/Path.cpp
M llvm/unittests/Support/ThreadPool.cpp
M llvm/unittests/Support/Threading.cpp
M llvm/unittests/Support/WithColorTest.cpp
M llvm/unittests/Support/raw_ostream_test.cpp
Log Message:
-----------
[NFC] Add explicit #include llvm-config.h where its macros are used. (#106621)
Without these explicit includes, removing other headers, who implicitly
include llvm-config.h, may have non-trivial side effects.
Commit: d6ad55167094b7b23e71ec6eabfe942e7a485b41
https://github.com/llvm/llvm-project/commit/d6ad55167094b7b23e71ec6eabfe942e7a485b41
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/test/Transforms/PGOProfile/memprof.ll
M llvm/test/Transforms/SCCP/pointer-nonnull.ll
Log Message:
-----------
[IPSCCP] Infer nonnull return attribute (#106553)
Similarly to the existing range attribute inference, also infer the
nonnull attribute on function return values.
I think in practice FunctionAttrs will handle nearly all cases, the main
one I think it doesn't is cases involving branch conditions. But as we
already have the information here, we may as well materialize it.
Commit: e0fa2f1c2957d9783d21460febf103cecac9e19a
https://github.com/llvm/llvm-project/commit/e0fa2f1c2957d9783d21460febf103cecac9e19a
Author: ofAlpaca <frank70199 at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/builtins.cpp
Log Message:
-----------
`__noop` not marked as constexpr #102064 (#105983)
Fixes #102064
Commit: 1693d8eb9aa94b0e8e2395234e6c63b57a2017b7
https://github.com/llvm/llvm-project/commit/1693d8eb9aa94b0e8e2395234e6c63b57a2017b7
Author: Max Beck-Jones <max.beck-jones at arm.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve2-histcnt.ll
Log Message:
-----------
[AArch64][SelectionDAG] Vector splitting and promotion for histogram intrinsic (#103037)
Adds support for wider-than-legal vector types for the histogram
intrinsic (llvm.experimental.vector.histogram.add) by splitting the
vector. Also adds integer promotion for the Inc operand.
Commit: d2b8969b7593fd01991a2089828e6256945874cf
https://github.com/llvm/llvm-project/commit/d2b8969b7593fd01991a2089828e6256945874cf
Author: Kai Luo <gluokai at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/EdgeBundles.cpp
Log Message:
-----------
[EdgeBundles] Correct MBB label name in output graph when `-view-edge-bundles`. NFC. (#106661)
With `-view-edge-bundles`, before the change, the dot file output is
kinda like
```dot
digraph {
"%bb.0" [ shape=box ]
0 -> "%bb.0"
"%bb.0" -> 1
"%bb.0" -> "%bb.1" [ color=lightgray ]
"%bb.0" -> "%bb.6" [ color=lightgray ]
"%bb.1" [ shape=box ]
1 -> "%bb.1"
"%bb.1" -> 1
"%bb.1" -> "%bb.2" [ color=lightgray ]
"%bb.1" -> "%bb.6" [ color=lightgray ]
"%bb.2" [ shape=box ]
1 -> "%bb.2"
"%bb.2" -> 1
"%bb.2" -> "%bb.3" [ color=lightgray ]
"%bb.3" [ shape=box ]
1 -> "%bb.3"
"%bb.3" -> 2
"%bb.3" -> "%bb.4" [ color=lightgray ]
"%bb.4" [ shape=box ]
2 -> "%bb.4"
"%bb.4" -> 2
"%bb.4" -> "%bb.4" [ color=lightgray ]
"%bb.4" -> "%bb.5" [ color=lightgray ]
"%bb.5" [ shape=box ]
2 -> "%bb.5"
"%bb.5" -> 1
"%bb.5" -> "%bb.6" [ color=lightgray ]
"%bb.5" -> "%bb.3" [ color=lightgray ]
"%bb.6" [ shape=box ]
1 -> "%bb.6"
"%bb.6" -> 3
}
```
However, the graph output by graphviz is
The node name corresponding to the MBB is incorrect.
After the change, the node name is consistent with MBB's name.
Commit: ce7c828e085563f29451ec5fac9626c76ebf70ee
https://github.com/llvm/llvm-project/commit/ce7c828e085563f29451ec5fac9626c76ebf70ee
Author: Igor Kudrin <ikudrin at accesssoftek.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
A lldb/test/Shell/Process/elf-core/aarch64-no-NT_ARM_TLS.yaml
A lldb/test/Shell/Process/elf-core/lit.local.cfg
Log Message:
-----------
[lldb][AArch64] Do not crash if NT_ARM_TLS is missing (#106478)
[D156118](https://reviews.llvm.org/D156118) states that this note is
always present, but it is better to check it explicitly, as otherwise
`lldb` may crash when trying to read registers.
Commit: 54916e5784d0fd928ef5b28b2eb99726a395cb3f
https://github.com/llvm/llvm-project/commit/54916e5784d0fd928ef5b28b2eb99726a395cb3f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M .github/workflows/pr-code-format.yml
Log Message:
-----------
[Github] Set code formatting job timeout to 30 minutes (#106674)
This patch sets the timeout of the code formatting job to 30 minutes.
The job is currently failing in specific circumstances and needs to be
reworked, but as a temp hack, change the timeout to 30 minutes so that
we can catch these jobs before they hit the Github Actions timeout limit
of six hours.
Somewhat (hackily) alleviates #79661 slightly.
Commit: d6dc7cf71bf52f866c092e92ce374f0266ebee1a
https://github.com/llvm/llvm-project/commit/d6dc7cf71bf52f866c092e92ce374f0266ebee1a
Author: Danial Klimkin <dklimkin at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Fix bazel build past 89e6a288674c (#106685)
Commit: 0722b8ab8168d9e1aa3413a62c65878f407225ae
https://github.com/llvm/llvm-project/commit/0722b8ab8168d9e1aa3413a62c65878f407225ae
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/test/SemaTemplate/default-arguments.cpp
R clang/test/SemaTemplate/default-parm-init.cpp
Log Message:
-----------
[Clang][NFC] Consolidate tests for default argument substitution (#105617)
Follow-up on 8ac140f39.
The test `SemaTemplate/default-parm-init.cpp` was introduced since the
fix #80288 and mainly did the following things:
- Ensure the default arguments are properly substituted inside either
the primary template & their explicit / out-of-line specializations.
- Ensure the strategy doesn't mess up the substitution of a lambda
expression as a default argument.
The 1st is for the bug of #68490, yet it does some redundant work: each
of the member functions is duplicated twice for the `sizeof` and
`alignof` operators, respectively, and the principle under the hood are
essentially the same. So this patch removes the duplication and reduces
the 8 functions to 4 functions that reveal the same thing.
The 2nd is presumably testing that the fix in #80288 doesn't impact a
complicated substitution. However, that seems unnecessary & unrelated to
the original issue. And more importantly, we don't have any problems
with that ever. Hence, I'll remove that test from this patch.
The test for default arguments is merged into
`SemaTemplate/default-arguments.cpp` with a new namespace, and hopefully
this could reduce the entropy of our testing cases.
Commit: 5b77e254e814eb9a56d31c30a5c8289c07d8a6ff
https://github.com/llvm/llvm-project/commit/5b77e254e814eb9a56d31c30a5c8289c07d8a6ff
Author: wanglei <wanglei at loongson.cn>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/CodeGen/LoongArch/imm.ll
Log Message:
-----------
[LoongArch] Pre-commit test for immediate value materialization using BSTRINS_D
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/106331
Commit: eaf87d32754beb5bec10bab517bf56e25575b48e
https://github.com/llvm/llvm-project/commit/eaf87d32754beb5bec10bab517bf56e25575b48e
Author: wanglei <wanglei at loongson.cn>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.h
M llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/LoongArch/imm.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll
M llvm/test/CodeGen/LoongArch/merge-base-offset.ll
M llvm/test/CodeGen/LoongArch/sextw-removal.ll
M llvm/test/MC/LoongArch/Macros/macros-li.s
Log Message:
-----------
[LoongArch] Optimize for immediate value materialization using BSTRINS_D instruction
Reviewed By: heiher, SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/106332
Commit: 8f4aafb58ceb2c60f8f13d475d0623c696cd5716
https://github.com/llvm/llvm-project/commit/8f4aafb58ceb2c60f8f13d475d0623c696cd5716
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
A llvm/test/Analysis/CostModel/RISCV/cast-half.ll
M llvm/test/Analysis/CostModel/RISCV/cast.ll
Log Message:
-----------
[RISCV][NFC] Splits f16 cast tests into a separate file (#106692)
precommit f16 test for #87506 fp-int conversion
Commit: b294951e3967730ffad14d51297694b1411d7af6
https://github.com/llvm/llvm-project/commit/b294951e3967730ffad14d51297694b1411d7af6
Author: yronglin <yronglin777 at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/CodeGen/compound-literal.c
Log Message:
-----------
[clang][bytecode] Fix the handling of address of a vector (#106558)
The PR https://github.com/llvm/llvm-project/pull/105996 broke taking the
address of a vector:
**compound-literal.c**
```C
typedef int v4i32 __attribute((vector_size(16)));
v4i32 *y = &(v4i32){1,2,3,4};
```
That because the current interpreter handle vector unary operator as a
fallback when the generic code path fail. but the new interpreter was
not. we need to handle `UO_AddrOf` in
`Compiler<Emitter>::VisitVectorUnaryOperator`.
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: 1b32c3e2985f89900030289eaa44e3d92cab85af
https://github.com/llvm/llvm-project/commit/1b32c3e2985f89900030289eaa44e3d92cab85af
Author: Danial Klimkin <dklimkin at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
Add no-op handing for HLSLAttributedResource switch cases (#106698)
New value added in e00e9a3f8294c9b96cb0328bf136fab72aeec749
Commit: a2a93f02930e20930d5ef38464ca9c99eb00ff23
https://github.com/llvm/llvm-project/commit/a2a93f02930e20930d5ef38464ca9c99eb00ff23
Author: kadir çetinkaya <kadircet at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/lib/Basic/SourceManager.cpp
M clang/unittests/Basic/SourceManagerTest.cpp
Log Message:
-----------
[clang] Cleanup IncludeLocMap (#106241)
CompilerInstance can re-use same SourceManager across multiple
frontendactions. During this process it calls
`SourceManager::clearIDTables` to reset any caches based on FileIDs.
It didn't reset IncludeLocMap, resulting in wrong include locations for
workflows that triggered multiple frontend-actions through same
CompilerInstance.
Commit: c4b5cb0f31227074d423b2db378dfbc486a5550e
https://github.com/llvm/llvm-project/commit/c4b5cb0f31227074d423b2db378dfbc486a5550e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
Log Message:
-----------
[AArch64] Add accelerate test coverage for acos/asin/atan and cosh/sinh/tanh intrinsics to support #106584
Commit: 833ce5d27b4e5452db73bf1b4eace7b1891f8650
https://github.com/llvm/llvm-project/commit/833ce5d27b4e5452db73bf1b4eace7b1891f8650
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
Log Message:
-----------
[mlir][ArmSME] Fix test after #98043 (NFC)
Commit: c8568f09577e9332d15edf98beb5376dc8d0672e
https://github.com/llvm/llvm-project/commit/c8568f09577e9332d15edf98beb5376dc8d0672e
Author: Longsheng Mou <moulongsheng at huawei.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
[mlir][tosa] Add missing check for mutiples of `tosa.tile` (#106337)
This patch adds check for mutiples of `tosa.tile`. The `multiples` in
`tosa.tile` indicates how many times the tensor should be replicated
along each dimension. Zero and negative values are invalid, except for
-1, which represents a dynamic value. Therefore, each element of
`mutiples` should be positive integer or -1. Fix #106167.
Commit: f0e34f381866b82a26241f7e9aa5964f0dd11ebd
https://github.com/llvm/llvm-project/commit/f0e34f381866b82a26241f7e9aa5964f0dd11ebd
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
Log Message:
-----------
[VPlan] Don't skip optimizable truncs in planContainsAdditionalSimps.
A optimizable cast can also be removed by VPlan simplifications. Remove
the restriction from planContainsAdditionalSimplifications, as this
causes it to miss relevant simplifications, triggering false positives
for the cost decision verification.
Also adds debug output for printing additional cost-precomputations.
Fixes https://github.com/llvm/llvm-project/issues/106641.
Commit: fab925651685505906416dca48469fd9f69ba39a
https://github.com/llvm/llvm-project/commit/fab925651685505906416dca48469fd9f69ba39a
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[LLVM][AArch64] Fix invalid use of AArch64ISD::UZP2 in performConcatVectorsCombine. (#104774)
UZP2 requires both operands to match the result type but the combine tries to replace a truncate by passing the pre-truncated operands directly to an UZP2 with the truncated result type. This patch nop-casts the operands to keep the DAG consistent. There should be no changes to the generated code, which is fine as it.
This patch also enables more target specific getNode() validation for fixed length vector types.
Commit: 68d8b3846ab1e6550910f2a9a685690eee558af2
https://github.com/llvm/llvm-project/commit/68d8b3846ab1e6550910f2a9a685690eee558af2
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[builtins] Fix missing main() function in float16/bfloat16 support checks (#104478)
The CMake docs state that `check_c_source_compiles()` checks whether the
supplied code "can be compiled as a C source file and linked as an
executable (so it must contain at least a `main()` function)."
https://cmake.org/cmake/help/v3.30/module/CheckCSourceCompiles.html
In practice, this command is a wrapper around `try_compile()`:
- https://gitlab.kitware.com/cmake/cmake/blob/2904ce00d2ed6ad5dac6d3459af62d8223e06ce0/Modules/CheckCSourceCompiles.cmake#L54
- https://gitlab.kitware.com/cmake/cmake/blob/2904ce00d2ed6ad5dac6d3459af62d8223e06ce0/Modules/Internal/CheckSourceCompiles.cmake#L101
When `CMAKE_SOURCE_DIR` is compiler-rt/lib/builtins/,
`CMAKE_TRY_COMPILE_TARGET_TYPE` is set to `STATIC_LIBRARY`, so the
checks for `float16` and `bfloat16` support work as intended in a
Clang + compiler-rt runtime build for example, as it runs CMake
recursively from that directory.
However, when using llvm/ or compiler-rt/ as CMake source directory, as
`CMAKE_TRY_COMPILE_TARGET_TYPE` defaults to `EXECUTABLE`, these checks
will indeed fail if the code doesn't have a `main()` function. This
results in LLVM using x86 SIMD registers when generating calls to
builtins that, with Arch Linux's compiler-rt package for example,
actually use a GPR for their argument or return value as they use
`uint16_t` instead of `_Float16`.
This had been caught in post-commit review:
https://reviews.llvm.org/D145237#4521152. Use of the internal
`CMAKE_C_COMPILER_WORKS` variable is not what hides the issue, however.
PR #69842 tried to fix this by unconditionally setting
`CMAKE_TRY_COMPILE_TARGET_TYPE` to `STATIC_LIBRARY`, but it apparently
caused other issues, so it was reverted. This PR just adds a `main()`
function in the checks, as per the CMake docs.
Commit: b065ec0af54988559334314ebbd51dd515d5bdd6
https://github.com/llvm/llvm-project/commit/b065ec0af54988559334314ebbd51dd515d5bdd6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/Transforms/Inline/X86/inline-target-cpu-i686.ll
M llvm/test/Transforms/Inline/X86/inline-target-cpu-x86_64.ll
Log Message:
-----------
[Inline][X86] Regenerate inline-target-cpu-* tests
Commit: fda7649b3c3797ddbb35a46746ae7876ab147612
https://github.com/llvm/llvm-project/commit/fda7649b3c3797ddbb35a46746ae7876ab147612
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
A llvm/test/Transforms/InstCombine/X86/x86-vperm.ll
Log Message:
-----------
[InstCombine][X86] Split off vperm shuffle tests from other avx512 tests
Commit: 6345604ae51df1251de5b5fd442910f4d8f5023e
https://github.com/llvm/llvm-project/commit/6345604ae51df1251de5b5fd442910f4d8f5023e
Author: Danial Klimkin <dklimkin at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize-with-call.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize.ll
A llvm/test/tools/llvm-split/AMDGPU/debug-name-hiding.ll
A llvm/test/tools/llvm-split/AMDGPU/debug-non-kernel-root.ll
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-alias-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-cost-ranking.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-external.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-overridable.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables-noexternal.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependency-indirect.ll
R llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
R llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
Log Message:
-----------
Revert: [AMDGPU] Graph-based Module Splitting Rewrite (llvm#104763) (#106707)
* Revert "Fix MSVC "not all control paths return a value" warning. NFC."
Dep to revert c9b6e01b2e4fc930dac91dd44c0592ad7e36d967
* Revert "[AMDGPU] Graph-based Module Splitting Rewrite (#104763)"
Breaks tests.
Commit: 2d5613afec0f4afeeb03cfd4edac556a65ad0eaf
https://github.com/llvm/llvm-project/commit/2d5613afec0f4afeeb03cfd4edac556a65ad0eaf
Author: Richard Howell <rmaz at users.noreply.github.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/tools/dsymutil/dsymutil.cpp
Log Message:
-----------
[dsymutil] return EXIT_FAILURE when Crashed (#106619)
Make dsymutil return a non-zero exit code when crashing during linking.
Commit: 87a988e881ac92e3d87aae01dc632f33c1fb36aa
https://github.com/llvm/llvm-project/commit/87a988e881ac92e3d87aae01dc632f33c1fb36aa
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
Log Message:
-----------
[SLP]Fix PR106655: Use FinalShuffle for alternate cast nodes.
Need to use FinalShuffle function for all vectorized results to
correctly produce vectorized value.
Fixes https://github.com/llvm/llvm-project/issues/106655
Commit: ce5620ba9a5bf48bce4e49933aec531c70c54aeb
https://github.com/llvm/llvm-project/commit/ce5620ba9a5bf48bce4e49933aec531c70c54aeb
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
Log Message:
-----------
[LLVM][VPlan] Pick more optimal initial value for VPBlend. (#104019)
By choosing an initial value whose mask is only used by the blend we can
remove the need for the mask entirely.
Commit: 64f19951718075fdd2d2b6d072e8e5ca15a1c6c4
https://github.com/llvm/llvm-project/commit/64f19951718075fdd2d2b6d072e8e5ca15a1c6c4
Author: Danial Klimkin <dklimkin at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
Log Message:
-----------
Fix stack overflow in allPathsGoThroughCold past 6b11573b8c5e (#106384)
Recursion here causes stack overflow on large inputs. Fixing by
unrolling via a stack.
Commit: ceb613a8bed218e2c98cd4fad3fd2a4a3217bd77
https://github.com/llvm/llvm-project/commit/ceb613a8bed218e2c98cd4fad3fd2a4a3217bd77
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
Log Message:
-----------
[RISCV] Add full test coverage for acos/asin/atan and cosh/sinh/tanh intrinsics to support #106584
Commit: 8586d0330e36b22496f9ba5ed116bc1aac5a1f28
https://github.com/llvm/llvm-project/commit/8586d0330e36b22496f9ba5ed116bc1aac5a1f28
Author: vdonaldson <37090318+vdonaldson at users.noreply.github.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/HLFIR/assumed_shape_with_value_keyword.f90
M flang/test/Lower/HLFIR/select-rank.f90
M flang/test/Lower/Intrinsics/system_clock.f90
M flang/test/Lower/OpenMP/master.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min.f90
M flang/test/Lower/OpenMP/wsloop-variable.f90
Log Message:
-----------
[flang] Don't generate empty else blocks (#106618)
Code lowering always generates fir.if else blocks for source level if
statements, whether needed or not. Change this to only generate else
blocks that are needed.
Commit: 2a8fda443e71707e73607feda2af0dbc871c972f
https://github.com/llvm/llvm-project/commit/2a8fda443e71707e73607feda2af0dbc871c972f
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-add-sub.ll
Log Message:
-----------
LICM: extend hoistAddSub to unsigned case (#106373)
Trivially extend dd0cf23 ([LICM] Reassociate & hoist sub expressions) to
handle unsigned predicates as well.
Alive2 proofs: https://alive2.llvm.org/ce/z/GdDBtT.
Commit: 86a60e7f1e8f361f84ccb6e656e848dd4fbaa713
https://github.com/llvm/llvm-project/commit/86a60e7f1e8f361f84ccb6e656e848dd4fbaa713
Author: Patryk Wychowaniec <pwychowaniec at pm.me>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
A llvm/test/CodeGen/AVR/jmp.ll
M llvm/test/MC/AVR/inst-brbc.s
M llvm/test/MC/AVR/inst-brbs.s
A llvm/test/MC/AVR/inst-brcc.s
A llvm/test/MC/AVR/inst-brcs.s
A llvm/test/MC/AVR/inst-breq.s
A llvm/test/MC/AVR/inst-brge.s
A llvm/test/MC/AVR/inst-brhc.s
A llvm/test/MC/AVR/inst-brhs.s
A llvm/test/MC/AVR/inst-brid.s
A llvm/test/MC/AVR/inst-brie.s
A llvm/test/MC/AVR/inst-brlo.s
A llvm/test/MC/AVR/inst-brlt.s
A llvm/test/MC/AVR/inst-brmi.s
A llvm/test/MC/AVR/inst-brne.s
A llvm/test/MC/AVR/inst-brpl.s
A llvm/test/MC/AVR/inst-brsh.s
A llvm/test/MC/AVR/inst-brtc.s
A llvm/test/MC/AVR/inst-brts.s
A llvm/test/MC/AVR/inst-brvc.s
A llvm/test/MC/AVR/inst-brvs.s
R llvm/test/MC/AVR/inst-family-cond-branch.s
M llvm/test/MC/AVR/inst-rcall.s
M llvm/test/MC/AVR/inst-rjmp.s
Log Message:
-----------
[AVR] Fix parsing & emitting relative jumps (#106722)
Ever since 6859685a87ad093d60c8bed60b116143c0a684c7 (or, precisely,
84428dafc0941e3a31303fa1b286835ab2b8e234) relative jumps emitted by the
AVR codegen are off by two bytes - this pull request fixes it.
## Abstract
As compared to absolute jumps, relative jumps - such as rjmp, rcall or
brsh - have an implied `pc+2` behavior; that is, `jmp 100` is `pc =
100`, but `rjmp 100` gets understood as `pc = pc + 100 + 2`.
This is not reflected in the AVR codegen:
https://github.com/llvm/llvm-project/blob/f95026dbf66e353128a3a3d7b55f3e52d5985535/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp#L89
... which always emits relative jumps that are two bytes too far - or
rather it _would_ emit such jumps if not for this check:
https://github.com/llvm/llvm-project/blob/f95026dbf66e353128a3a3d7b55f3e52d5985535/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp#L517
... which causes most of the relative jumps to be actually resolved
late, by the linker, which applies the offsetting logic on its own,
hiding the issue within LLVM.
[Some time
ago](https://github.com/llvm/llvm-project/commit/697a162fa63df328ec9ca334636c5e85390b2bf0)
we've had a similar "jumps are off" problem that got solved by touching
`shouldForceRelocation()`, but I think that has worked only by accident.
It's exploited the fact that absolute vs relative jumps in the parsed
assembly can be distinguished through a "side channel" check relying on
the existence of labels (i.e. absolute jumps happen to named labels, but
relative jumps are anonymous, so to say). This was an alright idea back
then, but it got broken by 6859685a87ad093d60c8bed60b116143c0a684c7.
I propose a different approach:
- when emitting relative jumps, offset them by `-2` (well, `-1`,
strictly speaking, because those instructions rely on right-shifted
offset),
- when parsing relative jumps, treat `.` as `+2` and read `rjmp .+1234`
as `rjmp (1234 + 2)`.
This approach seems to be sound and now we generate the same assembly as
avr-gcc, which can be confirmed with:
```cpp
// avr-gcc test.c -O3 && avr-objdump -d a.out
int main() {
asm(
" foo:\n\t"
" rjmp .+2\n\t"
" rjmp .-2\n\t"
" rjmp foo\n\t"
" rjmp .+8\n\t"
" rjmp end\n\t"
" rjmp .+0\n\t"
" end:\n\t"
" rjmp .-4\n\t"
" rjmp .-6\n\t"
" x:\n\t"
" rjmp x\n\t"
" .short 0xc00f\n\t"
);
}
```
avr-gcc is also how I got the opcodes for all new tests like `inst-brbc.s`, so we should be good.
Commit: a919588df4f108cef5829363a9ec6a1968dbb03a
https://github.com/llvm/llvm-project/commit/a919588df4f108cef5829363a9ec6a1968dbb03a
Author: Chris Apple <cja-private at pm.me>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan.h
M compiler-rt/lib/rtsan/tests/rtsan_test_functional.cpp
Log Message:
-----------
[compiler-rt][rtsan] NFC: Rename rtsan_on->rtsan_enable rtsan_off->rtsan_disable (#106727)
This better matches lsan_enable and disable, which we are trying to
emulate.
Commit: 7ffe67c17c524c2d3056c0721a33c7012dce3061
https://github.com/llvm/llvm-project/commit/7ffe67c17c524c2d3056c0721a33c7012dce3061
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
Log Message:
-----------
[RemoveDIs] Fix asan-identified leak in unittest (#106723)
Fixes issue found here
https://github.com/llvm/llvm-project/pull/106691#issuecomment-2320960847
The issue wasn't in the code change itself, just the unittest; the
trailing marker wasn't properly cleaned up.
Commit: 4a10b4c0bd241f3a2d7162fe29f520af7da6840c
https://github.com/llvm/llvm-project/commit/4a10b4c0bd241f3a2d7162fe29f520af7da6840c
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M flang/lib/Evaluate/intrinsics-library.cpp
Log Message:
-----------
[flang] fix flang builds with clang 20 after #100692 (#106718)
#100692 changes clang template deduction, and an error was now emitted
when building flang with top of the tree clang when mapping std::pow in
intrinsics-library.cpp for constant folding `error: address of
overloaded function 'pow' is ambiguous`
See https://lab.llvm.org/buildbot/#/builders/4/builds/1670
I I am not expert enough to understand if the new error is justified or
not here, but it is easy to help the compiler here with explicit
wrappers to fix the builds.
Commit: 96ad495289d241fc8f445ebdf4a9c1a6f6ff408e
https://github.com/llvm/llvm-project/commit/96ad495289d241fc8f445ebdf4a9c1a6f6ff408e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] vectorizeChainsInBlock - remove superfluous continue at the end of for loop. NFC.
Commit: b719c9255126aeba7a9455fd026471c45c988e2d
https://github.com/llvm/llvm-project/commit/b719c9255126aeba7a9455fd026471c45c988e2d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] findBestRootPair - fix incorrect argument name comment. NFC.
Commit: 362d37aeab7e8ba5dc4125480de3d45cc6bb23dc
https://github.com/llvm/llvm-project/commit/362d37aeab7e8ba5dc4125480de3d45cc6bb23dc
Author: MichelleCDjunaidi <michellechrisalyn at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/Contributing.rst
Log Message:
-----------
Update clang tidy Contributing guide (#106672)
Update the documentation to direct new users to the Github instead of
the discontinued Phabricator archive. Also details more ways and
information regarding clang-query usage. Partially resolves/disclaims
#106656 and #106663 as per discussion in
https://discourse.llvm.org/t/inconsistency-between-hasdescendant-in-clang-query-and-clang-libtooling-matchers/80799/.
Also updates the out-of-tree guide.
For context, I recently went through the Contributing guide while
writing https://github.com/llvm/llvm-project/pull/102299, and many of
these updates were from my experience trying to follow the guide. e.g. I
was trying to link the shared library of an out-of-tree check as SHARED
in CMake and encountered duplicate symbols like
_ZTIN5clang4tidy14ClangTidyCheckE. It wasn't until I saw
https://github.com/llvm/llvm-project/commit/84f137a590e7de25c4105303e5938c40566c2dfb
that I found out I had to use MODULE. I also encountered the clang-query
difference which was a surprise as the documentation said the two
matchers were "virtually identical". Also, the -header-filter thing
tripped me out until I found
https://github.com/llvm/llvm-project/issues/25590 and
https://github.com/llvm/llvm-project/pull/91400. Usually, when people
say restrict and filter, they mean filter out (since -header-filter
instead includes/filters in said headers).
Commit: 24977395592fb3a47d0356b6e9e6d25358a521c5
https://github.com/llvm/llvm-project/commit/24977395592fb3a47d0356b6e9e6d25358a521c5
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
A llvm/test/MC/AArch64/SVE/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE/directive-cpu-negative.s
M llvm/test/MC/AArch64/directive-arch-negative.s
M llvm/test/MC/AArch64/directive-arch_extension-negative.s
Log Message:
-----------
[AArch64][AsmParser] Directives should clear transitively implied features (#106625)
The commit ff3f3a54e2d1 made it possible to enable transitively implied
features when parsing assembler directives. For example enabling sve2
also enables sve.
This patch allows disabling features which depend on each other. For
example disabling sve also disables sve2.
Commit: c792de28dfaf3a13703e83e4eb09dd44574b3a3e
https://github.com/llvm/llvm-project/commit/c792de28dfaf3a13703e83e4eb09dd44574b3a3e
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M libcxx/test/std/language.support/cmp/cmp.alg/strong_order_long_double.verify.cpp
M libcxx/test/std/numerics/bit/bit.cast/bit_cast.pass.cpp
M libcxx/test/support/test_macros.h
Log Message:
-----------
[libcxx][test] Add macro for when long double is just double (#106708)
This removes the need for the long list of platforms in
strong_order_long_double_verify.
Commit: f4ea19b47e1e5af6682d94ad05ac2e7bca64cf73
https://github.com/llvm/llvm-project/commit/f4ea19b47e1e5af6682d94ad05ac2e7bca64cf73
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/include/syncstream
M libcxx/test/std/input.output/syncstream/syncbuf/syncstream.syncbuf.cons/cons.default.pass.cpp
Log Message:
-----------
[libc++][syncbuf] Implement LWG3253 (#99778)
Closes #100264
Commit: ab40ae8ff9f87b6e3d68cab2c47d692016ede958
https://github.com/llvm/llvm-project/commit/ab40ae8ff9f87b6e3d68cab2c47d692016ede958
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lldb/include/lldb/Core/SourceManager.h
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/unittests/Core/SourceManagerTest.cpp
Log Message:
-----------
[lldb] Store SupportFiles in SourceManager::File (NFC) (#106639)
To support detecting MD5 checksum mismatches, store a SupportFile rather
than a plain FileSpec in SourceManager::File.
Commit: b0eefb4c4e5136fd606cf4cff566df9dbc0fa051
https://github.com/llvm/llvm-project/commit/b0eefb4c4e5136fd606cf4cff566df9dbc0fa051
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lldb/include/lldb/Utility/SupportFile.h
Log Message:
-----------
[lldb] Update SupportFile documentation (NFC)
Commit: 0c4cf79defe30d43279bf4526cdf32b6c7f8a197
https://github.com/llvm/llvm-project/commit/0c4cf79defe30d43279bf4526cdf32b6c7f8a197
Author: Michał Górny <mgorny at gentoo.org>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/tools/scan-build-py/CMakeLists.txt
Log Message:
-----------
[clang] Install scan-build-py into plain "lib" directory (#106612)
Install scan-build-py modules into the plain `lib` directory,
without LLVM_LIBDIR_SUFFIX appended, to match the path expected
by `intercept-build` executable. This fixes the program being unable
to find its modules. Using unsuffixed path makes sense here, since
Python modules are not subject to multilib.
This change effectively reverts 1334e129a39cb427e7b855e9a711a3e7604e50e5.
The commit in question changed the path without a clear justification
("does not respect the given prefix") and the Python code was never
modified to actually work with the change.
Fixes #106608
Commit: 369d8148e09c2b91174ec01e845bc504cf622c45
https://github.com/llvm/llvm-project/commit/369d8148e09c2b91174ec01e845bc504cf622c45
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/test/Headers/__clang_hip_math.hip
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/Attributor/nofpclass.ll
Log Message:
-----------
[ValueTracking] use KnownBits to compute fpclass from bitcast (#97762)
When we encounter a bitcast from an integer type we can use the
information from `KnownBits` to glean some information about the
fpclass:
- If the sign bit is known, we can transfer this information over.
- If the float is IEEE format and enough of the bits are known, we may
be able to prove or rule out some fpclasses such as NaN, Zero, or Inf.
Commit: c4a53811c18b02490cbdc65be494e49018e23900
https://github.com/llvm/llvm-project/commit/c4a53811c18b02490cbdc65be494e49018e23900
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/docs/TestSuiteGuide.md
Log Message:
-----------
[test-suite] Document the LLVM test-suite benchmark apps (#105843)
There is no documentation or description of the different apps in the
LLVM benchmark test-suite and this is a first attempt to document this
for the MultiSource apps.
Commit: ece6566048086cf2870d2c2bff46384df1b9e531
https://github.com/llvm/llvm-project/commit/ece6566048086cf2870d2c2bff46384df1b9e531
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[MLIR][NVVM] Add support for fence.proxy.{acquire, release} Ops (#106689)
Commit: fef3426ad3d8d5bf01941438467df318d00c6279
https://github.com/llvm/llvm-project/commit/fef3426ad3d8d5bf01941438467df318d00c6279
Author: Chris Apple <cja-private at pm.me>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/Attributes.td
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/test/Bitcode/attributes.ll
M llvm/test/Bitcode/compatibility.ll
R llvm/test/Verifier/rtsan-attrs.ll
Log Message:
-----------
Revert "[LLVM][rtsan] Add LLVM nosanitize_realtime attribute (#105447)" (#106743)
This reverts commit 178fc4779ece31392a2cd01472b0279e50b3a199.
This attribute was not needed now that we are using the lsan style
ScopedDisabler for disabling this sanitizer
See #106736
#106125
For more discussion
Commit: 82a5ab756fdbce432794c00bdeeb95aa7e403d3f
https://github.com/llvm/llvm-project/commit/82a5ab756fdbce432794c00bdeeb95aa7e403d3f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/X86/x86-vperm.ll
Log Message:
-----------
[X86] x86-vperm.ll - strip superfluous semicolon check lines. NFC.
Commit: d01e0f7fb10ff1f9e2b797ce8437c701dfd58cbc
https://github.com/llvm/llvm-project/commit/d01e0f7fb10ff1f9e2b797ce8437c701dfd58cbc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/X86/x86-vperm.ll
M llvm/test/Transforms/InstCombine/X86/x86-vpermi2.ll
Log Message:
-----------
[InstCombine][X86] Add vpermv/vpermv3 test coverage for #106413
Commit: a3816b5a573dbf57ba3082a919ca2de6b47257e9
https://github.com/llvm/llvm-project/commit/a3816b5a573dbf57ba3082a919ca2de6b47257e9
Author: Patryk Wychowaniec <pwychowaniec at pm.me>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lld/test/ELF/avr-reloc.s
Log Message:
-----------
[AVR] Fix LLD test (#106739)
Since we don't generate relocations for those, it doesn't make sense to
assert them here; fallout of
https://github.com/llvm/llvm-project/pull/106722.
Commit: 924907bc6aa17bb15241143dc9858da971b25908
https://github.com/llvm/llvm-project/commit/924907bc6aa17bb15241143dc9858da971b25908
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Log Message:
-----------
[DAG] Prefer 0.0 over -0.0 as neutral value for FADD w/NoSignedZero (#106616)
When getting a neutral value, we can prefer using a positive zero over a
negative zero if nsz is set on the FADD (or reduction). A positive zero
should be cheaper to materialize on basically all targets.
Arguably, we should be doing this kind of canonicalization in
DAGCombine, but we don't do that for any of the other reduction
variants, so this seems like path of least resistance. This does mean
that we can only do this for "fast" reductions. Just nsz isn't enough,
as that goes through the SEQ_FADD path where the IR level start value
isn't folded away.
If folks think this is to RISCV specific, let me know. There's a trivial
RISCV specific implementation. I went with the generic one as I through
this might benefit other targets.
Commit: 49b04e60ed99307b0b4369b8956e6c15c7094d07
https://github.com/llvm/llvm-project/commit/49b04e60ed99307b0b4369b8956e6c15c7094d07
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/SandboxIR/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/SandboxIR/BUILD.gn
Log Message:
-----------
[gn build] Port 034f2b380bd2
Commit: 5224f65b44f9873c8298d51233005d4802ff0ba0
https://github.com/llvm/llvm-project/commit/5224f65b44f9873c8298d51233005d4802ff0ba0
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
Log Message:
-----------
[gn build] Port 115b87636b9f
Commit: b4d9c52db474041e417f547b699caeeecfa714cc
https://github.com/llvm/llvm-project/commit/b4d9c52db474041e417f547b699caeeecfa714cc
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Transforms/IPO/BUILD.gn
Log Message:
-----------
[gn build] Port bd6531b95086
Commit: 206b5aff44a95754f6dd7a5696efa024e983ac59
https://github.com/llvm/llvm-project/commit/206b5aff44a95754f6dd7a5696efa024e983ac59
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
AtomicExpand: Allow incrementally legalizing atomicrmw (#103371)
If a lowering changed control flow, resume the legalization
loop at the first newly inserted block.
This will allow incrementally legalizing atomicrmw and cmpxchg.
The AArch64 test might be a bugfix. Previously it would lower
the vector FP case as a cmpxchg loop, but cmpxchgs get lowered
but previously weren't. Maybe it shouldn't be reporting cmpxchg
for the expand type in the first place though.
Commit: 5703d8572f1bcca7bdcd01f1d83ad98ebb07ced0
https://github.com/llvm/llvm-project/commit/5703d8572f1bcca7bdcd01f1d83ad98ebb07ced0
Author: Brendan Dahl <brendan.dahl at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsWebAssembly.def
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/wasm_simd128.h
M cross-project-tests/intrinsic-header-tests/wasm_simd128.c
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/half-precision.ll
Log Message:
-----------
[WebAssembly] Add intrinsics to wasm_simd128.h for all FP16 instructions (#106465)
Getting this to work required a few additional changes:
- Add builtins for any instructions that can't be done with plain C
currently.
- Add support for the saturating version of fp_to_<s,i>_I16x8. Other
vector sizes supported this already.
- Support bitcast of f16x8 to v128. Needed to return a __f16x8 as
v128_t.
Commit: c55e24b8507d47a8cc04b5d9570e8e3d02be1ca3
https://github.com/llvm/llvm-project/commit/c55e24b8507d47a8cc04b5d9570e8e3d02be1ca3
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp
Log Message:
-----------
[llvm][LoongArch] Fix BSTRINS_D test failures on 32 bit hosts
eaf87d32754beb5bec10bab517bf56e25575b48e added new code that uses
64 bit types and ULL for constants, mostly, but a few UL snuck in.
UL is still 4 bytes on 32 bit, ULL is 8.
This fixes test failures on 32 bit Arm:
https://lab.llvm.org/buildbot/#/builders/39/builds/1338
Commit: d58d105cdaf366d7db3f60d356b21bc8e64666fb
https://github.com/llvm/llvm-project/commit/d58d105cdaf366d7db3f60d356b21bc8e64666fb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
Log Message:
-----------
[Analysis] isTriviallyVectorizable - add vectorization support for acos/asin/atan and cosh/sinh/tanh intrinsics (#106584)
Show fallback cases in amdlibm tests where it doesn't have that specific op
Commit: 68f0d20a9b507383a7577144bbd4811abe787e42
https://github.com/llvm/llvm-project/commit/68f0d20a9b507383a7577144bbd4811abe787e42
Author: JoelWee <32009741+JoelWee at users.noreply.github.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
Log Message:
-----------
Fix clang after ece6566048086cf2870d2c2bff46384df1b9e531
Commit: a2615ad45c73095dfda6ae546de107aacb10cbb7
https://github.com/llvm/llvm-project/commit/a2615ad45c73095dfda6ae546de107aacb10cbb7
Author: JoelWee <32009741+JoelWee at users.noreply.github.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M mlir/include/mlir/IR/Block.h
Log Message:
-----------
[mlir] Align mlir::Block (#106717)
This fixes an error from the LatticeAnchor PointerUnion with
ProgramPoint in b6603e1bf1
```
third_party/llvm/llvm-project/llvm/include/llvm/ADT/PointerIntPair.h:172:17: error: static assertion failed due to requirement '2U <= PointerUnionUIntTraits<mlir::GenericLatticeAnchor *, mlir::ProgramPoint, mlir::Value>::NumLowBitsAvailable': PointerIntPair with integer size too large for pointer
172 | static_assert(IntBits <= PtrTraits::NumLowBitsAvailable,
```
Commit: 97122550961944f2376f0e84a73cdd5b9e042bc4
https://github.com/llvm/llvm-project/commit/97122550961944f2376f0e84a73cdd5b9e042bc4
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/Contributing.rst
Log Message:
-----------
Fix a minor issue with the documentation; NFC
Commit: 1faa9c8a023fb42fda31fa1e6dd6d6d462fb7619
https://github.com/llvm/llvm-project/commit/1faa9c8a023fb42fda31fa1e6dd6d6d462fb7619
Author: Paul T Robinson <paul.robinson at sony.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/docs/Security.rst
Log Message:
-----------
[Security] Nominate Matthew Voss to replace Paul Robinson on the Secu… (#106112)
…rity Group
Matthew is a member of Sony's PS4/PS5 toolchain team, most visible for
his work on LTO, but he also has a long-standing interest in security.
He will replace Paul as one of Sony's participants in the Security Group
as Paul will be retiring from Sony at the end of September.
Commit: 348e74139ad7f06fdf8b332a81842de4bdf03b0c
https://github.com/llvm/llvm-project/commit/348e74139ad7f06fdf8b332a81842de4bdf03b0c
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M libcxx/include/__chrono/leap_second.h
M libcxx/include/__chrono/parser_std_format_spec.h
M libcxx/include/__chrono/statically_widen.h
M libcxx/include/__chrono/time_zone_link.h
M libcxx/include/__expected/expected.h
M libcxx/include/__format/buffer.h
M libcxx/include/__format/concepts.h
M libcxx/include/__format/container_adaptor.h
M libcxx/include/__format/enable_insertable.h
M libcxx/include/__format/escaped_output_table.h
M libcxx/include/__format/extended_grapheme_cluster_table.h
M libcxx/include/__format/format_arg.h
M libcxx/include/__format/format_arg_store.h
M libcxx/include/__format/format_args.h
M libcxx/include/__format/format_context.h
M libcxx/include/__format/format_error.h
M libcxx/include/__format/format_functions.h
M libcxx/include/__format/format_parse_context.h
M libcxx/include/__format/format_string.h
M libcxx/include/__format/format_to_n_result.h
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_char.h
M libcxx/include/__format/formatter_floating_point.h
M libcxx/include/__format/formatter_integer.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__format/formatter_output.h
M libcxx/include/__format/formatter_pointer.h
M libcxx/include/__format/formatter_string.h
M libcxx/include/__format/formatter_tuple.h
M libcxx/include/__format/indic_conjunct_break_table.h
M libcxx/include/__format/parser_std_format_spec.h
M libcxx/include/__format/range_default_formatter.h
M libcxx/include/__format/range_formatter.h
M libcxx/include/__format/unicode.h
M libcxx/include/__format/width_estimation_table.h
M libcxx/include/__fwd/format.h
M libcxx/include/__memory/allocator.h
M libcxx/include/__type_traits/is_member_pointer.h
M libcxx/include/__type_traits/is_void.h
M libcxx/include/array
M libcxx/include/forward_list
M libcxx/include/iosfwd
M libcxx/include/list
M libcxx/include/set
M libcxx/include/string
M libcxx/include/syncstream
M libcxx/include/tuple
M libcxx/include/vector
M libcxx/modules/std/format.inc
M libcxx/src/include/refstring.h
M libcxx/utils/generate_escaped_output_table.py
M libcxx/utils/generate_extended_grapheme_cluster_table.py
M libcxx/utils/generate_indic_conjunct_break_table.py
M libcxx/utils/generate_width_estimation_table.py
Log Message:
-----------
[libc++][NFC] Run clang-format on libcxx/include
This re-formats a few headers that had become out-of-sync with respect
to formatting since we ran clang-format on the whole codebase. There's
surprisingly few instances of it.
Commit: 68805de90280dc8d8df39ff3f6289033deb487cf
https://github.com/llvm/llvm-project/commit/68805de90280dc8d8df39ff3f6289033deb487cf
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
Log Message:
-----------
[IVDesc] Reuse getBinOpIdentity in getRecurrenceIdentity [nfc]
Avoid duplication so that we can easily tell these lists are in sync.
Commit: 941feb76c8186d2e237690511b48f57c6bda282b
https://github.com/llvm/llvm-project/commit/941feb76c8186d2e237690511b48f57c6bda282b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/Analysis/CostModel/X86/icmp-codesize.ll
M llvm/test/Analysis/CostModel/X86/icmp-latency.ll
M llvm/test/Analysis/CostModel/X86/icmp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/icmp.ll
Log Message:
-----------
[CostModel][X86] Fix SSE41/SSE42 cost checks on icmp tests
Noticed on #106747 - some SSE41 tests didn't match the SSE2 baseline so we were missing ALL the checks :(
Commit: 18e55052d6c7da765bbec311b1b6ac9590a2bfa3
https://github.com/llvm/llvm-project/commit/18e55052d6c7da765bbec311b1b6ac9590a2bfa3
Author: Connie Zhu <60797237+connieyzhu at users.noreply.github.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M mlir/test/lit.cfg.py
M polly/test/UnitIsl/lit.cfg
M polly/test/lit.cfg
Log Message:
-----------
[mlir][polly][llvm-lit] Fixed logic for turning on external shell in lit (#106458)
For both mlir and polly, the lit internal shell is the default shell for
running lit tests. However, if the user wanted to switch back to the
external shell by setting `LIT_USE_INTERNAL_SHELL=0`, the `not` used in
the body of the `if` conditional changes `use_lit_shell` to be True
instead of the intended False. Removing `not` allows for this lit config
to work as intended.
Fixes https://github.com/llvm/llvm-project/issues/106459.
Commit: f1cf09104eddbbe81c75e112a85c4f8dc14d5035
https://github.com/llvm/llvm-project/commit/f1cf09104eddbbe81c75e112a85c4f8dc14d5035
Author: Harini0924 <harinidonthula at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M compiler-rt/test/nsan/vec_sqrt.cpp
Log Message:
-----------
[compiler-rt][test] Added `env` command to fix NSAN_OPTIONS command not found error (#106676)
Resolved the issue where `'NSAN_OPTIONS=check_nan=true,halt_on_error=0'`
was not recognized as a command. Changed the test command to set the
environment variable correctly using `env`.
fixes: #106598
Commit: f81f283b365f99e1a71a836381c36874e965d80e
https://github.com/llvm/llvm-project/commit/f81f283b365f99e1a71a836381c36874e965d80e
Author: Florian Mayer <fmayer at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/test/CodeGen/address-safety-attr-flavors.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
R llvm/test/Instrumentation/HWAddressSanitizer/attrinfer.ll
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll
M llvm/test/Instrumentation/HWAddressSanitizer/hwasan-pass-second-run.ll
M llvm/test/Instrumentation/HWAddressSanitizer/mem-attr.ll
Log Message:
-----------
Revert "Reapply "[HWASan] remove incorrectly inferred attributes" (#106622)" (#106758)
Reverts llvm/llvm-project#106624
caused timeouts
Commit: 9764cf888502fe6dd15ab21de5c2f73cae47a2c0
https://github.com/llvm/llvm-project/commit/9764cf888502fe6dd15ab21de5c2f73cae47a2c0
Author: Harini0924 <harinidonthula at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
A llvm/utils/lit/tests/Inputs/shtest-glob/example_file1.input
A llvm/utils/lit/tests/Inputs/shtest-glob/example_file2.input
A llvm/utils/lit/tests/Inputs/shtest-glob/glob-echo.txt
A llvm/utils/lit/tests/Inputs/shtest-glob/glob-mkdir.txt
A llvm/utils/lit/tests/Inputs/shtest-glob/lit.cfg
A llvm/utils/lit/tests/shtest-glob.py
Log Message:
-----------
[llvm-lit] Add precommit test to verify current behavior of glob expansion in lit's internal shell (#106325)
This patch introduces a precommit test to verify the current behavior of
glob expansion in lit's internal shell. The motivation for this test
stems from an issue encountered during the BOLT test suite when running
with the lit internal shell using the command:
`LIT_USE_INTERNAL_SHELL=1 ninja check-bolt`
During execution, the following error was observed:
```
File "/usr/local/google/home/harinidonthula/llvm-project/llvm/utils/lit/lit/TestRunner.py", line 416, in executeBuiltinEcho
stdout.write(encode(maybeUnescape(args[-1])))
TypeError: string argument expected, got 'GlobItem'
```
The `executeBuiltinEcho` function in the lit testing framework expects a
string to be passed to `stdout.write`, but it received a `GlobItem`
object instead. This precommit test is designed to check the current
behavior where the glob pattern isn't correctly expanded, leading to
this `TypeError`.
While this patch doesn't fix the issue, it helps in understanding and
verifying the current behavior. The feedback I received from this
[PR](https://github.com/llvm/llvm-project/pull/105925) suggests using
`cmd.args = expand_glob_expressions(cmd.args, shenv.cwd)` to match the
behavior of `executeBuiltinMkdir` and `executeBuiltinRm`, but it is
recognized that the internal shell should ideally expand globs before
calling any built-in command.
**Request for Feedback:**
I'm looking for feedback on how to improve this precommit test,
specifically regarding the handling and expansion of glob patterns for
commands like mkdir and rm within the internal shell. Currently, the
args are expanded at the beginning of these functions, which should
ensure proper glob expansion. However, I'd appreciate guidance on
whether I should write additional tests to verify that mkdir and rm are
handling glob expansions correctly.
If such tests are recommended, I would also appreciate advice on the
best approach to implement them, considering the existing framework and
the way glob expansion is expected to function in the internal shell.
Should these tests confirm that the current implementation passes, or
are there specific edge cases I should be aware of?
**Next Steps:**
In my follow-up PR, I plan to address the UNRESOLVED error by expanding
the entire command, ensuring correct and consistent behavior across all
commands. The current test checks for an unresolved issue with the glob
expansion, specifically looking for a `TypeError` due to an unexpanded
`GlobItem`. This will be updated to reflect the correct behavior once
the issue is resolved.
This change is relevant for [[RFC] Enabling the Lit Internal Shell by
Default](https://discourse.llvm.org/t/rfc-enabling-the-lit-internal-shell-by-default/80179/3)
Commit: 9a0030e0f737fa06a4693a16d546b6336e138304
https://github.com/llvm/llvm-project/commit/9a0030e0f737fa06a4693a16d546b6336e138304
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Log Message:
-----------
[ARM] Don't use -1 as invalid register number in assembly parser. (#106666)
Use MCRegister instead.
Commit: 688843bda88e6dcc4f66a1283717258438dbbb96
https://github.com/llvm/llvm-project/commit/688843bda88e6dcc4f66a1283717258438dbbb96
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/float-imm.ll
M llvm/test/CodeGen/RISCV/half-imm.ll
Log Message:
-----------
[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)
Commit: c25293c6dd9a71b4655d1d6497ab8576c15e446e
https://github.com/llvm/llvm-project/commit/c25293c6dd9a71b4655d1d6497ab8576c15e446e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
Log Message:
-----------
[LegalizeVectorOps][RISCV] Don't promote VP_FABS/FNEG/FCOPYSIGN. (#106659)
Promoting canonicalizes NaNs which changes the semantics. Bitcast to
integer and use logic ops instead.
Commit: 5b3ba438dfa7815bb0f3be07a300866085a431b9
https://github.com/llvm/llvm-project/commit/5b3ba438dfa7815bb0f3be07a300866085a431b9
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUtils.cpp
Log Message:
-----------
Restructure createSimpleTargetReduction to match VP path [NFC]
Reduces code significantly, but more importantly makes it obvious that
this variant matches the VP variant just below.
Commit: 9aa25b8c15c99d8e717121837a2559801e311e2d
https://github.com/llvm/llvm-project/commit/9aa25b8c15c99d8e717121837a2559801e311e2d
Author: Walter Erquinigo <a20012251 at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFProperties.td
Log Message:
-----------
[LLDB][DWARF] Add an option to silence unsupported DW_FORM warnings (#106609)
My build of LLDB is all the time loading targets with a version of
libc++ that was built with gcc that uses the DW_FORM 0x1e that is not
implemented by LLVM, and I doubt it'll ever implement it. It's used for
some 128 bit encoding of numbers, which is just very weird. Because of
this, LLDB is showing some warnings all the time for my users, so I'm
adding a flag to control the enablement of this warning.
Commit: 26f6091dc9c24bdf22390f2b9f68aacc4669ef36
https://github.com/llvm/llvm-project/commit/26f6091dc9c24bdf22390f2b9f68aacc4669ef36
Author: Xiang Li <python3kgae at outlook.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/ObjectYAML/DXContainerYAML.h
M llvm/lib/BinaryFormat/DXContainer.cpp
M llvm/lib/ObjectYAML/DXContainerYAML.cpp
M llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-amplification.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-compute.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-domain.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-geometry.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-hull.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-mesh.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-pixel.yaml
M llvm/test/ObjectYAML/DXContainer/PSVv3-vertex.yaml
Log Message:
-----------
[DirectX] Replace ResourceFlag enum with struct fields (#106617)
Remove the enum about ResourceFlag.
Add struct ResourceFlags which save the resource flags with bool fields.
This will get better yaml dump.
For #103275
Commit: 4b553f4916180ac46c250b2625c5ee6f64b26533
https://github.com/llvm/llvm-project/commit/4b553f4916180ac46c250b2625c5ee6f64b26533
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Log Message:
-----------
Regen a bunch of vectorizer tests to avoid naming churn in upcoming review
Commit: 5af4ba2684b9b59de3bf8135f62e05ab68cfc489
https://github.com/llvm/llvm-project/commit/5af4ba2684b9b59de3bf8135f62e05ab68cfc489
Author: Harini0924 <harinidonthula at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
R llvm/utils/lit/tests/Inputs/shtest-glob/example_file1.input
R llvm/utils/lit/tests/Inputs/shtest-glob/example_file2.input
R llvm/utils/lit/tests/Inputs/shtest-glob/glob-echo.txt
R llvm/utils/lit/tests/Inputs/shtest-glob/glob-mkdir.txt
R llvm/utils/lit/tests/Inputs/shtest-glob/lit.cfg
R llvm/utils/lit/tests/shtest-glob.py
Log Message:
-----------
Revert "[llvm-lit] Add precommit test to verify current behavior of glob expansion in lit's internal shell" (#106763)
Reverts llvm/llvm-project#106325
Broke some Buildbots.
Commit: 5500e21942f7047344b6fee62d3e08c0ba2f9182
https://github.com/llvm/llvm-project/commit/5500e21942f7047344b6fee62d3e08c0ba2f9182
Author: Walter Erquinigo <a20012251 at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFProperties.td
Log Message:
-----------
Revert "[LLDB][DWARF] Add an option to silence unsupported DW_FORM warnings" (#106765)
Reverts llvm/llvm-project#106609
Commit: a4aa6bc8fc2130761b8db5db4748059127662785
https://github.com/llvm/llvm-project/commit/a4aa6bc8fc2130761b8db5db4748059127662785
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-bv-vectorized.ll
Log Message:
-----------
[SLP]Fix PR106667: carefully look for operand nodes.
If the operand node has the same scalars as one of the vectorized nodes,
the compiler could miss this and incorrectly request minbitwidth data
for the wrong node. It may lead to a compiler crash, because the
vectorized node might have different minbw result.
Fixes https://github.com/llvm/llvm-project/issues/106667
Commit: 6023d17e6b6624913b85fe9d2b5d79ae681e5764
https://github.com/llvm/llvm-project/commit/6023d17e6b6624913b85fe9d2b5d79ae681e5764
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Add a function description, NFC.
Commit: ef7b18a53c0d186dcda1e322be6035407fdedb55
https://github.com/llvm/llvm-project/commit/ef7b18a53c0d186dcda1e322be6035407fdedb55
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
Log Message:
-----------
[X86] Rename trailing whitespace. NFC.
Noticed in clang-formatting of #106750
Commit: d0d0e125a66b7c7921ad82c13c893bf592f071ba
https://github.com/llvm/llvm-project/commit/d0d0e125a66b7c7921ad82c13c893bf592f071ba
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Fix a presumed typo in isFPImmLegal limit. NFC (#106716)
The worst possible case for a double literal goes like:
```
mov ...
movk ..., lsl #16
movk ..., lsl #32
movk ..., lsl #48
fmov ...
```
The limit of 5 in the code gives the impression that `Insn` includes all
instructions including the `fmov`, but that's not true. It only counts
the integer moves. This led me astray on some other work in this area.
Commit: 0efa38699a4988793cdd51426fe27f00b5e5ce37
https://github.com/llvm/llvm-project/commit/0efa38699a4988793cdd51426fe27f00b5e5ce37
Author: Luke Lau <luke at igalia.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
A llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.ll
A llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir
Log Message:
-----------
[RISCV] Check VL dominates and potentially move in tryReduceVL (#106753)
Similar to what we do in foldVMV_V_V with the passthru, if we end up
changing the Src's VL in tryReduceVL we need to make sure it dominates.
Fixes #106735
Commit: 130eddf7a13f15c9c48b7fa7faf60e9bbee4f703
https://github.com/llvm/llvm-project/commit/130eddf7a13f15c9c48b7fa7faf60e9bbee4f703
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lldb/include/lldb/Core/SourceManager.h
M lldb/source/API/SBSourceManager.cpp
M lldb/source/Breakpoint/BreakpointResolverFileRegex.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/StackFrameList.cpp
Log Message:
-----------
[lldb] Deal with SupportFiles in SourceManager (NFC) (#106740)
To support detecting MD5 checksum mismatches, deal with SupportFiles
rather than a plain FileSpecs in the SourceManager.
Commit: 2c7e1b8893061fdf487f2d9945d2d1eecd59a604
https://github.com/llvm/llvm-project/commit/2c7e1b8893061fdf487f2d9945d2d1eecd59a604
Author: vporpo <vporpodas at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantFP (#106648)
This patch implements sandboxir::ConstantFP mirroring llvm::ConstantFP.
Commit: 07178981246c56e8beafe7fe49f0f442436f08c4
https://github.com/llvm/llvm-project/commit/07178981246c56e8beafe7fe49f0f442436f08c4
Author: rjmansfield <rjmansfield at users.noreply.github.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Log Message:
-----------
Fix cl::desc typos in aarch64-enable-dead-defs and arm-implicit-it. (#106712)
Commit: c49770c60f26e449379447109f7d915bd8de0384
https://github.com/llvm/llvm-project/commit/c49770c60f26e449379447109f7d915bd8de0384
Author: Nicolas van Kempen <nvankemp at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
M clang/docs/tools/generate_formatted_state.py
M clang/tools/scan-view/share/startfile.py
M clang/utils/creduce-clang-crash.py
M lldb/bindings/interface/SBErrorDocstrings.i
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/git/pre-push.py
M llvm/utils/gn/gn.py
Log Message:
-----------
[NFC] Prefer subprocess.DEVNULL over os.devnull (#106500)
There is no need to support Python 2.7 anymore, Python 3.3+ has
`subprocess.DEVNULL`. This is good practice and also prevents file
handles from
staying open unnecessarily.
Also remove a couple unused or unneeded `__future__` imports.
Commit: 079746d2c0804ddf616766eb525270d9c57ab542
https://github.com/llvm/llvm-project/commit/079746d2c0804ddf616766eb525270d9c57ab542
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
M llvm/test/Transforms/SLPVectorizer/X86/remark-masked-loads-consecutive-loads-same-ptr.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-possible-strided-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-masked-gather2.ll
Log Message:
-----------
[SLP]Better cost estimation for masked gather or "clustered" loads.
After landing support for actual vectorization of the "clustered" loads,
need better estimate the cost between the masked gather and clustered loads.
This includes estimation of the address calculation and better
estimation of the gathered loads. Also, this estimation now relies on
SLPCostThreshold option, allowing modify the behavior of the compiler.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/105858
Commit: 8a267b721180b172e329601039a7e170fa8aa5b5
https://github.com/llvm/llvm-project/commit/8a267b721180b172e329601039a7e170fa8aa5b5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Remove unused variable
Commit: 688a27496d73881a9e793a61f3f3a879f7efd581
https://github.com/llvm/llvm-project/commit/688a27496d73881a9e793a61f3f3a879f7efd581
Author: Artem Belevich <tra at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/lib/Analysis/PtrUseVisitor.cpp
Log Message:
-----------
[PtrUseVisitor] Allow using Argument as a starting point (#106308)
Argument is another possible starting point for the pointer traversal,
and PtrUseVisitor should be able to handle it.
Commit: 6ab07d71174982e5cb95420ee4df01347333c342
https://github.com/llvm/llvm-project/commit/6ab07d71174982e5cb95420ee4df01347333c342
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
Log Message:
-----------
[SLP]Initial support for non-power-of-2 (but still whole register) number of elements in operands.
Patch adds basic support for non-power-of-2 number of elements in
operands. The patch still requires that this number addresses whole
registers.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/106449
Commit: 897b00f3c563dd3f7b8f7263c41eaebb3520ec86
https://github.com/llvm/llvm-project/commit/897b00f3c563dd3f7b8f7263c41eaebb3520ec86
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUtils.cpp
Log Message:
-----------
Reuse getBinOpIdentity in createAnyOfTargetReduction [nfc]
Consolidating code so that we have one copy instead of multiple reasoning
about identity element. Note that we're (deliberately) not passing
the FMF flags to common utility to preserve behavior in this change.
Commit: 5eda4988117021b36ebe01b49082f63365846507
https://github.com/llvm/llvm-project/commit/5eda4988117021b36ebe01b49082f63365846507
Author: Matthias Springer <me at m-sp.org>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir
M mlir/test/Transforms/test-legalize-type-conversion.mlir
Log Message:
-----------
Revert "[mlir][Transforms] Dialect conversion: Make materializations optional" (#106778)
Reverts llvm/llvm-project#104668
This commit triggers an edge case that can cause circular
`unrealized_conversion_cast` ops.
https://github.com/llvm/llvm-project/pull/106760 may fix it, but it is
has other issues. Reverting this PR for now, until I find a solution for
that problem.
Commit: c315d787e3680e7f48d9de0502bb83300b190f84
https://github.com/llvm/llvm-project/commit/c315d787e3680e7f48d9de0502bb83300b190f84
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
Log Message:
-----------
[VP] Reduce duplicate code in vp.reduce expansions
Primary goal is having one way of doing this, to ensure that we don't
end up with accidental divergence.
Commit: a3f8790901cafaec8bcd863bd30b4f9ab7917bd8
https://github.com/llvm/llvm-project/commit/a3f8790901cafaec8bcd863bd30b4f9ab7917bd8
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M libcxx/include/cstddef
Log Message:
-----------
[libc++][NFC] Minor reformatting in <cstddef>
Commit: c53008de899653818b22c44eafd7e5eaab524e2b
https://github.com/llvm/llvm-project/commit/c53008de899653818b22c44eafd7e5eaab524e2b
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Manually jumpthread a bit of reduction code for readability [nfc]
Commit: 923a1c1fc348f7c30ff4726b54ed63ce403dc3ce
https://github.com/llvm/llvm-project/commit/923a1c1fc348f7c30ff4726b54ed63ce403dc3ce
Author: Brendan Dahl <brendan.dahl at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/MC/WebAssembly/simd-encodings.s
Log Message:
-----------
[WebAssembly] Update FP16 opcodes to match current spec. (#106759)
https://github.com/WebAssembly/half-precision/blob/f267a3d54432e5723dcc13ad4530c3581a0cc4b3/proposals/half-precision/Overview.md#binary-format
Commit: 5e7f0dcd69fd666bbb2a93d20e6a56a11261b519
https://github.com/llvm/llvm-project/commit/5e7f0dcd69fd666bbb2a93d20e6a56a11261b519
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M lldb/include/lldb/Core/SourceManager.h
M lldb/source/Core/SourceManager.cpp
Log Message:
-----------
[lldb] Include checksum in source cache dump (#106773)
This patch updates the source cache dump command to print both the
actual (on-disk) checksum and the expected (line table) checksum. To
achieve that we now read and store the on-disk checksum in the cached
object. The same information will be used in a future path to print a
warning when the checksums differ.
Commit: 432e9f44101e44bb996c350cf5693038916953f3
https://github.com/llvm/llvm-project/commit/432e9f44101e44bb996c350cf5693038916953f3
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp
Log Message:
-----------
[llvm][LoongArch] Avoid shift overflow (#106785)
Follow up fix to #106332
`LoongArchMatInt.cpp:96:33: runtime error: shift exponent 64 is too
large for 64-bit type`
https://lab.llvm.org/buildbot/#/builders/169/builds/2681
Commit: 982d2445f2a5bad96c501ff23923648ffa094ef2
https://github.com/llvm/llvm-project/commit/982d2445f2a5bad96c501ff23923648ffa094ef2
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
Revert "AtomicExpand: Allow incrementally legalizing atomicrmw" (#106792)
Reverts llvm/llvm-project#103371
There is `heap-use-after-free`, commented on
206b5aff44a95754f6dd7a5696efa024e983ac59
Maybe `if (Next == E || BB != Next->getParent()) {` is enough,
but not sure, what was the intent there,
Commit: 57fe53cae40351ebd079a9a0105addf4ad2e97dd
https://github.com/llvm/llvm-project/commit/57fe53cae40351ebd079a9a0105addf4ad2e97dd
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M libcxx/include/module.modulemap
M libcxx/test/libcxx/thread/thread.stoptoken/atomic_unique_lock.pass.cpp
M libcxx/test/libcxx/thread/thread.stoptoken/intrusive_list_view.pass.cpp
M libcxx/test/libcxx/thread/thread.stoptoken/intrusive_shared_ptr.pass.cpp
Log Message:
-----------
[libc++] First attempt to regroup a few modules in the modulemap (#98214)
We split up all the headers into top-level modules when we broke up
cycles with the C compatibility headers. However, this resulted in a
large number of small modules, which is awkward and clearly against the
philosophy of Clang modules. This was necessary to make things work.
This patch regroups a few headers from two leaf modules: stop_token and
pstl. It should be pretty uncontroversial that grouping these headers
into a single module doesn't introduce any cyclic dependency, yet it's a
first step towards reducing the number of top-level modules we have in
our modulemap.
Commit: 06c531e808ceeafdf996867a2e8e66960ae4774e
https://github.com/llvm/llvm-project/commit/06c531e808ceeafdf996867a2e8e66960ae4774e
Author: yonghong-song <yhs at fb.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFInstrInfo.td
A llvm/lib/Target/BPF/BPFMIChecking.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/CMakeLists.txt
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/atomics_2.ll
M llvm/test/CodeGen/BPF/objdump_atomics.ll
A llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
Log Message:
-----------
BPF: Generate locked insn for __sync_fetch_and_add() with cpu v1/v2 (#106494)
This patch contains two pars:
- first to revert the patch https://github.com/llvm/llvm-project/pull/101428.
- second to remove `atomic_fetch_and_*()` to `atomic_<op>()`
conversion (when return value is not used), but preserve
`__sync_fetch_and_add()` to locked insn with cpu v1/v2.
Commit: d66765ddf1ae9e16676a49cebd966258f8b5c6e0
https://github.com/llvm/llvm-project/commit/d66765ddf1ae9e16676a49cebd966258f8b5c6e0
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
Log Message:
-----------
[gn build] Port 06c531e808ce
Commit: 02654f7370638889b989b4d776d35c3d47c87cdd
https://github.com/llvm/llvm-project/commit/02654f7370638889b989b4d776d35c3d47c87cdd
Author: Chris B <chris.bieneman at me.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/docs/HLSL/ExpectedDifferences.rst
Log Message:
-----------
[HLSL][Doc] Document multi-argument resolution (#104474)
This updates the expected diffferences document to capture the
difference in multi-argument overload resolution between Clang and DXC.
Fixes #99530
Commit: 1293ab35e406e8b50030335ccf98580a7b719ff5
https://github.com/llvm/llvm-project/commit/1293ab35e406e8b50030335ccf98580a7b719ff5
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M .github/workflows/pr-code-format.yml
Log Message:
-----------
[Github] Cancel previous in-progress code formatting jobs (#106701)
Commit: 8f0c014b12663129d8bfe0cc89f06e7a1d8b48c2
https://github.com/llvm/llvm-project/commit/8f0c014b12663129d8bfe0cc89f06e7a1d8b48c2
Author: Yinying Li <yinyingli at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
A mlir/test/Dialect/SparseTensor/minipipeline_parallel.mlir
Log Message:
-----------
[mlir][sparse] add parallelization options to mini pipeline (#104233)
Commit: 10affaf894a72bee9b84ada77dc943b1bb03d02e
https://github.com/llvm/llvm-project/commit/10affaf894a72bee9b84ada77dc943b1bb03d02e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Log Message:
-----------
[AArch64][AsmParser] Stop parsing on error (#106804)
Fixes buffer overflow after #106625
Commit: 0dcd68c28a6170391b4643b737950689723d35fe
https://github.com/llvm/llvm-project/commit/0dcd68c28a6170391b4643b737950689723d35fe
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/CUDA/cuda-allocatable.cuf
Log Message:
-----------
[flang][cuda] Set allocator index for module allocatable variable (#106777)
Descriptor for module variable with cuda attribute must be set with the
correct allocator index. This patch updates the embox operation used in
the global to carry the allocator index.
Commit: d004ebc14a7ad9c0fa0509497ce75eaf9d073faa
https://github.com/llvm/llvm-project/commit/d004ebc14a7ad9c0fa0509497ce75eaf9d073faa
Author: Eugene Zhulenev <ezhulenev at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/ExecutionEngine/PerfJITEvents/PerfJITEventListener.cpp
Log Message:
-----------
Fix tsan race in PerfJITEventListener.cpp (#106800)
Static destructor can race with calls to notify and trigger tsan
warning.
```
WARNING: ThreadSanitizer: data race (pid=5787)
Write of size 1 at 0x55bec9df8de8 by thread T23:
#0 pthread_mutex_destroy [third_party/llvm/llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp:1344](third_party/llvm/llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp?l=1344&cl=669089572):3 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x1b12affb) (BuildId: ff25ace8b17d9863348bb1759c47246c)
#1 __libcpp_recursive_mutex_destroy [third_party/crosstool/v18/stable/src/libcxx/include/__thread/support/pthread.h:91](third_party/crosstool/v18/stable/src/libcxx/include/__thread/support/pthread.h?l=91&cl=669089572):10 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x4523d4e9) (BuildId: ff25ace8b17d9863348bb1759c47246c)
#2 std::__tsan::recursive_mutex::~recursive_mutex() [third_party/crosstool/v18/stable/src/libcxx/src/mutex.cpp:52](third_party/crosstool/v18/stable/src/libcxx/src/mutex.cpp?l=52&cl=669089572):11 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x4523d4e9)
#3 ~SmartMutex [third_party/llvm/llvm-project/llvm/include/llvm/Support/Mutex.h:28](third_party/llvm/llvm-project/llvm/include/llvm/Support/Mutex.h?l=28&cl=669089572):11 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x2bcaedfe) (BuildId: ff25ace8b17d9863348bb1759c47246c)
#4 (anonymous namespace)::PerfJITEventListener::~PerfJITEventListener() [third_party/llvm/llvm-project/llvm/lib/ExecutionEngine/PerfJITEvents/PerfJITEventListener.cpp:65](third_party/llvm/llvm-project/llvm/lib/ExecutionEngine/PerfJITEvents/PerfJITEventListener.cpp?l=65&cl=669089572):3 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x2bcaedfe)
#5 cxa_at_exit_callback_installed_at(void*) [third_party/llvm/llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp:437](third_party/llvm/llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp?l=437&cl=669089572):3 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x1b172cb9) (BuildId: ff25ace8b17d9863348bb1759c47246c)
#6 llvm::JITEventListener::createPerfJITEventListener() [third_party/llvm/llvm-project/llvm/lib/ExecutionEngine/PerfJITEvents/PerfJITEventListener.cpp:496](third_party/llvm/llvm-project/llvm/lib/ExecutionEngine/PerfJITEvents/PerfJITEventListener.cpp?l=496&cl=669089572):3 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x2bcad8f5) (BuildId: ff25ace8b17d9863348bb1759c47246c)
```
```
Previous atomic read of size 1 at 0x55bec9df8de8 by thread T192 (mutexes: write M0, write M1):
#0 pthread_mutex_unlock [third_party/llvm/llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp:1387](third_party/llvm/llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp?l=1387&cl=669089572):3 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x1b12b6bb) (BuildId: ff25ace8b17d9863348bb1759c47246c)
#1 __libcpp_recursive_mutex_unlock [third_party/crosstool/v18/stable/src/libcxx/include/__thread/support/pthread.h:87](third_party/crosstool/v18/stable/src/libcxx/include/__thread/support/pthread.h?l=87&cl=669089572):10 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x4523d589) (BuildId: ff25ace8b17d9863348bb1759c47246c)
#2 std::__tsan::recursive_mutex::unlock() [third_party/crosstool/v18/stable/src/libcxx/src/mutex.cpp:64](third_party/crosstool/v18/stable/src/libcxx/src/mutex.cpp?l=64&cl=669089572):11 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x4523d589)
#3 unlock [third_party/llvm/llvm-project/llvm/include/llvm/Support/Mutex.h:47](third_party/llvm/llvm-project/llvm/include/llvm/Support/Mutex.h?l=47&cl=669089572):16 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x2bcaf968) (BuildId: ff25ace8b17d9863348bb1759c47246c)
#4 ~lock_guard [third_party/crosstool/v18/stable/src/libcxx/include/__mutex/lock_guard.h:39](third_party/crosstool/v18/stable/src/libcxx/include/__mutex/lock_guard.h?l=39&cl=669089572):101 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x2bcaf968)
#5 (anonymous namespace)::PerfJITEventListener::notifyObjectLoaded(unsigned long, llvm::object::ObjectFile const&, llvm::RuntimeDyld::LoadedObjectInfo const&) [third_party/llvm/llvm-project/llvm/lib/ExecutionEngine/PerfJITEvents/PerfJITEventListener.cpp:290](https://cs.corp.google.com/piper///depot/google3/third_party/llvm/llvm-project/llvm/lib/ExecutionEngine/PerfJITEvents/PerfJITEventListener.cpp?l=290&cl=669089572):1 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x2bcaf968)
#6 llvm::orc::RTDyldObjectLinkingLayer::onObjEmit(llvm::orc::MaterializationResponsibility&, llvm::object::OwningBinary<llvm::object::ObjectFile>, std::__tsan::unique_ptr<llvm::RuntimeDyld::MemoryManager, std::__tsan::default_delete<llvm::RuntimeDyld::MemoryManager>>, std::__tsan::unique_ptr<llvm::RuntimeDyld::LoadedObjectInfo, std::__tsan::default_delete<llvm::RuntimeDyld::LoadedObjectInfo>>, std::__tsan::unique_ptr<llvm::DenseMap<llvm::orc::JITDylib*, llvm::DenseSet<llvm::orc::SymbolStringPtr, llvm::DenseMapInfo<llvm::orc::SymbolStringPtr, void>>, llvm::DenseMapInfo<llvm::orc::JITDylib*, void>, llvm::detail::DenseMapPair<llvm::orc::JITDylib*, llvm::DenseSet<llvm::orc::SymbolStringPtr, llvm::DenseMapInfo<llvm::orc::SymbolStringPtr, void>>>>, std::__tsan::default_delete<llvm::DenseMap<llvm::orc::JITDylib*, llvm::DenseSet<llvm::orc::SymbolStringPtr, llvm::DenseMapInfo<llvm::orc::SymbolStringPtr, void>>, llvm::DenseMapInfo<llvm::orc::JITDylib*, void>, llvm::detail::DenseMapPair<llvm::orc::JITDylib*, llvm::DenseSet<llvm::orc::SymbolStringPtr, llvm::DenseMapInfo<llvm::orc::SymbolStringPtr, void>>>>>>, llvm::Error) [third_party/llvm/llvm-project/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp:386](https://cs.corp.google.com/piper///depot/google3/third_party/llvm/llvm-project/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp?l=386&cl=669089572):10 (be1eb158bb70fc9cf7be2db70407e512890e5c6e20720cd88c69d7d9c26ea531_0200d5f71908+0x2bc404a8) (BuildId: ff25ace8b17d9863348bb1759c47246c)
```
Commit: 8b77aa990b5f2f75ea7128a87bdbb8b905162e90
https://github.com/llvm/llvm-project/commit/8b77aa990b5f2f75ea7128a87bdbb8b905162e90
Author: Petr Hosek <phosek at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M libc/spec/stdc.td
Log Message:
-----------
[libc] Use correct names for locale variants in spec.td (#106806)
This addresses issue introduced in #105718.
Commit: 332e6f86c50218ce60cafc9bf6d38d907da535ea
https://github.com/llvm/llvm-project/commit/332e6f86c50218ce60cafc9bf6d38d907da535ea
Author: Petr Hosek <phosek at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[Fuchsia] Support F extension for riscv32-unknown-elf (#106808)
This is used by some targets we support.
Commit: 5013cf682cf010c299e64acf68d35248b7c3e883
https://github.com/llvm/llvm-project/commit/5013cf682cf010c299e64acf68d35248b7c3e883
Author: Mike Hommey <mh at glandium.org>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/cmake/platforms/WinMsvc.cmake
Log Message:
-----------
[cmake] Add symbolic links for MSVC libraries (#106710)
When cross-compiling a Windows clang with `-DLLVM_BUILD_INSTRUMENTED`,
the profiling compiler-rt is linked to binaries, as one would expect,
but the profiling compiler-rt contains objects with `/DEFAULTLIB:LIBCMT`
and `/DEFAULTLIB:OLDNAMES` directives, which makes the build expect
`LIBCMT.lib` and `OLDNAMES.lib`, but they are nowhere to be found
because they are in lowercase. While the WinMsvc.cmake helper recreates
symbolic links to work around such case sensitivity issues for the
Windows SDK libs, it doesn't do so for the MSVC libs, which we add here.
Commit: 02eb03d5e0fef68a37751bd4865eff98c0e20a8c
https://github.com/llvm/llvm-project/commit/02eb03d5e0fef68a37751bd4865eff98c0e20a8c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV] Use DwarfRegAlias instead of DwarfRegNum for 32-bit and 64-bit FP registers.
There should only be one register that specifies a particular
DwarfRegNum.
Commit: 3745a2e8ab10029f8f401f5ff3c3c76c12e94822
https://github.com/llvm/llvm-project/commit/3745a2e8ab10029f8f401f5ff3c3c76c12e94822
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
M clang/lib/AST/ByteCode/Function.cpp
M clang/lib/AST/ByteCode/Function.h
Log Message:
-----------
[clang][bytecode][NFC] Cache the BuiltinID in Function (#106745)
FunctionDecl::getBuiltinID() is surprisingly slow and we tend to call it
quite a bit, especially when interpreting builtin functions. Caching the
BuiltinID here reduces the time I need to compile the
floating_comparison namespace from builtin-functions.cpp from 7.2s to
6.3s locally.
Commit: 18e35d8f665177a971d0f4ea93b2008dac5e7f33
https://github.com/llvm/llvm-project/commit/18e35d8f665177a971d0f4ea93b2008dac5e7f33
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp
Log Message:
-----------
[LoongArch] Don't left shift negative value (#106812)
Fixed another UB from #106332.
Detected here https://lab.llvm.org/buildbot/#/builders/169/builds/2662
Commit: 0ab3d6e14305ce8a97bfe3af7ddc52c416e698a6
https://github.com/llvm/llvm-project/commit/0ab3d6e14305ce8a97bfe3af7ddc52c416e698a6
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
A llvm/test/ThinLTO/X86/memprof-aliased-location1.ll
A llvm/test/ThinLTO/X86/memprof-aliased-location2.ll
A llvm/test/ThinLTO/X86/memprof-tailcall-aliased-location1.ll
A llvm/test/ThinLTO/X86/memprof-tailcall-aliased-location2.ll
A llvm/test/Transforms/MemProfContextDisambiguation/aliased-location1.ll
A llvm/test/Transforms/MemProfContextDisambiguation/aliased-location2.ll
A llvm/test/Transforms/MemProfContextDisambiguation/tailcall-aliased-location1.ll
A llvm/test/Transforms/MemProfContextDisambiguation/tailcall-aliased-location2.ll
Log Message:
-----------
Reapply "[MemProf] Reduce cloning overhead by sharing nodes when possible" (#102932) with fixes (#106623)
This reverts commit 11aa31f595325d6b2dede3364e4b86d78fffe635, restoring
commit 055e4319112282354327af9908091fdb25149e9b, with added fixes for
linker unsats.
In some cases multiple calls to different targets may end up with the
same debug information, and therefore callsite id. We will end up
sharing the node between these calls. We don't know which one matches
the callees until all nodes are matched with calls, at which point any
non-matching calls should be removed from the node. The fix extends the
handling in handleCallsitesWithMultipleTargets to do this, and adds
tests for various permutations of this situation.
Commit: d8bffa9018c88ef6ce441bb44d7b7d7a9091e583
https://github.com/llvm/llvm-project/commit/d8bffa9018c88ef6ce441bb44d7b7d7a9091e583
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
R llvm/test/MC/AArch64/SVE/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE/directive-cpu-negative.s
M llvm/test/MC/AArch64/directive-arch-negative.s
M llvm/test/MC/AArch64/directive-arch_extension-negative.s
Log Message:
-----------
Revert "[AArch64][AsmParser] Directives should clear transitively implied features (#106625)" (#106813)
Revert #106625 and fix attempt #106804"
There is another issue in
https://lab.llvm.org/buildbot/#/builders/169/builds/2690
directive-cpu-err.s
and the fix like #106804 fixed the overflow but fails CHECKs.
This reverts commit 10affaf894a72bee9b84ada77dc943b1bb03d02e.
This reverts commit 24977395592fb3a47d0356b6e9e6d25358a521c5.
Commit: e6e429179ecd425040af2bd475f090b503b047c9
https://github.com/llvm/llvm-project/commit/e6e429179ecd425040af2bd475f090b503b047c9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/half-arith.ll
Log Message:
-----------
[RISCV] Cleanup CHECK prefixes in half-arith.ll. NFC
Remove prefixes that donn't appear on RUN lines.
Rename prefixes for consistency.
Add RV32/RV64 prefixes where necessary to fix a conflict.
Commit: e0f2368cdeb7312973a92fb2d22199d1de540db8
https://github.com/llvm/llvm-project/commit/e0f2368cdeb7312973a92fb2d22199d1de540db8
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly annotate braces in ObjC square brackets (#106654)
See
https://github.com/llvm/llvm-project/pull/88238#issuecomment-2316954781.
Commit: d0dfcea608169e02293cb23905518481f3e8fedf
https://github.com/llvm/llvm-project/commit/d0dfcea608169e02293cb23905518481f3e8fedf
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
Log Message:
-----------
[RISCV][LoongArch] Don't store Dwarf register in MCRegister.
Commit: 4f9ea258c4f36e01e3a71a3603c588ee52b54a6f
https://github.com/llvm/llvm-project/commit/4f9ea258c4f36e01e3a71a3603c588ee52b54a6f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
Log Message:
-----------
[AsmPrinter] Don't store Dwarf register in Register.
Commit: ef50970204384643acca42ba4c7ca8f14865a0c2
https://github.com/llvm/llvm-project/commit/ef50970204384643acca42ba4c7ca8f14865a0c2
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M .github/workflows/release-binaries-save-stage/action.yml
Log Message:
-----------
workflows/release-binaries: Remove .git/config file from artifacts (#106310)
The .git/config file contains an auth token that can be leaked if the
.git directory is included in a workflow artifact.
Commit: 360e4abfc8c7298283041e8f5a07f1829a888d18
https://github.com/llvm/llvm-project/commit/360e4abfc8c7298283041e8f5a07f1829a888d18
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/MemberPointer.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/weak.cpp
Log Message:
-----------
[clang][bytecode] Diagnose comparisons with literals (#106734)
This requires adding a new opcode for PointerToBoolean casts, since we
otherwise emit too many diagnostics. But that fixes an older problem
when casting weak pointers to bool.
Commit: 8e972efb58ec35e35365d2f2ee6e8794c9336e59
https://github.com/llvm/llvm-project/commit/8e972efb58ec35e35365d2f2ee6e8794c9336e59
Author: Luke Lau <luke at igalia.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
A llvm/test/CodeGen/RISCV/rvv/vfwmaccbf16-sdnode.ll
Log Message:
-----------
[RISCV] Add scalable vector patterns for vfwmaccbf16.v{v,f} (#106771)
We can reuse the patterns for vfwmacc.v{v,f} as long as we swap out
fpext_oneuse for riscv_fpextend_bf16 in the scalar case.
Commit: 58e1c0e416f4a071482d1d9c2d620c7a0df4cf33
https://github.com/llvm/llvm-project/commit/58e1c0e416f4a071482d1d9c2d620c7a0df4cf33
Author: Luke Lau <luke at igalia.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
Log Message:
-----------
[RISCV] Discard the false operand in vmerge.vvm -> vmv.v.v peephole (#106688)
vmerge.vvm needs to have an all ones mask, so nothing is taken from the
false operand. So instead of checking that the passthru is the same as
false, just use the passthru directly for the tail elements.
This supersedes the convertVMergeToVMv part of #105788, as noted in
https://github.com/llvm/llvm-project/pull/105788/files#r1731683971
Commit: d884b77c662374bd779ccbf20ba3b31cb9949a18
https://github.com/llvm/llvm-project/commit/d884b77c662374bd779ccbf20ba3b31cb9949a18
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.h
M mlir/test/CAPI/llvm.c
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
Log Message:
-----------
[MLIR][LLVM] Make DISubprogramAttr cyclic (#106571)
This commit implements LLVM_DIRecursiveTypeAttrInterface for the
DISubprogramAttr to ensure cyclic subprograms can be imported properly.
In the process multiple shortcuts around the recently introduced
DIImportedEntityAttr can be removed.
Commit: 6f81c878ecd40acf1a0364e0ea5c9e6ea87407a2
https://github.com/llvm/llvm-project/commit/6f81c878ecd40acf1a0364e0ea5c9e6ea87407a2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/MemberPointer.h
M clang/lib/AST/ByteCode/Opcodes.td
Log Message:
-----------
[clang][bytecode][NFC] Implement MemberPointer::toDiagnosticString() (#106825)
Commit: 5257fa19c985f6fbb7ca422c60e9631c7d16527c
https://github.com/llvm/llvm-project/commit/5257fa19c985f6fbb7ca422c60e9631c7d16527c
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-08-30 (Fri, 30 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-declare.f90
Log Message:
-----------
[flang][openacc] Attach post allocate action on the correct operation (#106805)
In some cases (when using stat), the action was attached to the
invisible fir.result op. Apply same fix as in #89662.
Commit: fa93be4b1c249f5899ac8721724f7ee511c8b992
https://github.com/llvm/llvm-project/commit/fa93be4b1c249f5899ac8721724f7ee511c8b992
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.h
M mlir/test/CAPI/llvm.c
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
Log Message:
-----------
Revert "[MLIR][LLVM] Make DISubprogramAttr cyclic" (#106827)
Reverts llvm/llvm-project#106571
This commit breaks the following build bot:
https://lab.llvm.org/buildbot/#/builders/138/builds/2992
It looks like there is a missing dependency in this particular setup.
Commit: e4cf0a047d30fcd6cf606af0764883ca896a5153
https://github.com/llvm/llvm-project/commit/e4cf0a047d30fcd6cf606af0764883ca896a5153
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Check for custom typechecking in call cleanup (#106826)
The comment already explains that this is only true for _some_ builtin
functions. This also brings the time it takes me to run the
builtin-functions.cpp test locally from 50s down to 47s.
Commit: c6008cef7a710b3d97e6b9b6fcf8e9661333c5e6
https://github.com/llvm/llvm-project/commit/c6008cef7a710b3d97e6b9b6fcf8e9661333c5e6
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/include/llvm/IR/DataLayout.h
Log Message:
-----------
[DL] Invert `getTypeStoreSize` bytes/bits relationship to avoid ceil div (NFC)
Change how `getTypeStoreSize` and `getTypeStoreSizeInBits` interact
by first aligning the bit size to the nearest power of 2 boundary
and then applying plain division to derive the byte size. This
simplifies the calculation by avoiding possible overflow concerns
in the first place.
Commit: 3766ba44a8945681f4c52acb0331efcff66ef7b1
https://github.com/llvm/llvm-project/commit/3766ba44a8945681f4c52acb0331efcff66ef7b1
Author: Kasper Nielsen <kasper0406 at gmail.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M mlir/python/mlir/dialects/_ods_common.py
M mlir/test/mlir-tblgen/op-python-bindings.td
M mlir/test/python/dialects/ods_helpers.py
M mlir/test/python/dialects/python_test.py
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
Log Message:
-----------
[mlir][python] Fix how the mlir variadic Python accessor `_ods_equally_sized_accessor` is used (#101132) (#106003)
As reported in https://github.com/llvm/llvm-project/issues/101132, this
fixes two bugs:
1. When accessing variadic operands inside an operation, it must be
accessed as `self.operation.operands` instead of `operation.operands`
2. The implementation of the `equally_sized_accessor` function is doing
wrong arithmetics when calculating the resulting index and group sizes.
I have added a test for the `equally_sized_accessor` function, which did
not have a test previously.
Commit: 49aa255009f6096b055dab4b4dd31ffa5403b750
https://github.com/llvm/llvm-project/commit/49aa255009f6096b055dab4b4dd31ffa5403b750
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
Log Message:
-----------
[X86] Add missing pass initialization function for X86DynAllocaExpander. (#106820)
This allows it to show up in -print-before/after-all
Commit: 8c5d53f8deb26456432cc0459551cdd69754fea7
https://github.com/llvm/llvm-project/commit/8c5d53f8deb26456432cc0459551cdd69754fea7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Log Message:
-----------
[RISCV] Use MCRegister instead of unsigned in RISCVAsmParser.cpp. NFC
Rename RegNo to Reg.
Commit: 5b0bcec93dbc2e5bec049c452b157548334c5e28
https://github.com/llvm/llvm-project/commit/5b0bcec93dbc2e5bec049c452b157548334c5e28
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/CXX/temp/temp.res/temp.local/p8.cpp
Log Message:
-----------
[Clang][Parser] Fix name lookup of template parameters for out-of-line specializations (#101020)
Since the implementation of DR458 (d1446017), we have had an algorithm
that template parameters would take precedence over its parent scopes at
the name lookup. However, we failed to handle the following case where
the member function declaration is not yet deferral parsed (This is
where the patch of DR458 applies):
```cpp
namespace NS {
int CC;
template <typename> struct C;
}
template <typename CC>
struct NS::C {
void foo(CC);
};
```
When parsing the parameter of the function declaration `void foo(CC)`,
we used to perform a name lookup following such a Scope chain:
```
FunctionScope foo (failed)
RecordScope C (failed)
NamespaceScope NS (found `int CC`)
(If failed)
TemplateParameterScope of C
```
This doesn't seem right because according to `[temp.local]`, a template
parameter scope should be searched before its parent scope to which the
parameter appertains. This patch corrects the search scopes by setting a
lookup Entity for template parameter Scopes so that we can bail out in
CppNameLookup() when reaching the RecordScope. Afterward, the search
chain would be like:
```
FunctionScope foo (failed)
RecordScope C (failed)
TemplateParameterScope of C (found CC)
(If failed)
NamespaceScope NS
```
Fixes https://github.com/llvm/llvm-project/issues/64082
Commit: 0f7400c4c97f813808e72b87a9ef73ab16d6bb4a
https://github.com/llvm/llvm-project/commit/0f7400c4c97f813808e72b87a9ef73ab16d6bb4a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M libcxx/test/std/utilities/charconv/charconv.to.chars/integral.pass.cpp
Log Message:
-----------
[libc++] Add missing include to std/utilities/charconv/charconv.to.chars/integral.pass.cpp
Commit: 4d412bedcc97125896d58c27e63a977fdc856901
https://github.com/llvm/llvm-project/commit/4d412bedcc97125896d58c27e63a977fdc856901
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
Log Message:
-----------
[LoopVectorize][X86] amdlibm-calls.ll - add missing sinh and f64 test coverage to all functions
Shows failure to vectorise acos/asin/atan and cosh/sinh/tanh libcalls if they don't have a corresponding veclib mapping
Commit: d1f3fecf11a1013dcea12c93a3aaf9e4b6164f92
https://github.com/llvm/llvm-project/commit/d1f3fecf11a1013dcea12c93a3aaf9e4b6164f92
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/X86/x86-vperm.ll
M llvm/test/Transforms/InstCombine/X86/x86-vpermi2.ll
Log Message:
-----------
[InstCombine][X86] Only demand the active index bits for VPERMV/VPERMV3 mask values (#106750)
VPERMV/VPERMV3 only uses the lower bits of the vector element indices - so use SimplifyDemandedBits to ignore anything touching the remaining bits.
Fixes #106413
Commit: 239127d731e633f89b912b0775b638c0e8b4a9eb
https://github.com/llvm/llvm-project/commit/239127d731e633f89b912b0775b638c0e8b4a9eb
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vundefined.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
M clang/utils/TableGen/RISCVVEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/Type.h
M llvm/lib/IR/Type.cpp
Log Message:
-----------
[llvm][RISCV] Support RISCV vector tuple type in llvm IR (#97992)
Summary:
This patch proposes new llvm types for RISCV vector tuples represented
as `TargetExtType` which contains both `LMUL` and `NF`(num_fields)
information and keep it all the way down to `selectionDAG` to match the
corresponding `MVT`(support in the following patch).
Detail:
Currently we have built-in C types for RISCV vector tuple type, e.g.
`vint32m1x2_t`, however it's is represented as structure of scalable
vector types, i.e. `{<vscale x 2 x i32>, <vscale x 2 x i32>}`. It loses
the information for num_fields(NF) as struct is flattened during
`selectionDAG`, thus it makes it not possible to handle inline assembly
of vector tuple type, it also makes the calling convention of vector
tuple types handing not strait forward and hard to realize the
allocation code, i.e. `RVVArgDispatcher`.
The llvm IR for the example above is then represented as
`target("riscv.vector.tuple", <vscale x 8 x i8>, 2)` in which the first
type parameter is the equivalent size scalable vecotr of i8 element
type, the following integer parameter is the `NF` of the tuple.
The new RISCV specific vector insert/extract intrinsics are also added
as `llvm.riscv.vector.insert` and `llvm.riscv.vector.extract` to handle
tuple type subvector insertion/extraction since the generic ones only
operates on `VectorType` but not `TargetExtType`.
There are total of 32 llvm types added for each `VREGS * NF <= 8`, where
`VREGS` is the vector registers needed for each `LMUL` and `NF` is
num_fields.
The name of types are:
```
target("riscv.vector.tuple", <vscale x 1 x i8>, 2) // LMUL = mf8, NF = 2
target("riscv.vector.tuple", <vscale x 1 x i8>, 3) // LMUL = mf8, NF = 3
target("riscv.vector.tuple", <vscale x 1 x i8>, 4) // LMUL = mf8, NF = 4
target("riscv.vector.tuple", <vscale x 1 x i8>, 5) // LMUL = mf8, NF = 5
target("riscv.vector.tuple", <vscale x 1 x i8>, 6) // LMUL = mf8, NF = 6
target("riscv.vector.tuple", <vscale x 1 x i8>, 7) // LMUL = mf8, NF = 7
target("riscv.vector.tuple", <vscale x 1 x i8>, 8) // LMUL = mf8, NF = 8
target("riscv.vector.tuple", <vscale x 2 x i8>, 2) // LMUL = mf4, NF = 2
target("riscv.vector.tuple", <vscale x 2 x i8>, 3) // LMUL = mf4, NF = 3
target("riscv.vector.tuple", <vscale x 2 x i8>, 4) // LMUL = mf4, NF = 4
target("riscv.vector.tuple", <vscale x 2 x i8>, 5) // LMUL = mf4, NF = 5
target("riscv.vector.tuple", <vscale x 2 x i8>, 6) // LMUL = mf4, NF = 6
target("riscv.vector.tuple", <vscale x 2 x i8>, 7) // LMUL = mf4, NF = 7
target("riscv.vector.tuple", <vscale x 2 x i8>, 8) // LMUL = mf4, NF = 8
target("riscv.vector.tuple", <vscale x 4 x i8>, 2) // LMUL = mf2, NF = 2
target("riscv.vector.tuple", <vscale x 4 x i8>, 3) // LMUL = mf2, NF = 3
target("riscv.vector.tuple", <vscale x 4 x i8>, 4) // LMUL = mf2, NF = 4
target("riscv.vector.tuple", <vscale x 4 x i8>, 5) // LMUL = mf2, NF = 5
target("riscv.vector.tuple", <vscale x 4 x i8>, 6) // LMUL = mf2, NF = 6
target("riscv.vector.tuple", <vscale x 4 x i8>, 7) // LMUL = mf2, NF = 7
target("riscv.vector.tuple", <vscale x 4 x i8>, 8) // LMUL = mf2, NF = 8
target("riscv.vector.tuple", <vscale x 8 x i8>, 2) // LMUL = m1, NF = 2
target("riscv.vector.tuple", <vscale x 8 x i8>, 3) // LMUL = m1, NF = 3
target("riscv.vector.tuple", <vscale x 8 x i8>, 4) // LMUL = m1, NF = 4
target("riscv.vector.tuple", <vscale x 8 x i8>, 5) // LMUL = m1, NF = 5
target("riscv.vector.tuple", <vscale x 8 x i8>, 6) // LMUL = m1, NF = 6
target("riscv.vector.tuple", <vscale x 8 x i8>, 7) // LMUL = m1, NF = 7
target("riscv.vector.tuple", <vscale x 8 x i8>, 8) // LMUL = m1, NF = 8
target("riscv.vector.tuple", <vscale x 16 x i8>, 2) // LMUL = m2, NF = 2
target("riscv.vector.tuple", <vscale x 16 x i8>, 3) // LMUL = m2, NF = 3
target("riscv.vector.tuple", <vscale x 16 x i8>, 4) // LMUL = m2, NF = 4
target("riscv.vector.tuple", <vscale x 32 x i8>, 2) // LMUL = m4, NF = 2
```
RFC:
https://discourse.llvm.org/t/rfc-support-riscv-vector-tuple-type-in-llvm/80005
Commit: dc03ee3cbba65356de62f2f27fb1934b2731000d
https://github.com/llvm/llvm-project/commit/dc03ee3cbba65356de62f2f27fb1934b2731000d
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/lib/CodeGen/ValueTypes.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/VTEmitter.cpp
Log Message:
-----------
[llvm][RISCV] Add RISCV vector tuple type to value types(MVT) (#97993)
Summary:
This patch handles the types(MVT) in `selectionDAG` for RISCV vector
tuples.
As described in previous patch handling llvm types, the MVTs also have
32 variants:
```
riscv_nxv1i8x2, riscv_nxv1i8x3, riscv_nxv1i8x4, riscv_nxv1i8x5, riscv_nxv1i8x6, riscv_nxv1i8x7, riscv_nxv1i8x8,
riscv_nxv2i8x2, riscv_nxv2i8x3, riscv_nxv2i8x4, riscv_nxv2i8x5, riscv_nxv2i8x6, riscv_nxv2i8x7, riscv_nxv2i8x8,
riscv_nxv4i8x2, riscv_nxv4i8x3, riscv_nxv4i8x4, riscv_nxv4i8x5, riscv_nxv4i8x6, riscv_nxv4i8x7, riscv_nxv4i8x8,
riscv_nxv8i8x2, riscv_nxv8i8x3, riscv_nxv8i8x4, riscv_nxv8i8x5, riscv_nxv8i8x6, riscv_nxv8i8x7, riscv_nxv8i8x8,
riscv_nxv16i8x2, riscv_nxv16i8x3, riscv_nxv16i8x4,
riscv_nxv32i8x2.
```
Detail:
An intuitive way to model vector tuple type is using nested scalable
vector, e.g. `nElts=NF, EltTy=nxv2i32`. However it's not compatible to
what we've done to handle scalable vector in TargetLowering, so it would
need more effort to change the code to handle this concept.
Another approach is encoding the `MinNumElts` info in `sz` of `MVT`,
e.g.
`nElts=NF, sz=(NF*MinNumElts*8)`, this makes it much easier to handle
and
changes less code.
This patch adopts the latter approach.
Stacked on https://github.com/llvm/llvm-project/pull/97992
Commit: db67a66e8e02b565b135544e5c9b0bb0cf2f2437
https://github.com/llvm/llvm-project/commit/db67a66e8e02b565b135544e5c9b0bb0cf2f2437
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
Log Message:
-----------
Revert "[RISCV] RISCV vector calling convention (2/2)" (#97994)
This reverts commit 91dd844aa499d69c7ff75bf3156e2e3593a88057.
Stacked on https://github.com/llvm/llvm-project/pull/97993
Commit: 22f98740b6181223f1e20ccc62ee569fb640ea13
https://github.com/llvm/llvm-project/commit/22f98740b6181223f1e20ccc62ee569fb640ea13
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
A llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll
M llvm/test/CodeGen/RISCV/rvv/inline-asm.ll
M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
Log Message:
-----------
[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)
This patch handles target lowering and calling convention.
For target lowering, the vector tuple type represented as multiple
scalable vectors is now changed to a single `MVT`, each `MVT` has a
corresponding register class.
The load/store of vector tuples are handled as the same way but need
another vector insert/extract instructions to get sub-register group.
Inline assembly constraint for vector tuple type can directly be modeled
as "vr" which is identical to normal vector registers.
For calling convention, it no longer needs an alternative algorithm to
handle register allocation, this makes the code easier to maintain and
read.
Stacked on https://github.com/llvm/llvm-project/pull/97994
Commit: 9e86d4f2ed2c543f5023de9b3812702662e93283
https://github.com/llvm/llvm-project/commit/9e86d4f2ed2c543f5023de9b3812702662e93283
Author: Martin Storsjö <martin at martin.st>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
Log Message:
-----------
Revert "[SLP]Initial support for non-power-of-2 (but still whole register) number of elements in operands."
This reverts commit 6ab07d71174982e5cb95420ee4df01347333c342.
This commit caused failed asserts, see
https://github.com/llvm/llvm-project/pull/106449.
Commit: b0276ec6b74cd65b765234f42b8e0e32597d3642
https://github.com/llvm/llvm-project/commit/b0276ec6b74cd65b765234f42b8e0e32597d3642
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
Log Message:
-----------
[RISCV][NFC] Reimplementation of target attribute override mechanism (#106680)
This patch aims to replace the target attribute override mechanism based
on `__RISCV_TargetAttrNeedOverride` with the insertion of several
negative target features
When the target attribute uses the full architecture string
("arch=rv64gc") or specifies the CPU ("cpu=rocket-rv64") as the version,
it will override the module-level target feature. Currently, this
mechanism is implemented by inserting `__RISCV_TargetAttrNeedOverride`
as a dummy target feature immediately before the target attribute's
feature.
```
module target features + __RISCV_TargetAttrNeedOverride + target attribute's feature
```
The RISCVTargetInfo::initFeatureMap function will remove the "module
target features" and use only the "target attribute's features".
This patch changes the process as follows:
```
module target features + negative target feature for all supported extension + target attribute's feature
```
The `module target features` will be disable by `negative target feature
for all supported extension` in `TargetInfo::initFeatureMap`
Commit: 75545b344913ad94e75d7ac81b776574c750d1b1
https://github.com/llvm/llvm-project/commit/75545b344913ad94e75d7ac81b776574c750d1b1
Author: WÁNG Xuěruì <git at xen0n.name>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M offload/CMakeLists.txt
Log Message:
-----------
[Offload] Fix disabling of cuda target on unsupported platforms (#106835)
The target name and the message are wrong -- both should say "cuda" for
the filtering to work.
Fixes commit 300e5b911442 (#93186).
Commit: 9adf81182e68b60417eea21d39b91da231a15990
https://github.com/llvm/llvm-project/commit/9adf81182e68b60417eea21d39b91da231a15990
Author: WÁNG Xuěruì <git at xen0n.name>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M offload/DeviceRTL/CMakeLists.txt
M offload/test/CMakeLists.txt
Log Message:
-----------
[Offload] Fix stray libomptarget message helper calls (#106837)
In #92581 the `LibomptargetUitls.cmake` helpers have been removed, but
only uses of `libomptarget_say` were migrated. Migrate the remaining few
warning and error messages so the `check-offload` target would not fail
due to missing `libomptarget_warning_say`.
While at it, update the `check-offload` unavailability message to say
`check-offload` instead of `check-libomptarget`.
Fixes #92581
Commit: 109bff1f1656e87933f7650f9a77dedeb0c8688c
https://github.com/llvm/llvm-project/commit/109bff1f1656e87933f7650f9a77dedeb0c8688c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M libcxx/src/locale.cpp
Log Message:
-----------
[libcxx] Do not include `langinfo.h` when using the LLVM C library (#106634)
Summary:
The `langinfo.h` header is a POSIX extension, so ideally we would be
able to build the C++ library without it. Currently the LLVM C library
doesn't support / provide it. This allows us to build the C++ library
with locales enabled. We can either disable it here, or just provide
stubs that do nothing as in
https://github.com/llvm/llvm-project/pull/106620.
Commit: 38dbcbdcb433265fcee63236ddf3ee25c0760b27
https://github.com/llvm/llvm-project/commit/38dbcbdcb433265fcee63236ddf3ee25c0760b27
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M libcxx/include/__config
Log Message:
-----------
[libcxx] Use the default rune table when using the LLVM libc (#106632)
Summary:
We currently do not provide a more complicated rune table, so we want
the
default.
Commit: 140e80a220d751b289aca2cf993a96af9baa4063
https://github.com/llvm/llvm-project/commit/140e80a220d751b289aca2cf993a96af9baa4063
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/X86/icmp-codesize.ll
M llvm/test/Analysis/CostModel/X86/icmp-latency.ll
M llvm/test/Analysis/CostModel/X86/icmp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/icmp.ll
Log Message:
-----------
[TTI] Add cost model support for [u|s]cmp (#106824)
This patch adds cost model support for [u|s]cmp.
Commit: 1061c6da53a7a2c36b6ce8f7499b850212483562
https://github.com/llvm/llvm-project/commit/1061c6da53a7a2c36b6ce8f7499b850212483562
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Fix -Wunused-variable in RISCVISelLowering.cpp (NFC)
/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp:21558:14: error: unused variable 'ValLMUL' [-Werror,-Wunused-variable]
unsigned ValLMUL =
^
/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp:21561:14: error: unused variable 'PartLMUL' [-Werror,-Wunused-variable]
unsigned PartLMUL =
^
2 errors generated.
Commit: 4514c381f37204cbd26f3ea1d5d00a23b9cde309
https://github.com/llvm/llvm-project/commit/4514c381f37204cbd26f3ea1d5d00a23b9cde309
Author: Eisuke Kawashima <e.kawaschima+github at gmail.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M lld/test/MachO/tools/validate-unwind-info.py
M lld/utils/benchmark.py
Log Message:
-----------
[lld] Fix invalid Python escape sequences (#94033)
Commit: a3ea90ffbbe47d9a1b3eab03324f09d7b8e0dcb3
https://github.com/llvm/llvm-project/commit/a3ea90ffbbe47d9a1b3eab03324f09d7b8e0dcb3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
Log Message:
-----------
[SLP]Initial support for non-power-of-2 (but still whole register) number of elements in operands.
Patch adds basic support for non-power-of-2 number of elements in
operands. The patch still requires that this number addresses whole
registers.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/106449
Commit: e41579a31f77008eb76c418df5d192d0974421d2
https://github.com/llvm/llvm-project/commit/e41579a31f77008eb76c418df5d192d0974421d2
Author: Xiang Li <python3kgae at outlook.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/WaveSize.hlsl
A clang/test/SemaHLSL/WaveSize-invalid-param.hlsl
A clang/test/SemaHLSL/WaveSize-invalid-profiles.hlsl
A clang/test/SemaHLSL/WaveSize-sm6.6-6.5.hlsl
M llvm/include/llvm/Support/DXILABI.h
Log Message:
-----------
[HLSL] AST support for WaveSize attribute. (#101240)
First step for support WaveSize attribute in
https://microsoft.github.io/DirectX-Specs/d3d/HLSL_SM_6_6_WaveSize.html
and
https://microsoft.github.io/hlsl-specs/proposals/0013-wave-size-range.html
A new attribute HLSLWaveSizeAttr was supported in the AST.
Implement both the wave size and the wave size range, rather than
separately which might require more work.
For #70118
Commit: 89fb8490a99e612f7a574e8678b21a90f689f5b4
https://github.com/llvm/llvm-project/commit/89fb8490a99e612f7a574e8678b21a90f689f5b4
Author: Chris B <chris.bieneman at me.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/Attr.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprClassification.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCall.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaSwift.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/AST/HLSL/OutArgExpr.hlsl
A clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
A clang/test/SemaHLSL/Language/OutputParameters.hlsl
A clang/test/SemaHLSL/Language/TemplateOutArg.hlsl
M clang/test/SemaHLSL/parameter_modifiers.hlsl
M clang/test/SemaHLSL/parameter_modifiers_ast.hlsl
M clang/tools/libclang/CXCursor.cpp
Log Message:
-----------
[HLSL] Implement output parameter (#101083)
HLSL output parameters are denoted with the `inout` and `out` keywords
in the function declaration. When an argument to an output parameter is
constructed a temporary value is constructed for the argument.
For `inout` pamameters the argument is initialized via copy-initialization
from the argument lvalue expression to the parameter type. For `out`
parameters the argument is not initialized before the call.
In both cases on return of the function the temporary value is written
back to the argument lvalue expression through an implicit assignment
binary operator with casting as required.
This change introduces a new HLSLOutArgExpr ast node which represents
the output argument behavior. The OutArgExpr has three defined children:
- An OpaqueValueExpr of the argument lvalue expression.
- An OpaqueValueExpr of the copy-initialized parameter.
- A BinaryOpExpr assigning the first with the value of the second.
Fixes #87526
---------
Co-authored-by: Damyan Pepper <damyanp at microsoft.com>
Co-authored-by: John McCall <rjmccall at gmail.com>
Commit: 8638fe1444a532c660f1ef2b93816cf6af6b05e9
https://github.com/llvm/llvm-project/commit/8638fe1444a532c660f1ef2b93816cf6af6b05e9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/test/CodeGen/X86/win_coreclr_chkstk.ll
Log Message:
-----------
[X86] Fix livein handling in emitStackProbeInlineWindowsCoreCLR64. (#106828)
Stop adding liveins for virtual registers. In the livein interface, the
register goes through a MCPhysReg which is uint16_t. This causes the
virtual register bit to be dropped making it alias to some nonsense
physical register.
Recompute the liveins for the continue block to handle any live
registers that are needed by instructions that were spliced from the
original block. This fixing the machine verifier error so we can remove
that fixme now.
Commit: 6d9c6f0ca5957f112b790be479b52ed86950ef12
https://github.com/llvm/llvm-project/commit/6d9c6f0ca5957f112b790be479b52ed86950ef12
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Use MCRegister for return value from allocateRVVReg. NFC
Commit: 470f55facd083d20d429266de91e4cba15c80ff7
https://github.com/llvm/llvm-project/commit/470f55facd083d20d429266de91e4cba15c80ff7
Author: yonghong-song <yhs at fb.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
M llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp
M llvm/test/Transforms/ArgumentPromotion/2008-02-01-ReturnAttrs.ll
M llvm/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll
Log Message:
-----------
[Transforms][IPO] Add remarks for ArgumentPromotion and DeadArgumentE… (#105740)
…limination
ArgumentPromotion and DeadArgumentElimination passes may change function
signature. This makes bpf tracing difficult since users either not aware
of signature change or need to poke into IR or assembly to understand
the function signature change.
This patch enabled to emit some remarks so if recompiling with
-foptimization-record-file=<file>, users can check remarks to see what
kind of signature changes for a particular function. The following are
some examples for implemented remarks:
```
Pass: deadargelim
Name: ReturnValueRemoved
DebugLoc: { File: 'bpf-next/net/mptcp/protocol.c', Line: 572, Column: 0 }
Function: mptcp_check_data_fin
Args:
- String: 'removing return value '
- String: '0'
Pass: deadargelim
Name: ArgumentRemoved
DebugLoc: { File: 'bpf-next/kernel/bpf/syscall.c', Line: 1670, Column: 0 }
Function: map_delete_elem
Args:
- String: 'eliminating argument '
- ArgName: uattr.coerce0
- String: '('
- ArgIndex: '1'
- String: ')'
Pass: argpromotion
Name: ArgumentPromoted
DebugLoc: { File: 'bpf-next/net/mptcp/protocol.h', Line: 570, Column: 0 }
Function: mptcp_subflow_ctx
Args:
- String: 'promoting argument '
- ArgName: sk
- String: '('
- ArgIndex: '0'
- String: ')'
- String: ' to pass by value'
```
[1] https://github.com/llvm/llvm-project/issues/104678
Commit: 2afa9759280393fddb8f9a3be3bb28dbab73d56b
https://github.com/llvm/llvm-project/commit/2afa9759280393fddb8f9a3be3bb28dbab73d56b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Use MCRegister for vectors in CC_RISCV_FastCC. NFC
Commit: cfe331b853003cea868b84295552cecea63ab153
https://github.com/llvm/llvm-project/commit/cfe331b853003cea868b84295552cecea63ab153
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/SemaTemplate/GH18291.cpp
Log Message:
-----------
[clang] function template non-call partial ordering fixes (#106829)
This applies to function template non-call partial ordering the same
provisional wording change applied in the call context: Don't perform
the consistency check on return type and parameters which didn't have
any template parameters deduced from.
Fixes regression introduced in #100692, which was reported on the PR.
Commit: ec588175370a32dd40df86dc4672e65926817f25
https://github.com/llvm/llvm-project/commit/ec588175370a32dd40df86dc4672e65926817f25
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/docs/DeveloperPolicy.rst
Log Message:
-----------
docs: Clarify commit access requirements in the Developer Policy (#101414)
We have been discussing changes to our commit access polices recently
and based on some feedback from clattner here:
https://discourse.llvm.org/t/rfc-new-criteria-for-commit-access/76290/81
We need to update our Developer Policy so that it matches what we are
actually doing in this project. We currently grant commit access to
anyone with a valid justification, not just contributors who have
submitted high-quality patches in the past.
---------
Co-authored-by: Shilei Tian <i at tianshilei.me>
Commit: 37e109c6f86e7562a7f0b54a229f57e36b778f05
https://github.com/llvm/llvm-project/commit/37e109c6f86e7562a7f0b54a229f57e36b778f05
Author: Brad Smith <brad at comstyle.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M openmp/runtime/cmake/LibompDefinitions.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/z_Linux_util.cpp
Log Message:
-----------
[OpenMP] Support setting POSIX thread name on *BSD's and Solaris (#106489)
Commit: a3e293617354ee5be261345a5f1ffabe711632e0
https://github.com/llvm/llvm-project/commit/a3e293617354ee5be261345a5f1ffabe711632e0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Log Message:
-----------
[SelectionDAGISel] Use MCRegister and Register for LiveInMap. NFC
This matches the MachineBasicBlock liveins used to populate it.
Commit: 8aa8c0590c09a52737787ed7c35befa3fbede231
https://github.com/llvm/llvm-project/commit/8aa8c0590c09a52737787ed7c35befa3fbede231
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/include/llvm/Analysis/DXILMetadataAnalysis.h
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
A llvm/test/Analysis/DXILMetadataAnalysis/dxilVer-1.0.ll
A llvm/test/Analysis/DXILMetadataAnalysis/dxilVer-1.8.ll
A llvm/test/Analysis/DXILMetadataAnalysis/entry-properties.ll
A llvm/test/Analysis/DXILMetadataAnalysis/shaderModel-as.ll
A llvm/test/Analysis/DXILMetadataAnalysis/shaderModel-cs-val-ver-0.0.ll
A llvm/test/Analysis/DXILMetadataAnalysis/shaderModel-cs.ll
A llvm/test/Analysis/DXILMetadataAnalysis/shaderModel-gs.ll
A llvm/test/Analysis/DXILMetadataAnalysis/shaderModel-hs.ll
A llvm/test/Analysis/DXILMetadataAnalysis/shaderModel-ms.ll
A llvm/test/Analysis/DXILMetadataAnalysis/shaderModel-ps.ll
A llvm/test/Analysis/DXILMetadataAnalysis/shaderModel-vs.ll
M llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.0.ll
M llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.8.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-as.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-cs-val-ver-0.0.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-cs.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-gs.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-hs.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-lib.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-ms.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-ps.ll
M llvm/test/CodeGen/DirectX/Metadata/shaderModel-vs.ll
Log Message:
-----------
[DXIL][Analysis] Collect Function properties in Metadata Analysis (#105728)
Basic infrastructure to collect Function properties in Metadata Analysis
- Add a `SmallVector` of entry properties to the metadata information.
- Add a structure to represent function properties. Currently
`numthreads` and shader kind properties of shader entry functions are
represented.
Commit: 84580a02e0f0d3a43efc73dacd6bf5a18cf628cc
https://github.com/llvm/llvm-project/commit/84580a02e0f0d3a43efc73dacd6bf5a18cf628cc
Author: Timothy Hoffman <4001421+tim-hoffman at users.noreply.github.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/IRDL/IR/IRDLOps.td
M mlir/include/mlir/Dialect/IRDL/IR/IRDLTypes.td
Log Message:
-----------
[mlir][irdl] update documentation (#103394)
fixes #103300
Commit: 380fa875ab050293be6c8723d770700100b10b8f
https://github.com/llvm/llvm-project/commit/380fa875ab050293be6c8723d770700100b10b8f
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/branch.ll
M llvm/test/Transforms/InstCombine/compare-unescaped.ll
M llvm/test/Transforms/InstCombine/icmp-dom.ll
M llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/InstCombine/pr44245.ll
M llvm/test/Transforms/InstCombine/sink-into-ncd.ll
M llvm/test/Transforms/InstCombine/sink_to_unreachable.ll
M llvm/test/Transforms/InstCombine/zext-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll
A llvm/test/Transforms/PhaseOrdering/branch-dom-cond.ll
Log Message:
-----------
[InstCombine] Replace all dominated uses of condition with constants (#105510)
This patch replaces all dominated uses of condition with true/false to
improve context-sensitive optimizations. It eliminates a bunch of
branches in llvm-opt-benchmark.
As a side effect, it may introduce new phi nodes in some corner cases.
See the following case:
```
define i1 @test(i1 %cmp, i1 %cond) {
entry:
br i1 %cond, label %bb1, label %bb2
bb1:
br i1 %cmp, label %if.then, label %if.else
if.then:
br %bb2
if.else:
br %bb2
bb2:
%res = phi i1 [%cmp, %entry], [%cmp, %if.then], [%cmp, %if.else]
ret i1 %res
}
```
It will be simplified into:
```
define i1 @test(i1 %cmp, i1 %cond) {
entry:
br i1 %cond, label %bb1, label %bb2
bb1:
br i1 %cmp, label %if.then, label %if.else
if.then:
br %bb2
if.else:
br %bb2
bb2:
%res = phi i1 [%cmp, %entry], [true, %if.then], [false, %if.else]
ret i1 %res
}
```
I am planning to fix this in late pipeline/CGP since this problem exists
before the patch.
Commit: 4f4bd41f7098af51c3ba2e62cc635e3c45c294d4
https://github.com/llvm/llvm-project/commit/4f4bd41f7098af51c3ba2e62cc635e3c45c294d4
Author: c8ef <c8ef at outlook.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M clang/lib/Tooling/Refactoring/AtomicChange.cpp
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/scan-build-py/tests/functional/cases/test_create_cdb.py
M llvm/examples/ExceptionDemo/ExceptionDemo.cpp
Log Message:
-----------
[NFC] Fix typos (#106817)
Fixes #106761.
Commit: 6f682c26b04f0b349c4c473756cb8625b4f37c6d
https://github.com/llvm/llvm-project/commit/6f682c26b04f0b349c4c473756cb8625b4f37c6d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Merge similar code for legalizing i16<->f16 and i<->bf16 bitcasts. NFC
Commit: e4f3b56dae25e792b4aa5b009e371c8836fdc2fa
https://github.com/llvm/llvm-project/commit/e4f3b56dae25e792b4aa5b009e371c8836fdc2fa
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/references.cpp
Log Message:
-----------
[clang][bytecode] Fix diagnosing reads from temporaries (#106868)
Fix the DeclID not being set in global temporaries and use the same
strategy for deciding if a temporary is readable as the current
interpreter.
Commit: feb391c387c8751fd927d73e8f6d9de428f2fbe0
https://github.com/llvm/llvm-project/commit/feb391c387c8751fd927d73e8f6d9de428f2fbe0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.h
Log Message:
-----------
[X86] Remove X86RegisterInfo::getSEHRegNum. (#106866)
As far as I can tell, there's no way to call this. There are no calls in
the X86 directory. It has the same name as a function in MCRegisterInfo,
but that function takes a MCRegister and isn't virtual.
The function in MCRegisterInfo uses a DenseMap populated by
`X86_MC::initLLVMToSEHAndCVRegMapping`. The DenseMap is populated for
every physical register using the encoding value. I think that means the
function in MCRegisterInfo would return the same value as the function
in X86RegisterInfo.
Commit: 3bdec313160918c908ea469713764174d8a7d17c
https://github.com/llvm/llvm-project/commit/3bdec313160918c908ea469713764174d8a7d17c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-31 (Sat, 31 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
Log Message:
-----------
[RISCV] Custom legalize f16/bf16 FNEG/FABS with Zfhmin/Zbfmin. (#106886)
The LegalizeDAG expansion will go through memory since i16 isn't a legal
type. Avoid this by using FMV nodes.
Commit: 840d4d9446ef0a49b7600b42a188148a1826e17c
https://github.com/llvm/llvm-project/commit/840d4d9446ef0a49b7600b42a188148a1826e17c
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaTemplateDeduction.cpp
Log Message:
-----------
[clang] NFCI: don't check deduced constraints when partial ordering (#106882)
Commit: bec1d86516f59997794f7707a50da858792a8d8d
https://github.com/llvm/llvm-project/commit/bec1d86516f59997794f7707a50da858792a8d8d
Author: Matt Bolitho <matt.bolitho.software at gmail.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Support/BLAKE3/CMakeLists.txt
Log Message:
-----------
[CMake][Support] Use /nologo when compiling BLAKE3 assembly sources on Windows (#106794)
Suppresses the copyright banner for `ml64` compiling BLAKE3 assembly
sources with MSVC and Ninja on Windows:
```
[157/3758] Building ASM_MASM object lib\Support\BLAKE3\CMa...upportBlake3.dir\blake3_avx512_x86-64_windows_msvc.asm.obj
Microsoft (R) Macro Assembler (x64) Version 14.41.34120.0
Copyright (C) Microsoft Corporation. All rights reserved.
Assembling: C:\path\to\llvm-project\llvm\lib\Support\BLAKE3\blake3_avx512_x86-64_windows_msvc.asm
```
is now just:
```
Assembling: C:\path\to\llvm-project\llvm\lib\Support\BLAKE3\blake3_avx512_x86-64_windows_msvc.asm
```
We can suppress that last line with `/quiet` in more recent versions of
`ml64` (from MSVC 2022 17.6) but it is not supported by all potential
MASM compilers.
Commit: 4fef204ac42eb84e167d43ce076c9a167eae3be0
https://github.com/llvm/llvm-project/commit/4fef204ac42eb84e167d43ce076c9a167eae3be0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M clang/include/clang/AST/DeclID.h
Log Message:
-----------
[Clang][NFC] Don't manually enumerate the PredefinedDeclIDs (#106891)
This doesn't seem to have any use other than the possibility of merge
conflicts and accidentally forgetting to update `NUM_PREDEF_DECL_IDS`.
Commit: 24a043a6ff052ad7c123e67d020d688eea1a7efa
https://github.com/llvm/llvm-project/commit/24a043a6ff052ad7c123e67d020d688eea1a7efa
Author: tcwzxx <tcwzxx at gmail.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/crash_extractelement_poison.ll
Log Message:
-----------
[SLP] Fix crash of shuffle poison (#106857)
When the shuffle masks are `PoisonMaskElem`, there is not need to check
the cost of `SK_ExtractSubvector`. It is free. Otherwise, it will cause
the compiler to crash.
Assertion `(Idx + EltsPerVector) <= alignTo(NumElts, EltsPerVector) &&
"SK_ExtractSubvector index out of range"' failed.
Commit: 7c4cffd9d8be424e9e9542be9aec3b5a6f69073e
https://github.com/llvm/llvm-project/commit/7c4cffd9d8be424e9e9542be9aec3b5a6f69073e
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
Log Message:
-----------
[compiler-rt][fuzzer] SetThreadName build fix for Mingwin attempt (#106902)
Commit: 84ed3c29e8583bdd704d0e2f7e7c3d1162c6181c
https://github.com/llvm/llvm-project/commit/84ed3c29e8583bdd704d0e2f7e7c3d1162c6181c
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
R llvm/test/LTO/AMDGPU/gpu-rdc-amdgpu-attrs.ll
Log Message:
-----------
Revert "[AMDGPU][LTO] Assume closed world after linking (#105845)" (#106889)
We can't assume closed world even in full LTO post-link stage. It is
only true
if we are building a "GPU executable". However, AMDGPU does support
"dyamic
library". I'm not aware of any approach to tell if it is relocatable
link when
we create the pass. For now let's revert the patch as it is currently
breaking things.
We can re-enable it once we can handle it correctly.
Commit: 57ef16c699c274b7f3eee12e5c2896e193f513c4
https://github.com/llvm/llvm-project/commit/57ef16c699c274b7f3eee12e5c2896e193f513c4
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
Log Message:
-----------
Fix -Wswitch warning after 4fef204ac42eb84e167d43ce076c9a167eae3be0
Commit: 803ab280901588bdb92c52f8ea241caaa3926d8f
https://github.com/llvm/llvm-project/commit/803ab280901588bdb92c52f8ea241caaa3926d8f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/ARM/invalid-fp-operations.ll
Log Message:
-----------
[SLP][NFC]Add a test with unsafe fp vectorization.
Commit: 6e68fa921bb7bf5ceb0b5036bb7d71399d5c7906
https://github.com/llvm/llvm-project/commit/6e68fa921bb7bf5ceb0b5036bb7d71399d5c7906
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/ARM/invalid-fp-operations.ll
Log Message:
-----------
[SLP]Fix PR106909: add a check for unsafe FP operations.
NEON has non-IEEE compliant denormal flushing and the compiler should
check if it safe to vectorize instructions for NEON in non-fast math
mode.
Fixes https://github.com/llvm/llvm-project/issues/106909
Commit: 7b2fe84ff57b49f6275bc12d47f87a1887919d9e
https://github.com/llvm/llvm-project/commit/7b2fe84ff57b49f6275bc12d47f87a1887919d9e
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M clang/lib/Sema/CheckExprLifetime.cpp
Log Message:
-----------
Don't run the lifetime analysis for pointer assignment if the warning is
disabled.
Commit: affc0c64b65e73e5e0afe790762376f633ea970c
https://github.com/llvm/llvm-project/commit/affc0c64b65e73e5e0afe790762376f633ea970c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/test/CodeGen/X86/scmp.ll
M llvm/test/CodeGen/X86/ucmp.ll
Log Message:
-----------
[SDAG] Expand vector [u|s]cmp in VectorLegalizer (#106883)
Address comment
https://github.com/llvm/llvm-project/pull/106747#issuecomment-2322922855.
Commit: 9ccf82543d509bb5a0f5d0551fc4d6c1913b9a9b
https://github.com/llvm/llvm-project/commit/9ccf82543d509bb5a0f5d0551fc4d6c1913b9a9b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Implement VPWidenCallRecipe::computeCost (NFCI). (#106047)
Implement cost computation for VPWidenCallRecipe. In some cases, targets
use argument info to compute intrinsic costs. If all operands of the
call are VPValues with an underlying IR value, use the IR values as
arguments.
PR: https://github.com/llvm/llvm-project/pull/106731
Commit: 5c0d61e318a77434487fcec8361d8110fb06e59d
https://github.com/llvm/llvm-project/commit/5c0d61e318a77434487fcec8361d8110fb06e59d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M llvm/include/llvm/Transforms/IPO/FunctionImport.h
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/tools/llvm-link/llvm-link.cpp
Log Message:
-----------
[LTO] Reduce memory usage for import lists (#106772)
This patch reduces the memory usage for import lists by employing
memory-efficient data structures.
With this patch, an import list for a given destination module is
basically DenseSet<uint32_t> with each element indexing into the
deduplication table containing tuples of:
{SourceModule, GUID, Definition/Declaration}
In one of our large applications, the peak memory usage goes down by
9.2% from 6.120GB to 5.555GB during the LTO indexing step.
This patch addresses several sources of space inefficiency associated
with std::unordered_map:
- std::unordered_map<GUID, ImportKind> takes up 16 bytes because of
padding even though ImportKind only carries one bit of information.
- std::unordered_map uses pointers to elements, both in the hash table
proper and for collision chains.
- We allocate an instance of std::unordered_map for each
{Destination Module, Source Module} pair for which we have at least
one import. Most import lists have less than 10 imports, so the
metadata like the size of std::unordered_map and the pointer to the
hash table costs a lot relative to the actual contents.
Commit: 984fca5a8a7de726dc8d3ad232f45e1ae395829c
https://github.com/llvm/llvm-project/commit/984fca5a8a7de726dc8d3ad232f45e1ae395829c
Author: Da-Viper <57949090+Da-Viper at users.noreply.github.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts
M lldb/tools/lldb-dap/src-ts/extension.ts
Log Message:
-----------
[lldb-dap] show dialog when executable is not found (#104711)
Commit: 5aa83eb677d2f8cba0c2ad3dcc14f3f4e80a0bba
https://github.com/llvm/llvm-project/commit/5aa83eb677d2f8cba0c2ad3dcc14f3f4e80a0bba
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
Log Message:
-----------
[RISCV] Add test for llvm.round.i32.f16 RV64+Zfhmin/Zhinxmin. NFC
We have special handling for this in type legalization, but we
didn't have a test.
Commit: 654bb4e9f287f9ccb5142d1c62a9ab17c16e29d7
https://github.com/llvm/llvm-project/commit/654bb4e9f287f9ccb5142d1c62a9ab17c16e29d7
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
Log Message:
-----------
[LV] Don't consider branches leaving loop in collectValuesToIgnore.
Branches exiting the loop will remain regardless, so don't consider them
in collectValuesToIgnore.
This fixes another divergence between legacy and VPlan-based cost model.
Fixes https://github.com/llvm/llvm-project/issues/106780.
Commit: 747d89a89728c64a98ecb98f4f70f9a6d6750aac
https://github.com/llvm/llvm-project/commit/747d89a89728c64a98ecb98f4f70f9a6d6750aac
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/literal_pools_float_apple.ll
Log Message:
-----------
[AArch64] Add tests for fused FP literals. NFC (#106731)
This is for an upcoming change to the threshold on Apple targets for
using a constant pool for FP literals versus building them with integer
moves.
This file is based on literal_pools_float.ll. I tried to bolt on to the
existing test, but it got messy as that file is already testing a matrix
of combinations, so creating this new file instead.
Commit: 776aef1a5ac70eb6a58e6ab8e362716dbd0aa051
https://github.com/llvm/llvm-project/commit/776aef1a5ac70eb6a58e6ab8e362716dbd0aa051
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
Log Message:
-----------
[RISCV] Correct the rounding mode for llvm.lround.i64.f32 with RV64+Zfinx.
We should use RMM instead of DYN.
Commit: 357bd61744bb8cc2b9b07447294fa977e5758550
https://github.com/llvm/llvm-project/commit/357bd61744bb8cc2b9b07447294fa977e5758550
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
Log Message:
-----------
[RISCV] Custom promote f16 (l)lround/(l)lrint with Zfhmin/Zhinxmin instead of using isel patterns.
Commit: 5fe852e774b1b3526561e959effea3eec3ac4b36
https://github.com/llvm/llvm-project/commit/5fe852e774b1b3526561e959effea3eec3ac4b36
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M lld/ELF/Options.td
A lld/test/ELF/lto/time-trace.ll
Log Message:
-----------
[lld][ELF] Add `-plugin-opt=time-trace=` as an alias of `--time-trace=` (#106803)
Time trace profiler support was added into LLVMgold in
cd3255abede5e3687c1538f2d3857deb2c51af1b. This patch adds its
`-plugin-opt` counterpart, which is just an alias to `--time-trace=`,
into LLD for compatibility.
Commit: 837ee5b46a5f7f898f0de7e46a19600b896a0a1f
https://github.com/llvm/llvm-project/commit/837ee5b46a5f7f898f0de7e46a19600b896a0a1f
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/cast-half.ll
M llvm/test/Analysis/CostModel/RISCV/cast.ll
Log Message:
-----------
[RISCV][TTI] Scale the cost of FP-Int conversion with LMUL (#87506)
Widening/narrowing the source data type to match the destination data
type may require multiple steps.
To model the costs, the patch generated the interim type by following
the logic in RISCVTargetLowering::lowerVPFPIntConvOp.
Commit: 77523f9d5f7eac860a39728f031e3db9a53ee3b6
https://github.com/llvm/llvm-project/commit/77523f9d5f7eac860a39728f031e3db9a53ee3b6
Author: wanglei <wanglei at loongson.cn>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp
Log Message:
-----------
[LoongArch] Remove unnecessary increment operations
`HighMask` is the value that sets bits from `Msb+1` to 63 to 1, while
the other bits are set to 0.
Commit: 27e244f51435f8f0933969782a6faddfcbe809a6
https://github.com/llvm/llvm-project/commit/27e244f51435f8f0933969782a6faddfcbe809a6
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
A clang/test/Driver/aix-print-runtime-dir.c
Log Message:
-----------
[clang][AIX] Fix -print-runtime-dir on AIX (#104806)
Currently the option prints a path to a nonexistent directory with the
full triple, `lib/powerpc64-ibm-aix7.2.0.0`. It should only be
`lib/aix`.
Commit: c74cc73f2bfc1a82c2c68c2bfe9c4d70299aa060
https://github.com/llvm/llvm-project/commit/c74cc73f2bfc1a82c2c68c2bfe9c4d70299aa060
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-01 (Sun, 01 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVScheduleV.td
Log Message:
-----------
[RISCV] Move VLDSX0Pred from RISCVSchedSiFive7.td to RISCVScheduleV.td. NFC (#106671)
This predicate isn't bound to the scheduler model and and we may want to
reuse it in the future. We already moved it to reuse it in our
downstream.
Commit: 647f892a7281e99c4209cee07097f6a052ed474f
https://github.com/llvm/llvm-project/commit/647f892a7281e99c4209cee07097f6a052ed474f
Author: Brad Smith <brad at comstyle.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Support/Unix/Threading.inc
Log Message:
-----------
[llvm][Support] Simplify HAVE_PTHREAD_GETNAME/SETNAME_NP handling. NFCI (#106486)
Commit: 358165ded3c45115ce587d56ef792a9e7c0214ea
https://github.com/llvm/llvm-project/commit/358165ded3c45115ce587d56ef792a9e7c0214ea
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.normal/p1.cpp
M clang/test/SemaTemplate/concepts-friends.cpp
Log Message:
-----------
[Clang][Concepts] Correct the CurContext for friend declarations (#106890)
`FindInstantiatedDecl()` relies on the `CurContext` to find the
corresponding class template instantiation for a class template
declaration.
Previously, we pushed the semantic declaration context for constraint
comparison, which is incorrect for constraints on friend declarations.
In issue #78101, the semantic context of the friend is the TU, so we
missed the implicit template specialization `Template<void, 4>` when
looking for the instantiation of the primary template `Template` at the
time of checking the member instantiation; instead, we mistakenly picked
up the explicit specialization `Template<float, 5>`, hence the error.
As a bonus, this also fixes a crash when diagnosing constraints. The
DeclarationName is not necessarily an identifier, so it's incorrect to
call `getName()` on e.g. overloaded operators. Since the
DiagnosticBuilder has correctly handled Decl printing, we don't need to
find the printable name ourselves.
Fixes https://github.com/llvm/llvm-project/issues/78101
Commit: da13754103b8880811f4c164d858c6dd3c393927
https://github.com/llvm/llvm-project/commit/da13754103b8880811f4c164d858c6dd3c393927
Author: Akshat Oke <76596238+Akshat-Oke at users.noreply.github.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
A llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h
M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
Log Message:
-----------
AMDGPU/NewPM Port SILoadStoreOptimizer to NPM (#106362)
Commit: dd5d73007240712957f2b633f795d9965afaadd6
https://github.com/llvm/llvm-project/commit/dd5d73007240712957f2b633f795d9965afaadd6
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M lldb/include/lldb/Symbol/Type.h
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Symbol/Type.cpp
M lldb/test/API/lang/cpp/dynamic-value/Makefile
M lldb/test/API/lang/cpp/dynamic-value/TestDynamicValue.py
A lldb/test/API/lang/cpp/dynamic-value/a.h
A lldb/test/API/lang/cpp/dynamic-value/anonymous-b.cpp
M lldb/test/API/lang/cpp/dynamic-value/pass-to-base.cpp
M lldb/test/API/lang/cpp/namespace/TestNamespace.py
M lldb/unittests/Symbol/TestType.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDIETest.cpp
Log Message:
-----------
[lldb] Better matching of types in anonymous namespaces (#102111)
This patch extends TypeQuery matching to support anonymous namespaces. A
new flag is added to control the behavior. In the "strict" mode, the
query must match the type exactly -- all anonymous namespaces included.
The dynamic type resolver in the itanium abi (the motivating use case
for this) uses this flag, as it queries using the name from the
demangles, which includes anonymous namespaces.
This ensures we don't confuse a type with a same-named type in an
anonymous namespace. However, this does *not* ensure we don't confuse
two types in anonymous namespacs (in different CUs). To resolve this, we
would need to use a completely different lookup algorithm, which
probably also requires a DWARF extension.
In the "lax" mode (the default), the anonymous namespaces in the query
are optional, and this allows one search for the type using the usual
language rules (`::A` matches `::(anonymous namespace)::A`).
This patch also changes the type context computation algorithm in
DWARFDIE, so that it includes anonymous namespace information. This
causes a slight change in behavior: the algorithm previously stopped
computing the context after encountering an anonymous namespace, which
caused the outer namespaces to be ignored. This meant that a type like
`NS::(anonymous namespace)::A` would be (incorrectly) recognized as
`::A`). This can cause code depending on the old behavior to misbehave.
The fix is to specify all the enclosing namespaces in the query, or use
a non-exact match.
Commit: d2ce9dc85e5d94e19a69d4a72e7b9197447d480a
https://github.com/llvm/llvm-project/commit/d2ce9dc85e5d94e19a69d4a72e7b9197447d480a
Author: Brad Smith <brad at comstyle.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Support/Unix/Threading.inc
Log Message:
-----------
Add support for retrieving the thread ID on DragonFly BSD (#106938)
Commit: f044564db1cbc588d0cad4f953d38f6c787dadd4
https://github.com/llvm/llvm-project/commit/f044564db1cbc588d0cad4f953d38f6c787dadd4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
Log Message:
-----------
[InstCombine] Make backedge check in op of phi transform more precise (#106075)
The op of phi transform wants to prevent moving an operation across a
backedge, as this may lead to an infinite combine loop.
Currently, this is done using isPotentiallyReachable(). The problem with
that is that all blocks inside a loop are reachable from each other.
This means that the op of phi transform is effectively completely
disabled for code inside loops, even when it's not actually operating on
a loop phi (just a phi that happens to be in a loop).
Fix this by explicitly computing the backedges inside the function
instead. Do this via RPOT, which is a bit more efficient than using
FindFunctionBackedges() (which does it without any pre-computed
analyses).
For irreducible cycles, there may be multiple possible choices of
backedge, and this just picks one of them. This is still sufficient to
prevent combine loops.
This also removes the last use of LoopInfo in InstCombine -- I'll drop
the analysis in a followup.
Commit: c950ecb90e1945012ef3180aacbf92c994b7ee83
https://github.com/llvm/llvm-project/commit/c950ecb90e1945012ef3180aacbf92c994b7ee83
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
R llvm/test/CodeGen/RISCV/zfbfmin.ll
Log Message:
-----------
[RISCV] Remove zfbfmin.ll. NFC (#106937)
Most of it is redundant with bfloat-convert.ll. One testcase is found in
bfloat-imm.ll. The load and stores are more thoroughly tested in
bfloat-mem.ll.
Commit: cd3667d1dbc9c1db05aaf3cd5b39f33b143bd8b5
https://github.com/llvm/llvm-project/commit/cd3667d1dbc9c1db05aaf3cd5b39f33b143bd8b5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugVariables.cpp
M llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp
Log Message:
-----------
[CodeGen] Update a few places that were passing Register to raw_ostream::operator<< (#106877)
These would implicitly cast the register to `unsigned`. Switch most of
them to use printReg will give a more readable output. Change some
others to use Register::id() so we can eventually remove the implicit
cast to `unsigned`.
Commit: 08a72cbd6b12b5ccffb82c657bd668938f1b42e1
https://github.com/llvm/llvm-project/commit/08a72cbd6b12b5ccffb82c657bd668938f1b42e1
Author: Lang Hames <lhames at gmail.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticIDs.h
Log Message:
-----------
[clang] Bump up DIAG_SIZE_SEMA by 500 for downstream diagnostics.
Recently added HLSL diagnostics (89fb8490a99e) pushed the Swift compiler over
the existing limit.
rdar://135126738
Commit: fe1006b7f25258742173304c7c32e891be31d14e
https://github.com/llvm/llvm-project/commit/fe1006b7f25258742173304c7c32e891be31d14e
Author: pudge62 <70063806+pudge62 at users.noreply.github.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_mac.cpp
Log Message:
-----------
[TSan] fix crash when symbolize on darwin platforms (#99441)
The `dli_sname` filed in `Dl_info` may be `NULL`, which could cause a
crash
Commit: ed6d9f6d2af7da90ac089cf648a1f8b2e8e4eb10
https://github.com/llvm/llvm-project/commit/ed6d9f6d2af7da90ac089cf648a1f8b2e8e4eb10
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
A llvm/test/Transforms/CodeGenPrepare/revert-constant-ptr-propagation-on-calls.ll
Log Message:
-----------
[CGP] Introduce test for PR102926 (NFC)
Commit: e4e0dfb0c24c9bcd4bef835bd6a162967f097584
https://github.com/llvm/llvm-project/commit/e4e0dfb0c24c9bcd4bef835bd6a162967f097584
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/Transforms/CodeGenPrepare/revert-constant-ptr-propagation-on-calls.ll
Log Message:
-----------
[CGP] Undo constant propagation of pointers across calls
It may be profitable to revert SCCP propagation of C++ static values,
if such constants are pointers, in order to avoid redundant pointer
computation, since the method returning the constant is non-removable.
Commit: 30cc198c2d4ad784f18cc10a03d45a19145357af
https://github.com/llvm/llvm-project/commit/30cc198c2d4ad784f18cc10a03d45a19145357af
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/include/llvm/ADT/APInt.h
M llvm/lib/Support/APInt.cpp
M llvm/unittests/ADT/APIntTest.cpp
Log Message:
-----------
[APInt] Add default-disabled assertion to APInt constructor (#106524)
If the uint64_t constructor is used, assert that the value is actually a
signed or unsigned N-bit integer depending on whether the isSigned flag
is set. Provide an implicitTrunc flag to restore the previous behavior,
where the argument is silently truncated instead.
In this commit, implicitTrunc is enabled by default, which means that
the new assertions are disabled and no actual change in behavior occurs.
The plan is to flip the default once all places violating the assertion
have been fixed. See #80309 for the scope of the necessary changes.
The primary motivation for this change is to avoid incorrectly specified
isSigned flags. A recurring problem we have is that people write
something like `APInt(BW, -1)` and this works perfectly fine -- until
the code path is hit with `BW > 64`. Most of our i128 specific
miscompilations are caused by variants of this issue.
The cost of the change is that we have to specify the correct isSigned
flag (and make sure there are no excess bits) for uses where BW is
always <= 64 as well.
Commit: 9cf68679c4f45e79d67c94ef1f968c7c1213b610
https://github.com/llvm/llvm-project/commit/9cf68679c4f45e79d67c94ef1f968c7c1213b610
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
A llvm/test/CodeGen/ARM/atomic-64bit-fast-regalloc.ll
M llvm/test/CodeGen/ARM/atomic-load-store.ll
M llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
M llvm/test/CodeGen/ARM/cmpxchg-O0.ll
M llvm/test/CodeGen/ARM/cmpxchg.mir
M llvm/test/CodeGen/Thumb2/cmpxchg.mir
Log Message:
-----------
[ARM] Fix failure to register-allocate CMP_SWAP_64 pseudo-inst (#106721)
This test case was failing to compile with a "ran out of registers
during register allocation" error at -O0. This was because CMP_SWAP_64
has 3 operands which must be an even-odd register pair, and two other
GPR operands. All of the def operands are also early-clobber, so
registers can't be shared between uses and defs. Because the function
has an over-aligned alloca it needs frame and base pointers, so r6 and
r11 are both reserved. That leaves r0/r1, r2/r3, r4/r5 and r8/r9 as the
only valid register pairs, and if the two individual GPR operands happen
to get allocated to registers in different pairs then only 2 pairs will
be available for the three GPRPair operands.
To fix this, I've merged the two GPR operands into a single GPRPair
operand. This means that the instruction now has 4 GPRPair operands,
which can always be allocated without relying on luck. This does
constrain register allocation a bit more, but this pseudo instruction is
only used at -O0, so I don't think that's a problem.
Commit: d79c4c111952990062173f30bb83084cb2993f39
https://github.com/llvm/llvm-project/commit/d79c4c111952990062173f30bb83084cb2993f39
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/test/Transforms/CodeGenPrepare/revert-constant-ptr-propagation-on-calls.ll
Log Message:
-----------
[CGP] Regenerate `revert-constant-ptr-propagation-on-calls.ll` test (NFC)
Multiple buildbots were previously failing.
Commit: 5bd3ee0ac02880df0c4d7e89026ee8b9d8f1039e
https://github.com/llvm/llvm-project/commit/5bd3ee0ac02880df0c4d7e89026ee8b9d8f1039e
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M libcxx/test/std/language.support/cmp/cmp.alg/strong_order.pass.cpp
Log Message:
-----------
[libcxx][test] Use long double test macro in strong_order.pass.cpp (#106742)
Commit: 34b10e165d809bb133d37dfe934859800f21a100
https://github.com/llvm/llvm-project/commit/34b10e165d809bb133d37dfe934859800f21a100
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/include/llvm/Transforms/InstCombine/InstCombine.h
M llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Other/new-pm-print-pipeline.ll
M llvm/test/Transforms/InstCombine/gep-combine-loop-invariant.ll
Log Message:
-----------
[InstCombine] Remove optional LoopInfo dependency
https://github.com/llvm/llvm-project/pull/106075 has removed the
last dependency on LoopInfo in InstCombine, so don't fetch the
analysis anymore and remove the use-loop-info pass option.
Commit: 0fa78b6c7bd43c2498700a98c47a02cf4fd06388
https://github.com/llvm/llvm-project/commit/0fa78b6c7bd43c2498700a98c47a02cf4fd06388
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly annotate braces in macro definition (#106662)
Fixes #106418.
Commit: a156b5a47df58a1ac75cf67e26f557b1a4d26dc9
https://github.com/llvm/llvm-project/commit/a156b5a47df58a1ac75cf67e26f557b1a4d26dc9
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
A llvm/test/Transforms/SLPVectorizer/X86/arith-scmp.ll
A llvm/test/Transforms/SLPVectorizer/X86/arith-ucmp.ll
Log Message:
-----------
[SLP] Add vectorization support for [u|s]cmp (#106747)
This patch adds vectorization support for [u|s]cmp intrinsic calls.
Commit: a0a253181e3eb2e7173a37b043b82325c7cddd67
https://github.com/llvm/llvm-project/commit/a0a253181e3eb2e7173a37b043b82325c7cddd67
Author: Alastair Houghton <ahoughton at apple.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.h
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
Log Message:
-----------
[RuntimeDyld][Windows] Allocate space for dllimport things. (#102586)
We weren't taking account of the space we require in the stubs for
things that are dllimported, and as a result we could hit the assertion
failure for running out of stub space. Fix that.
rdar://133473673
---------
Co-authored-by: Saleem Abdulrasool <compnerd at compnerd.org>
Co-authored-by: Lang Hames <lhames at gmail.com>
Co-authored-by: Ben Barham <b.n.barham at gmail.com>
Commit: cde3838c430502620cb4c1663e843e465c6e67b5
https://github.com/llvm/llvm-project/commit/cde3838c430502620cb4c1663e843e465c6e67b5
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
Log Message:
-----------
[flang][runtime] long double isn't always f80 (#106746)
f80 is only a thing on x86, and even then the size of long double can be
changed with compiler flags. Instead set the size according to the host
system (this is what is already done for integer types).
Commit: eaea4d15acd4cab92e6287d692d2652066c3368a
https://github.com/llvm/llvm-project/commit/eaea4d15acd4cab92e6287d692d2652066c3368a
Author: c8ef <c8ef at outlook.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/builtins.cpp
Log Message:
-----------
[clang] The ms-extension __noop should return zero in a constexpr context. (#106849)
Fixes #106713.
Commit: 87d904871fe96a01dfa1f254ca2a7639de67960c
https://github.com/llvm/llvm-project/commit/87d904871fe96a01dfa1f254ca2a7639de67960c
Author: Alastair Houghton <ahoughton at apple.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.h
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
Log Message:
-----------
Revert "[RuntimeDyld][Windows] Allocate space for dllimport things." (#106954)
Looks like I missed an `override` (maybe that warning was enabled recently?). Will revert and fix.
Reverts llvm/llvm-project#102586
Commit: 24fe1d4fd61983277c8061ce591970bc775a0fb5
https://github.com/llvm/llvm-project/commit/24fe1d4fd61983277c8061ce591970bc775a0fb5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/test/CodeGen/attr-counted-by.c
M llvm/include/llvm/Transforms/Utils/SCCPSolver.h
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/lib/Transforms/Scalar/SCCP.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll
M llvm/test/Transforms/SCCP/exact-flags.ll
M llvm/test/Transforms/SCCP/phis.ll
M llvm/test/Transforms/SCCP/pointer-nonnull.ll
Log Message:
-----------
[SCCP] Infer return attributes in SCCP as well (#106732)
We can infer the range/nonnull attributes in non-interprocedural SCCP as
well. The results may be better after the function has been simplified.
Commit: d7100111f41ca314c094987d880d1648b78256af
https://github.com/llvm/llvm-project/commit/d7100111f41ca314c094987d880d1648b78256af
Author: Brad Smith <brad at comstyle.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Support/Unix/Threading.inc
Log Message:
-----------
[llvm][Support] Adjust maximum thread name length to the right value for OpenBSD (#106956)
The thread name length is derived from _MAXCOMLEN which is 24.
Commit: b9bba6ca9fc62c5ae3ee402196b11a523a500fdc
https://github.com/llvm/llvm-project/commit/b9bba6ca9fc62c5ae3ee402196b11a523a500fdc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/BasicAA/gep-nuw-alias.ll
Log Message:
-----------
[BasicAA] Track nuw through decomposed expressions (#106512)
When we decompose the GEP offset expression, and the arithmetic is not
performed using nuw operations, we cannot retain the nuw flag on the
decomposed GEP.
For example, if we have `gep nuw p, (a-1)`, this is not at all the same
as `gep nuw (gep nuw p, a), -1`.
Fix this by tracking NUW through linear expression decomposition,
similarly to what we already do for the NSW flag.
This fixes the miscompilation reported in
https://github.com/llvm/llvm-project/pull/105496#issuecomment-2315322220.
Commit: c42512436b23ab50e7637f239abe8371407104a1
https://github.com/llvm/llvm-project/commit/c42512436b23ab50e7637f239abe8371407104a1
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/lib/Conversion/ArithToArmSME/ArithToArmSME.cpp
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
M mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
M mlir/test/Conversion/ArithToArmSME/arith-to-arm-sme.mlir
M mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir
M mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
M mlir/test/Conversion/VectorToArmSME/vector-to-arm-sme.mlir
M mlir/test/Dialect/ArmSME/invalid.mlir
M mlir/test/Dialect/ArmSME/roundtrip.mlir
M mlir/test/Dialect/ArmSME/tile-allocation-copies.mlir
M mlir/test/Dialect/ArmSME/tile-allocation-liveness.mlir
Log Message:
-----------
[mlir][ArmSME] Rename slice move operations to insert/extract_tile_slice (#106755)
This renames:
- `arm_sme.move_tile_slice_to_vector` to `arm_sme.extract_tile_slice`
- `arm_sme.move_vector_to_tile_slice` to `arm_sme.insert_tile_slice`
The new names are more consistent with the rest of MLIR and should be
easier to understand. The current names (to me personally) are hard to
parse and easy to mix up when skimming through code.
Additionally, the syntax for `insert_tile_slice` has changed from:
```mlir
%4 = arm_sme.insert_tile_slice %0, %1, %2
: vector<[16]xi8> into vector<[16]x[16]xi8>
```
To:
```mlir
%4 = arm_sme.insert_tile_slice %0, %1[%2]
: vector<[16]xi8> into vector<[16]x[16]xi8>
```
This is for consistency with `extract_tile_slice`, but also helps with
readability as it makes it clear which operand is the index.
Commit: 1e65b765879fb39214b28d96e3305fa3599581db
https://github.com/llvm/llvm-project/commit/1e65b765879fb39214b28d96e3305fa3599581db
Author: Brad Smith <brad at comstyle.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/cmake/config-ix.cmake
M llvm/include/llvm/Config/config.h.cmake
M llvm/lib/Support/Unix/Threading.inc
Log Message:
-----------
[llvm][Support] Add support for thread naming under DragonFly BSD and Solaris/illumos (#106944)
Commit: 751975530e1041e5a8fb12cf57d5378c058d6d93
https://github.com/llvm/llvm-project/commit/751975530e1041e5a8fb12cf57d5378c058d6d93
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.h
M mlir/test/CAPI/llvm.c
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
Log Message:
-----------
Reapply "[MLIR][LLVM] Make DISubprogramAttr cyclic" (#106571) with fixes (#106947)
This reverts commit fa93be4, restoring
commit d884b77, with fixes that ensure the CAPI declarations are
exported properly.
This commit implements LLVM_DIRecursiveTypeAttrInterface for the
DISubprogramAttr to ensure cyclic subprograms can be imported properly.
In the process multiple shortcuts around the recently introduced
DIImportedEntityAttr can be removed.
Commit: 5dcea4628d7206d4351101850655356d4a8fc24a
https://github.com/llvm/llvm-project/commit/5dcea4628d7206d4351101850655356d4a8fc24a
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/IR/AutoUpgrade.cpp
A llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll
Log Message:
-----------
[AutoUpgrade] Preserve attributes when upgrading named struct return
For example, if the argument has an alignment attribute, preserve it.
Commit: 25f87f2d703178bb4bc13a62cb3df001b186cba2
https://github.com/llvm/llvm-project/commit/25f87f2d703178bb4bc13a62cb3df001b186cba2
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/TypeFinder.cpp
A llvm/test/DebugInfo/type-finder-w-dbg-records.ll
Log Message:
-----------
[DebugInfo][RemoveDIs] Find types hidden in DbgRecords (#106547)
When serialising to textual IR, there can be constant Values referred to
by DbgRecords that don't appear anywhere else, and have types hidden
even deeper in side them. Enumerate these when enumerating all types.
Test by Mikael Holmén.
Commit: f79722b932ce40edf2937f3b9386e6fb43757bce
https://github.com/llvm/llvm-project/commit/f79722b932ce40edf2937f3b9386e6fb43757bce
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/test/AST/ByteCode/references.cpp
Log Message:
-----------
[clang][bytecode][NFC] Move test case to -verify=both style
Commit: f19dff1b80172ff5628bb9ecef760c65f78ba0d9
https://github.com/llvm/llvm-project/commit/f19dff1b80172ff5628bb9ecef760c65f78ba0d9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/scmp.ll
M llvm/test/CodeGen/X86/ucmp.ll
Log Message:
-----------
[X86] scmp/ucmp - add SSE42/AVX2/AVX512 test coverage to show current state of vector legalization/lowering
Commit: a9c71d36655bd188521c74ce7834983e8c2a86cc
https://github.com/llvm/llvm-project/commit/a9c71d36655bd188521c74ce7834983e8c2a86cc
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][vector] Add more tests for ConvertVectorToLLVM (5/n) (#106510)
Commit: e90b21959a95df9a31056ec7fd6be9881cc63b95
https://github.com/llvm/llvm-project/commit/e90b21959a95df9a31056ec7fd6be9881cc63b95
Author: Christian Sigg <csigg at google.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M utils/bazel/llvm_configs/config.h.cmake
Log Message:
-----------
[llvm][bazel] Port 1e65b76 to bazel.
https://github.com/llvm/llvm-project/commit/1e65b765879fb39214b28d96e3305fa3599581db
Commit: bdfd7804902b92f53ace85afb96bc54054d03f9c
https://github.com/llvm/llvm-project/commit/bdfd7804902b92f53ace85afb96bc54054d03f9c
Author: Alastair Houghton <ahoughton at apple.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.h
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
Log Message:
-----------
[RuntimeDyld][Windows] Allocate space for dllimport things. (#106958)
We weren't taking account of the space we require in the stubs for
things that are dllimported, and as a result we could hit the assertion
failure for running out of stub space. Fix that.
Also add a couple of `override` specifiers that were missing last time
(#102586).
rdar://133473673
Commit: 4ed90920a84272a4e1737db9bdd50d57cade3cf4
https://github.com/llvm/llvm-project/commit/4ed90920a84272a4e1737db9bdd50d57cade3cf4
Author: Roger Ferrer Ibáñez <rofirrim at gmail.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M flang/lib/Lower/Mangler.cpp
A flang/test/Lower/module-generic-with-specific-mangling.f90
Log Message:
-----------
[Flang][Lower] Handle mangling of a generic name with a homonym specific procedure (#106693)
This may happen when using modules.
Fixes #93707
Commit: f838d6b1b2d84d3149685c3a3896dc82889563f7
https://github.com/llvm/llvm-project/commit/f838d6b1b2d84d3149685c3a3896dc82889563f7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Function.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/ms.cpp
Log Message:
-----------
[clang][bytecode] Implement __noop (#106714)
This does nothing and returns 0.
Commit: a9006bffa994d5afe9ad0b661b69d655658ab5e8
https://github.com/llvm/llvm-project/commit/a9006bffa994d5afe9ad0b661b69d655658ab5e8
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/SemaObjC/non-trivial-c-union.m
Log Message:
-----------
[clang][bytecode] Fix zero-init of first union member (#106962)
... if done via a ImplicitValueInitExpr.
We were already doing this later in visitZeroRecordInitializer().
Commit: 224112f8334f944ecb354bff8d57d85274037b85
https://github.com/llvm/llvm-project/commit/224112f8334f944ecb354bff8d57d85274037b85
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/test/CodeGen/ARM/arm-vld1.ll
Log Message:
-----------
[ARM] Regenerate test checks (NFC)
Commit: 60ed1043d76554a48f66fc0c15fb97ac8b3af7b0
https://github.com/llvm/llvm-project/commit/60ed1043d76554a48f66fc0c15fb97ac8b3af7b0
Author: kadir çetinkaya <kadircet at google.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang-tools-extra/include-cleaner/lib/WalkAST.cpp
M clang-tools-extra/include-cleaner/unittests/WalkASTTest.cpp
Log Message:
-----------
[include-cleaner] Report refs for enum constants used through namespace aliases (#106706)
Commit: 8b2ad5c8f18096c8ef25d77906391b7c09342137
https://github.com/llvm/llvm-project/commit/8b2ad5c8f18096c8ef25d77906391b7c09342137
Author: Marius Brehler <marius.brehler at amd.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/test/Target/Cpp/common-cpp.mlir
Log Message:
-----------
[mlir][EmitC] Remove restrictions on include op (#106953)
An `emitc.include` should be usable even though the parent is not a
ModuleOp. This requirement is therefore removed.
Commit: b32dc677325ccf992f7e957e15e97f41fdfa9c77
https://github.com/llvm/llvm-project/commit/b32dc677325ccf992f7e957e15e97f41fdfa9c77
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
Log Message:
-----------
Revert "[compiler-rt][fuzzer] SetThreadName build fix for Mingwin attempt (#106902)"
This reverts commit 7c4cffd9d8be424e9e9542be9aec3b5a6f69073e.
This commit broke compilation in environments that don't use
winpthreads.
Commit: dc3f66af58db258287e1c2dbfb3f06916b463227
https://github.com/llvm/llvm-project/commit/dc3f66af58db258287e1c2dbfb3f06916b463227
Author: Mital Ashok <mital at mitalashok.co.uk>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/include/clang/Basic/TargetCXXABI.def
Log Message:
-----------
[NFC] Fix dead links in TargetCXXABI.def (#96348)
http://itanium-cxx-abi.github.io/cxx-abi/
> This website may be mirrored in many places, some of which may become
stale. The current canonical location is:
> * http://itanium-cxx-abi.github.io/cxx-abi/
https://github.com/ARM-software/abi-aa
> This is the official place for the latest documents of the Application
Binary Interface for the Arm® Architecture, both for source files and
officially released documents.
Commit: dc6c3ba4c4372172f504fcbe440f62932edf1cc1
https://github.com/llvm/llvm-project/commit/dc6c3ba4c4372172f504fcbe440f62932edf1cc1
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
Log Message:
-----------
[NFC][IR] Add CreateCountTrailingZeroElems helper (#106711)
The LoopIdiomVectorize pass already creates calls to the intrinsic
experimental_cttz_elts, but PR #88385 will start calling this more
too so I've created a helper for it.
Commit: 0c0bac94c08e73d4c35b454ba02317f2db313f93
https://github.com/llvm/llvm-project/commit/0c0bac94c08e73d4c35b454ba02317f2db313f93
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/ARM/neon-intrinsics.ll
Log Message:
-----------
[InstCombine] Add additional tests for arm intrinsic alignment (NFC)
Commit: 181cc75ea8be70e3fa7145456e1bf2331e0bc5e4
https://github.com/llvm/llvm-project/commit/181cc75ea8be70e3fa7145456e1bf2331e0bc5e4
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
A lldb/test/API/functionalities/memory/holes/Makefile
A lldb/test/API/functionalities/memory/holes/TestMemoryHoles.py
A lldb/test/API/functionalities/memory/holes/main.cpp
Log Message:
-----------
[lldb/linux] Make truncated reads work (#106532)
Previously, we were returning an error if we couldn't read the whole
region. This doesn't matter most of the time, because lldb caches memory
reads, and in that process it aligns them to cache line boundaries. As
(LLDB) cache lines are smaller than pages, the reads are unlikely to
cross page boundaries.
Nonetheless, this can cause a problem for large reads (which bypass the
cache), where we're unable to read anything even if just a single byte
of the memory is unreadable. This patch fixes the lldb-server to do
that, and also changes the linux implementation, to reuse any partial
results it got from the process_vm_readv call (to avoid having to
re-read everything again using ptrace, only to find that it stopped at
the same place).
This matches debugserver behavior. It is also consistent with the gdb
remote protocol documentation, but -- notably -- not with actual
gdbserver behavior (which returns errors instead of partial results). We
filed a
[clarification
bug](https://sourceware.org/bugzilla/show_bug.cgi?id=24751) several
years ago. Though we did not really reach a conclusion there, I think
this is the most logical behavior.
The associated test does not currently pass on windows, because the
windows memory read APIs don't support partial reads (I have a WIP patch
to work around that).
Commit: b0de7fa4668743aec14c6ccae287ac9f8f7d343b
https://github.com/llvm/llvm-project/commit/b0de7fa4668743aec14c6ccae287ac9f8f7d343b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
Log Message:
-----------
[VPlan] Use op from underlying call in computeCost if needed.
This fixes a divergence between legacy and VPlan-based cost model, e.g.
if one of the operands has an first-order recurrence phi as operand.
Commit: ef26afcb88dcb5f2de79bfc3cf88a8ea10f230ec
https://github.com/llvm/llvm-project/commit/ef26afcb88dcb5f2de79bfc3cf88a8ea10f230ec
Author: Hans <hans at hanshq.net>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/utils/release/build_llvm_release.bat
Log Message:
-----------
Win release packaging: Don't try to use rpmalloc for 32-bit x86 (#106969)
because that doesn't work (results in `LINK : error LNK2001: unresolved
external symbol malloc`).
Based on the title of #91862 it was only intended for use in 64-bit
builds.
Commit: df3d70b5a72fee43af3793c8b7a138bd44cac8cf
https://github.com/llvm/llvm-project/commit/df3d70b5a72fee43af3793c8b7a138bd44cac8cf
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll
A llvm/test/Analysis/ScalarEvolution/predicated-exit-count.ll
M llvm/test/Analysis/ScalarEvolution/predicated-symbolic-max-backedge-taken-count.ll
Log Message:
-----------
[Analysis] Add getPredicatedExitCount to ScalarEvolution (#105649)
Due to a reviewer request on PR #88385 I have created this patch
to add a getPredicatedExitCount function, which is similar to
getExitCount except that it uses the predicated backedge taken
information. With PR #88385 we will start to care about more
loops with multiple exits, and want the ability to query exit
counts for a particular exiting block. Such loops may require
predicates in order to be vectorised.
New tests added here:
Analysis/ScalarEvolution/predicated-exit-count.ll
Commit: 44cfbef1b3cb0dd33886cc27441930008a245963
https://github.com/llvm/llvm-project/commit/44cfbef1b3cb0dd33886cc27441930008a245963
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
A llvm/test/CodeGen/AArch64/partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64] Lower partial add reduction to udot or svdot (#101010)
This patch introduces lowering of the partial add reduction intrinsic to
a udot or svdot for AArch64. This also involves adding a
`shouldExpandPartialReductionIntrinsic` target hook, which AArch64 will
return false from in the cases that it can be lowered.
Commit: b47d7ce8121b1cb1923e879d58eaa1d63aeaaae2
https://github.com/llvm/llvm-project/commit/b47d7ce8121b1cb1923e879d58eaa1d63aeaaae2
Author: kadir çetinkaya <kadircet at google.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang-tools-extra/clangd/TidyFastChecks.inc
Log Message:
-----------
[clangd] Update TidyFastChecks for release/19.x (#106354)
Run for clang-tidy checks available in release/19.x branch.
Some notable findings:
- altera-id-dependent-backward-branch, stays slow with 13%.
- misc-const-correctness become faster, going from 261% to 67%, but
still above
8% threshold.
- misc-header-include-cycle is a new SLOW check with 10% runtime
implications
- readability-container-size-empty went from 16% to 13%, still SLOW.
Commit: ad30a050caae724c1f4f0dfa8f26e6bee45aa0ad
https://github.com/llvm/llvm-project/commit/ad30a050caae724c1f4f0dfa8f26e6bee45aa0ad
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/unittests/Support/FormatVariadicTest.cpp
Log Message:
-----------
[NFC][Support] Add FormatVariadic sub-test for validation (#106578)
- Add validation subtest that tests assert failures in assert enabled
builds, and that validation is disabled in assert disabled builds.
Commit: e5c7cde5c812535c1ac8368ffdda3f503ccce013
https://github.com/llvm/llvm-project/commit/e5c7cde5c812535c1ac8368ffdda3f503ccce013
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/utils/TableGen/IntrinsicEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Refactor `getIntrinsicFnAttributeSet` (#106587)
Fix intrinsic function attributes to not generate attribute sets that
are empty in `getIntrinsicFnAttributeSet`. Refactor the code to use
helper functions to get effective memory effects for an intrinsic and to
check if it has non-default attributes.
This eliminates one case statement in `getIntrinsicFnAttributeSet` that
we generate today for the case when intrinsic attributes are default
ones.
Also rename `Intrinsic` to `Int` to follow the naming convention used in
this file and adjust emission code to not emit unnecessary empty line
between cases generated.
Commit: b6a4ab5a12c9ced0642769e4b2d8f77859541ba8
https://github.com/llvm/llvm-project/commit/b6a4ab5a12c9ced0642769e4b2d8f77859541ba8
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/docs/AssignmentTracking.md
Log Message:
-----------
[NFC] Fix #106873 - update assignment tracking docs (#106959)
Commit: 4a505e15e768011e47101cf9aeb0c7787fdc9acf
https://github.com/llvm/llvm-project/commit/4a505e15e768011e47101cf9aeb0c7787fdc9acf
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/test/CXX/drs/cwg14xx.cpp
M clang/test/CXX/drs/cwg19xx.cpp
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg3xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add tests for CWG issues about friend declaration matching (#106117)
This patch covers CWG issues regarding declaration matching when
`friend` declarations are involved:
[CWG138](https://cplusplus.github.io/CWG/issues/138.html),
[CWG386](https://cplusplus.github.io/CWG/issues/386.html),
[CWG1477](https://cplusplus.github.io/CWG/issues/1477.html), and
[CWG1900](https://cplusplus.github.io/CWG/issues/1900.html). Atypical
for our CWG tests, the ones in this patch are quite extensively
commented in-line, explaining the mechanics. PR description focuses on
high-level concerns and references.
[CWG138](https://cplusplus.github.io/CWG/issues/138.html) "Friend
declaration name lookup"
-----------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
> [CWG138](https://cplusplus.github.io/CWG/issues/138.html) is resolved
according to [N1229](http://wg21.link/n1229), except that
using-directives that nominate nested namespaces are considered.
I find it hard to pin down the scope of this issue, so I'm relying on
three examples from the filing to define it. Because of that, it's also
hard to pinpoint exact wording changes that resolve it. Relevant
references are:
[[dcl.meaning.general]/2](http://eel.is/c++draft/dcl.meaning#general-2),
[[namespace.udecl]/10](https://eel.is/c++draft/namespace.udecl#10),
[[dcl.type.elab]/3](https://eel.is/c++draft/dcl.type.elab#3),
[[basic.lookup.elab]/1](https://eel.is/c++draft/basic.lookup.elab#1).
[CWG386](https://cplusplus.github.io/CWG/issues/386.html) "Friend
declaration of name brought in by _using-declaration_"
-----------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
> [CWG386](https://cplusplus.github.io/CWG/issues/386.html),
[CWG1839](https://cplusplus.github.io/CWG/issues/1839.html),
[CWG1818](https://cplusplus.github.io/CWG/issues/1818.html),
[CWG2058](https://cplusplus.github.io/CWG/issues/2058.html),
[CWG1900](https://cplusplus.github.io/CWG/issues/1900.html), and
Richard’s observation in [“are non-type names ignored in a
class-head-name or
enum-head-name?”](http://lists.isocpp.org/core/2017/01/1604.php) are
resolved by describing the limited lookup that occurs for a
declarator-id, including the changes in Richard’s [proposed resolution
for
CWG1839](http://wiki.edg.com/pub/Wg21cologne2019/CoreWorkingGroup/cwg1839.html)
(which also resolves CWG1818 and what of CWG2058 was not resolved along
with CWG2059) and rejecting the example from
[CWG1477](https://cplusplus.github.io/CWG/issues/1477.html).
Wording
([[dcl.meaning.general]/2](http://eel.is/c++draft/dcl.meaning#general-2)):
> — If the
[id-expression](http://eel.is/c++draft/expr.prim.id.general#nt:id-expression)
E in the
[declarator-id](http://eel.is/c++draft/dcl.decl.general#nt:declarator-id)
of the
[declarator](http://eel.is/c++draft/dcl.decl.general#nt:declarator) is a
[qualified-id](http://eel.is/c++draft/expr.prim.id.qual#nt:qualified-id)
or a [template-id](http://eel.is/c++draft/temp.names#nt:template-id):
> — [...]
> — The
[declarator](http://eel.is/c++draft/dcl.decl.general#nt:declarator)
shall correspond to one or more declarations found by the lookup; they
shall all have the same target scope, and the target scope of the
[declarator](http://eel.is/c++draft/dcl.decl.general#nt:declarator) is
that
scope[.](http://eel.is/c++draft/dcl.meaning#general-2.2.2.sentence-1)
This issue focuses on interaction of `friend` declarations with
template-id and qualified-id with using-declarations. The short answer
is that terminal name in such declarations undergo lookup, and
using-declarations do what they usually do helping that lookup. Target
scope of such friend declaration is the target scope of lookup result,
so no conflicts arise with the using-declarations.
[CWG1477](https://cplusplus.github.io/CWG/issues/1477.html) "Definition
of a `friend` outside its namespace"
-----------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
> [...] and rejecting the example from
[CWG1477](https://cplusplus.github.io/CWG/issues/1477.html).
Wording
([[dcl.meaning.general]/3.4](http://eel.is/c++draft/dcl.meaning#general-3.4)):
> Otherwise, the terminal name of the
[declarator-id](http://eel.is/c++draft/dcl.decl.general#nt:declarator-id)
is not looked
up[.](http://eel.is/c++draft/dcl.meaning#general-3.4.sentence-1)
If it is a qualified name, the
[declarator](http://eel.is/c++draft/dcl.decl.general#nt:declarator)
shall correspond to one or more declarations nominable in S; all the
declarations shall have the same target scope and the target scope of
the [declarator](http://eel.is/c++draft/dcl.decl.general#nt:declarator)
is that
scope[.](http://eel.is/c++draft/dcl.meaning#general-3.4.sentence-2)
This issue focuses on befriending a function in one scope, then defining
it from other scope using qualified-id. Contrary to what P1787R6 says in
prose, this example is accepted by the wording in that paper. In the
wording quote above, note the absence of a statement like "terminal name
of the declarator-id is not bound", contrary to similar statements made
before that in [dcl.meaning.general] about friend declarations and
template-ids.
There's also a note in [basic.scope.scope] that supports the rejection,
but it's considered incorrect and expected to be removed in the future.
This is tracked in https://github.com/cplusplus/draft/pull/7238.
[CWG1900](https://cplusplus.github.io/CWG/issues/1900.html) "Do `friend`
declarations count as “previous declarations”?"
------------------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
> [CWG386](https://cplusplus.github.io/CWG/issues/386.html),
[CWG1839](https://cplusplus.github.io/CWG/issues/1839.html),
[CWG1818](https://cplusplus.github.io/CWG/issues/1818.html),
[CWG2058](https://cplusplus.github.io/CWG/issues/2058.html),
[CWG1900](https://cplusplus.github.io/CWG/issues/1900.html), and
Richard’s observation in [“are non-type names ignored in a
class-head-name or
enum-head-name?”](http://lists.isocpp.org/core/2017/01/1604.php) are
resolved by describing the limited lookup that occurs for a
declarator-id, including the changes in Richard’s [proposed resolution
for
CWG1839](http://wiki.edg.com/pub/Wg21cologne2019/CoreWorkingGroup/cwg1839.html)
(which also resolves CWG1818 and what of CWG2058 was not resolved along
with CWG2059) and rejecting the example from
[CWG1477](https://cplusplus.github.io/CWG/issues/1477.html).
Wording
([[dcl.meaning.general]/2.3](http://eel.is/c++draft/dcl.meaning#general-2.3)):
> The declaration's target scope is the innermost enclosing namespace
scope; if the declaration is contained by a block scope, the declaration
shall correspond to a reachable
([[module.reach]](http://eel.is/c++draft/module.reach)) declaration that
inhabits the innermost block
scope[.](http://eel.is/c++draft/dcl.meaning#general-2.3.sentence-2)
Wording
([[basic.scope.scope]/7](http://eel.is/c++draft/basic.scope#scope-7)):
> A declaration is
[nominable](http://eel.is/c++draft/basic.scope#def:nominable) in a
class, class template, or namespace E at a point P if it precedes P, it
does not inhabit a block scope, and its target scope is the scope
associated with E or, if E is a namespace, any element of the inline
namespace set of E
([[namespace.def]](http://eel.is/c++draft/namespace.def))[.](http://eel.is/c++draft/basic.scope#scope-7.sentence-1)
Wording
([[dcl.meaning.general]/3.4](http://eel.is/c++draft/dcl.meaning#general-3.4)):
> If it is a qualified name, the
[declarator](http://eel.is/c++draft/dcl.decl.general#nt:declarator)
shall correspond to one or more declarations nominable in S; [...]
In the new wording it's clear that while `friend` declarations of
functions do not bind names, declaration is still introduced, and is
nominable, making it eligible for a later definition by qualified-id.
Commit: 30d56bedd0a77c4c075e4cdc6191611bb84c8a49
https://github.com/llvm/llvm-project/commit/30d56bedd0a77c4c075e4cdc6191611bb84c8a49
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan_context.cpp
M compiler-rt/lib/rtsan/rtsan_context.h
M compiler-rt/lib/rtsan/tests/rtsan_test_context.cpp
Log Message:
-----------
[compiler-rt][rtsan] NFC: Refactor context helper functions (#106869)
Commit: 26bf0b4ae7df7f5350f71afd40a57cdf8f98c588
https://github.com/llvm/llvm-project/commit/26bf0b4ae7df7f5350f71afd40a57cdf8f98c588
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/docs/Multilib.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Driver/Multilib.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/Multilib.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/OHOS.cpp
A clang/test/Driver/baremetal-multilib-custom-error.yaml
M clang/unittests/Driver/MultilibBuilderTest.cpp
M clang/unittests/Driver/MultilibTest.cpp
M clang/unittests/Driver/SimpleDiagnosticConsumer.h
Log Message:
-----------
[clang][Driver] Add a custom error option in multilib.yaml. (#105684)
Sometimes a collection of multilibs has a gap in it, where a set of
driver command-line options can't work with any of the available
libraries.
For example, the Arm MVE extension requires special startup code (you
need to initialize FPSCR.LTPSIZE), and also benefits greatly from
-mfloat-abi=hard. So a multilib provider might build a library for
systems without MVE, and another for MVE with -mfloat-abi=hard,
anticipating that that's what most MVE users would want. But then if a
user compiles for MVE _without_ -mfloat-abi=hard, thhey can't use either
of those libraries – one has an ABI mismatch, and the other will fail to
set up LTPSIZE.
In that situation, it's useful to include a multilib.yaml entry for the
unworkable intermediate situation, and have it map to a fatal error
message rather than a set of actual libraries. Then the user gets a
build failure with a sensible explanation, instead of selecting an
unworkable library and silently generating bad output. The new
regression test demonstrates this case.
This patch introduces extra syntax into multilib.yaml, so that a record
in the `Variants` list can omit the `Dir` key, and in its place, provide
a `FatalError` key. Then, if that variant is selected, the error message
is emitted as a clang diagnostic, and multilib selection fails.
In order to emit the error message in `MultilibSet::select`, I had to
pass a `Driver &` to that function, which involved plumbing one through
to every call site, and in the unit tests, constructing one specially.
Commit: f32f0289fd57971759d7cab9da8d56863eee86ae
https://github.com/llvm/llvm-project/commit/f32f0289fd57971759d7cab9da8d56863eee86ae
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
Log Message:
-----------
[NFC] Update check lines of the test case `llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll`
Commit: cb949b74e8fdfd04821c0fa5da961f91496d3682
https://github.com/llvm/llvm-project/commit/cb949b74e8fdfd04821c0fa5da961f91496d3682
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
Log Message:
-----------
[NFC][FIX] Work around update_test_checks bug
Commit: 38ae53da15c6636c0d13ccf20415b5ce8541aefd
https://github.com/llvm/llvm-project/commit/38ae53da15c6636c0d13ccf20415b5ce8541aefd
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/lib/AST/ASTContext.cpp
Log Message:
-----------
[clang][AST][NFC] Make ASTContext::UnwrapSimilar{Array,}Types const (#106992)
They don't mutate the context at all, so mark them const.
Commit: 55eb93b2688de99ada14c71804af99502276ac79
https://github.com/llvm/llvm-project/commit/55eb93b2688de99ada14c71804af99502276ac79
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
Log Message:
-----------
[RISCV] Remove RISCVISD::FP_EXTEND_BF16. (#106939)
I don't think we need this node. We can isel fp_extend directly.
fp_extend to f64 requires two instructions, but we can emit them with an
isel pattern.
I have not removed RISCVISD::FP_ROUND_BF16 because f64->bf16 needs more
work to fix the double rounding.
Commit: a586b5a49dbd3b6c658f9edbf0b4a9be0b108a14
https://github.com/llvm/llvm-project/commit/a586b5a49dbd3b6c658f9edbf0b4a9be0b108a14
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
A llvm/test/MC/AArch64/SVE/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE/directive-cpu-negative.s
M llvm/test/MC/AArch64/directive-arch-negative.s
M llvm/test/MC/AArch64/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/directive-cpu-err.s
Log Message:
-----------
Reland [AArch64][AsmParser] Directives should clear transitively implied features (#106625) (#106850)
Relands 24977395592f addressing the buffer overflow caused when
dereferencing an iterator past the end of ExtensionMap.
Commit: 50a02e7c68f964c5d8338369746c849ed8d3bef4
https://github.com/llvm/llvm-project/commit/50a02e7c68f964c5d8338369746c849ed8d3bef4
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
Log Message:
-----------
[VPlan] Pass intrinsic inst to TTI in VPWidenCallRecipe::computeCost.
Follow-up to 9ccf825, adjust computeCost to also pass IntrinsicInst to
TTI if available, as there are multiple places in TTI which use the
IntrinsicInst.
Fixes https://github.com/llvm/llvm-project/issues/107016.
Commit: 954ed05c1001489802ae43d4bea403181570a799
https://github.com/llvm/llvm-project/commit/954ed05c1001489802ae43d4bea403181570a799
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
A llvm/test/Transforms/LoopVectorize/AArch64/mul-simplification.ll
Log Message:
-----------
[VPlan] Simplify MUL operands at recipe construction.
This moves the logic to create simplified operands using SCEV to MUL
recipe creation. This is needed to match the behavior of the legacy's cost
model. TODOs are to extend to other opcodes and move to a transform.
Note that this also restricts the number of SCEV simplifications we
apply to more precisely match the cases handled by the legacy cost
model.
Fixes https://github.com/llvm/llvm-project/issues/107015.
Commit: ecc9aece72989461167ba39541dce51032c0d76d
https://github.com/llvm/llvm-project/commit/ecc9aece72989461167ba39541dce51032c0d76d
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M lld/COFF/InputFiles.cpp
A lld/test/COFF/arm64ec-lib.test
Log Message:
-----------
[LLD][COFF] Use archive's ECSYMBOLS on ARM64EC target when available. (#106904)
Commit: 7e8aba2b993014d975cf35f1f9831c951c4ab292
https://github.com/llvm/llvm-project/commit/7e8aba2b993014d975cf35f1f9831c951c4ab292
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M clang/lib/Basic/OpenMPKinds.cpp
Log Message:
-----------
[clang][OpenMP] `masked` and `master` are not capturing (#106787)
Commit: 0ba006daf5d9f10017ba15b4287c272912a34d73
https://github.com/llvm/llvm-project/commit/0ba006daf5d9f10017ba15b4287c272912a34d73
Author: Jesse D <jesse.a.deguire at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/test/MC/Mips/cnmips/invalid-wrong-error.s
M llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s
M llvm/test/MC/Mips/eva/invalid_R6.s
M llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
M llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s
M llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s
M llvm/test/MC/Mips/mips1/invalid-mips3.s
M llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
M llvm/test/MC/Mips/mips1/invalid-mips4.s
M llvm/test/MC/Mips/mips1/invalid-mips5.s
M llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s
M llvm/test/MC/Mips/mips2/invalid-mips3.s
M llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s
M llvm/test/MC/Mips/mips2/invalid-mips4.s
M llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
M llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
M llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s
M llvm/test/MC/Mips/target-soft-float.s
Log Message:
-----------
[MIPS] Fix error messages when rejecting certain assembly not supported by ISA (#94695)
… instructions.
This is a fix I stumbled upon while working on something else. I decided
to break it out since it seems like a good "first issue" to submit. I
updated the comments in the "wrong error" test files to indicate that
the messages are no longer incorrect, but I left the names of the test
files alone. I was not sure what to do with those, so I would appreciate
thoughts or guidance.
Commit: 366ac8c09051b6e293ecc0390168f505b56f6654
https://github.com/llvm/llvm-project/commit/366ac8c09051b6e293ecc0390168f505b56f6654
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Log Message:
-----------
[LegalizeVectorOps] Defer UnrollVectorOp in ExpandFNEG to caller. (#106783)
Make ExpandFNEG return SDValue() when it doesn't expand. The caller
already knows how to Unroll when Results is empty.
Commit: b6597f521d8a040f2b9fee54b3f89c380de8e432
https://github.com/llvm/llvm-project/commit/b6597f521d8a040f2b9fee54b3f89c380de8e432
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
Log Message:
-----------
[gn] port 1e65b765879fb39
Apparently DragonFly BSD and Solaris/illumos call these APIs
`pthread_get_name_np` / `pthread_set_name_np` (with an extra
underscore) instead of `pthread_getname_np` / `pthread_setname_np`.
Commit: ba3c1edcc8cf96206df259bd07001fa7ee9957cb
https://github.com/llvm/llvm-project/commit/ba3c1edcc8cf96206df259bd07001fa7ee9957cb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
Log Message:
-----------
[RISCV] Correct the scheduler class for FCVT_S_BF16. (#107028)
Use FCvtF16ToF32 instead of FCvtF32ToF16.
Commit: 9a1d14a8d26778a5d2d24928ba11cc557c2df24b
https://github.com/llvm/llvm-project/commit/9a1d14a8d26778a5d2d24928ba11cc557c2df24b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/FunctionImport.h
Log Message:
-----------
[LTO] Don't make unnecessary copies of ImportIDTable (#106998)
Without this patch, {ImportMapTy,SortedImportList}::{begin,end} make
unnecessary copies of ImportIDTable via:
map_iterator(Imports.begin(), IDs);
The second parameter, IDs, is passed by value, so we make a copy of
MapVector inside ImportIDTable every time we call begin and end.
These begin and end show up as time-consuming functions in the
performance profile.
This patch fixes the problem by passing IDs by reference with
std::cref.
While we are at it, this patch deletes the copy constructor and
assignment operator. I cannot think of any legitimate need reason to
make a copy of the deduplication table.
Commit: dc19b59ea2502193c0e7bc16bb7d711c8053edcf
https://github.com/llvm/llvm-project/commit/dc19b59ea2502193c0e7bc16bb7d711c8053edcf
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
Log Message:
-----------
[RISCV] Rename test cases in bfloat-arith.ll and half-arith.ll. NFC
Use _bf16 or _h instead of _s. The _s was copied from float-arith.ll
Commit: 2cbd1bc830861bc08f78fb6cc11747b82f66c4c6
https://github.com/llvm/llvm-project/commit/2cbd1bc830861bc08f78fb6cc11747b82f66c4c6
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/test/Modules/no-local-decl-in-reduced-bmi.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview-std.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview.cppm
M clang/test/Modules/unreached-static-entities.cppm
Log Message:
-----------
Revert "[C++20] [Modules] Embed all source files for C++20 Modules (#102444)"
This reverts commit 2eeeff842f993a694159183a2834b4d305549cad.
See the post commit discussion in
https://github.com/llvm/llvm-project/commit/2eeeff842f993a694159183a2834b4d305549cad
Commit: 78abeca1d88593d7f2a27f3c3e140abe77236e7e
https://github.com/llvm/llvm-project/commit/78abeca1d88593d7f2a27f3c3e140abe77236e7e
Author: s-watanabe314 <watanabe.shu-06 at fujitsu.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaCXX/extern-c.cpp
Log Message:
-----------
[clang][Sema] Fix diagnostic for function overloading in extern "C" (#106033)
Fixes #80235
When trying to overload a function within `extern "C"`, the diagnostic
`functions that differ only in their return type cannot be overloaded`
is given. This diagnostic is inappropriate because overloading is
basically not allowed in the C language. However, if the redeclared
function has the `((overloadable))` attribute, it should be diagnosed as
`functions that differ only in their return type cannot be overloaded`.
This patch uses `isExternC()` to provide an appropriate diagnostic
during the diagnostic process. `isExternC()` updates the linkage
information cache internally, so calling it before merging functions can
cause clang to crash. An example is declaring `static void foo()` and
`void foo()` within an `extern "C"` block. Therefore, I decided to call
`isExternC()` after the compilation error is confirmed and select the
diagnostic message. The diagnostic message is `conflicting types for
'func'` similar to the diagnostic in C, and `functions that differ only
in their return type cannot be overloaded` if the `((overloadable))`
attribute is given.
Regression tests verify that the expected diagnostics are given when
trying to overload functions within `extern "C"` and when the
`((overloadable))` attribute is present.
---------
Co-authored-by: Sirraide <aeternalmail at gmail.com>
Commit: 9a1eded9b9afa3eab1e0b5cad5dbff3117d22391
https://github.com/llvm/llvm-project/commit/9a1eded9b9afa3eab1e0b5cad5dbff3117d22391
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
The LegalizeDAG expansion will go through memory since i16 isn't a legal
type. Avoid this by using FMV nodes.
Similar to what we did for #106886 for FNEG and FABS. Special care is
needed to handle the Sign operand being a different type.
Commit: 042104985cc37d28db5f22f8bdf582c1108977d8
https://github.com/llvm/llvm-project/commit/042104985cc37d28db5f22f8bdf582c1108977d8
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
A llvm/lib/Target/AMDGPU/SIShrinkInstructions.h
M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
Log Message:
-----------
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
Commit: 8e5b43c8effc0a01745bb7c53ca21fb6c8384c51
https://github.com/llvm/llvm-project/commit/8e5b43c8effc0a01745bb7c53ca21fb6c8384c51
Author: Akshat Oke <76596238+Akshat-Oke at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
Log Message:
-----------
[AMDGPU][NewPM] Have consistent property changes in GCNDPPCombine (#106520)
Commit: 7d7d2d2b54172f97300c02ec80bb568d35403cce
https://github.com/llvm/llvm-project/commit/7d7d2d2b54172f97300c02ec80bb568d35403cce
Author: Da-Viper <57949090+Da-Viper at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/instruction-breakpoint/TestDAP_instruction_breakpoint.py
Log Message:
-----------
[lldb-dap][test] Fix: Typo in unresolved test (#107030)
There is a typo in an assertion that causes the instruction break-point
test to be unresolved
Commit: 00c198b2ca6b6bee2d90e62d78816686ab056b1b
https://github.com/llvm/llvm-project/commit/00c198b2ca6b6bee2d90e62d78816686ab056b1b
Author: Michael Marjieh <99331190+mmarjieh at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
A llvm/test/CodeGen/PowerPC/sms-recmii.ll
M llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir
Log Message:
-----------
[MachinePipeliner] Make Recurrence MII More Accurate (#105475)
Current RecMII calculation is bigger than it needs to be. The
calculation was refined in this patch.
Commit: 7e6bad112c978d1dabfd2c6bef4674224b63583c
https://github.com/llvm/llvm-project/commit/7e6bad112c978d1dabfd2c6bef4674224b63583c
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
Log Message:
-----------
[RISCV] Rename `vcix_state` register to `sf_vcix_state`. NFC (#106995)
Since it's SiFive VCIX specific register, it's better to have a prefix
so that it's more understandable.
Commit: af5c18ad356ee334f3ec629149940f84d4b5f06d
https://github.com/llvm/llvm-project/commit/af5c18ad356ee334f3ec629149940f84d4b5f06d
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/www/index.html
Log Message:
-----------
[compiler-rt] [docs] Mention Windows as one of the supported OSes (#106874)
Compiler-rt can be built for Windows, and most parts of it work. Some
parts only really work on x86/x86_64 (like address sanitizers), but the
OS overall is supported.
Commit: 525ffd626231a8c6fecb0b886c272ff4568f09f5
https://github.com/llvm/llvm-project/commit/525ffd626231a8c6fecb0b886c272ff4568f09f5
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/test/Analysis/mmap-writeexec.c
Log Message:
-----------
[clang][analyzer] Bring alpha.security.MmapWriteExec checker out of alpha package (#102636)
Commit: 04ed12ca3f027a3a189d181e5e5880285ebc7916
https://github.com/llvm/llvm-project/commit/04ed12ca3f027a3a189d181e5e5880285ebc7916
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/test/API/functionalities/memory/holes/TestMemoryHoles.py
Log Message:
-----------
[lldb] Support partial memory reads on windows (#106981)
ReadProcessMemory will not perform the read if part of the memory is
unreadable (and even though the API has a `number_of_bytes_read`
argument). To make this work, I explicitly inspect the memory region
being read and only read the accessible part.
Commit: 6c8746b6e36260e31067765ac1c8dd6cd3f5b868
https://github.com/llvm/llvm-project/commit/6c8746b6e36260e31067765ac1c8dd6cd3f5b868
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
Log Message:
-----------
[Analysis] getIntrinsicForCallSite - add vectorization support for acos/asin/atan and cosh/sinh/tanh libcalls (#106844)
Followup to #106584 - ensure acos/asin/atan and cosh/sinh/tanh libcalls correctly map to the llvm intrinsic equivalents
Commit: 733a92d7bced7119986a93a1b4e1c760f92b9583
https://github.com/llvm/llvm-project/commit/733a92d7bced7119986a93a1b4e1c760f92b9583
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/constexpr-frame-describe.cpp
Log Message:
-----------
[clang][bytecode] Print Pointers via APValue (#107056)
Instead of doing this ourselves, just rely on printing the APValue.
Commit: a70d999203702e245a54bc694048c8817215c65e
https://github.com/llvm/llvm-project/commit/a70d999203702e245a54bc694048c8817215c65e
Author: Christian Sigg <csigg at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Attempt to fix issue fetching remote blob
Bazel builds currently fail with `Failed to fetch blobs because they do not exist remotely.`. These extra bazel flags hopefully fix it.
Commit: 6c59dfb0184aa11ec202f1cd8aee9e971a1565a4
https://github.com/llvm/llvm-project/commit/6c59dfb0184aa11ec202f1cd8aee9e971a1565a4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/movmsk-cmp.ll
Log Message:
-----------
[X86] Add test showing failure to remove freeze from all_of pattern
Commit: 851bacb7ce66213d667c6ed375ce43ab0ed3cd56
https://github.com/llvm/llvm-project/commit/851bacb7ce66213d667c6ed375ce43ab0ed3cd56
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/IR/DebugProgramInstruction.cpp
Log Message:
-----------
[IR] DebugProgramInstruction.cpp - fix GCC Wparentheses warning. NFC.
Commit: 4befe65cf065a1be8bb8f30d76a3f45ea45aa63f
https://github.com/llvm/llvm-project/commit/4befe65cf065a1be8bb8f30d76a3f45ea45aa63f
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Semantics/OpenMP/clause-order.f90
Log Message:
-----------
[flang][semantics][OpenMP] store DSA using ultimate sym (#107002)
Previously we tracked data sharing attributes by the symbol itself not
by the ultimate symbol. When the private clause came first, subsequent
uses of the symbol found a host-associated version instead of the
ultimate symbol and so the check didn't consider them to be the same
symbol. Always adding and checking for the ultimate symbol ensures that
we have the same behaviour no matter the order of clauses.
The modified list is only used for this multiple clause check.
Closes #78235
Commit: 377045ece6471a1e59bb5239707aad54ba035ff2
https://github.com/llvm/llvm-project/commit/377045ece6471a1e59bb5239707aad54ba035ff2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/movmsk-cmp.ll
Log Message:
-----------
[X86] canCreateUndefOrPoisonForTargetNode - X86ISD::CMPP (CMPPS/D) nodes do not generate poison
Commit: fe1a1eee2ff864d2ba00ad67e6360b7178e67d5c
https://github.com/llvm/llvm-project/commit/fe1a1eee2ff864d2ba00ad67e6360b7178e67d5c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/JumpThreading/pr22086.ll
M llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
M llvm/test/Transforms/SCCP/loadtest2.ll
M llvm/test/Transforms/SCCP/select.ll
Log Message:
-----------
[Tests] Regenerate test checks (NFC)
Commit: c3d8124617a0f7916123174001547eb3b4968644
https://github.com/llvm/llvm-project/commit/c3d8124617a0f7916123174001547eb3b4968644
Author: Nathan Gauër <brioche at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
A llvm/test/Other/spirv-sim/branch.spv
A llvm/test/Other/spirv-sim/call.spv
A llvm/test/Other/spirv-sim/constant.spv
A llvm/test/Other/spirv-sim/lit.local.cfg
A llvm/test/Other/spirv-sim/loop.spv
A llvm/test/Other/spirv-sim/simple-bad-result.spv
A llvm/test/Other/spirv-sim/simple.spv
A llvm/test/Other/spirv-sim/simulator-args.spv
A llvm/test/Other/spirv-sim/switch.spv
A llvm/test/Other/spirv-sim/wave-get-lane-index.spv
A llvm/test/Other/spirv-sim/wave-read-lane-first.spv
M llvm/test/lit.cfg.py
A llvm/utils/spirv-sim/instructions.py
A llvm/utils/spirv-sim/spirv-sim.py
Log Message:
-----------
[Utils][SPIR-V] Adding spirv-sim to LLVM (#104020)
Currently, the testing infrastructure for SPIR-V is based on FileCheck.
Those tests are great to check some level of codegen, but when the test
needs check both the CFG layout and the content of each basic-block,
things becomes messy.
- Because the CHECK/CHECK-DAG/CHECK-NEXT state is limited, it is
sometimes hard to catch the good block: if 2 basic blocks have similar
instructions, FileCheck can match the wrong one.
- Cross-lane interaction can be a bit difficult to understand, and
writting a FileCheck test that is strong enough to catch bad CFG
transforms while not being broken everytime some unrelated codegen part
changes is hard.
And lastly, the spirv-val tooling we have checks that the generated
SPIR-V respects the spec, not that it is correct in regards to the
source IR.
For those reasons, I believe the best way to test the structurizer is
to:
- run spirv-val to make sure the CFG respects the spec.
- simulate the function to validate result for each lane, making sure
the generated code is correct.
This simulator has no other dependencies than core python. It also only
supports a very limited set of instructions as we can test most features
through control-flow and some basic cross-lane interactions.
As-is, the added tests are just a harness for the simulator itself. If
this gets merged, the structurizer PR will benefit from this as I'll be
able to add extensive testing using this.
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: d24a2fd38e42f58d6f34f3e985d9387139c12478
https://github.com/llvm/llvm-project/commit/d24a2fd38e42f58d6f34f3e985d9387139c12478
Author: Aditi Medhane <Aditi.Medhane at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
A llvm/test/MachineVerifier/AMDGPU/lit.local.cfg
A llvm/test/MachineVerifier/AMDGPU/register-killed-inside-loop.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_bitcast.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_intrinsic.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_intrinsic_w_side_effects.mir
A llvm/test/MachineVerifier/AMDGPU/undef-should-only-be-set-on-subreg-defs.mir
A llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
A llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-nonentry-block.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-pseudo-terminators.mir
A llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
A llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
A llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
R llvm/test/MachineVerifier/register-killed-inside-loop.mir
R llvm/test/MachineVerifier/test_g_bitcast.mir
R llvm/test/MachineVerifier/test_g_intrinsic.mir
R llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir
R llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir
R llvm/test/MachineVerifier/undef-virt-reg-entry-block.mir
R llvm/test/MachineVerifier/undef-virt-reg-nonentry-block.mir
R llvm/test/MachineVerifier/verifier-ec-subreg-liveness.mir
R llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir
R llvm/test/MachineVerifier/verifier-pseudo-terminators.mir
R llvm/test/MachineVerifier/verify-implicit-def.mir
R llvm/test/MachineVerifier/verify-reg-sequence.mir
R llvm/test/MachineVerifier/writelane_m0.mir
Log Message:
-----------
[AMDGPU] Create dir for amdgpu specific machineverifier tests (#106960)
Move the AMDGPU target specific testcases in MachineVerifier separately
into new directory.
Reference :
https://github.com/llvm/llvm-project/pull/105494#discussion_r1735055750
Commit: 4d8903bd4e6ec29ab28be0d8949c7fde4a740fbe
https://github.com/llvm/llvm-project/commit/4d8903bd4e6ec29ab28be0d8949c7fde4a740fbe
Author: Pablo Antonio Martinez <pablo.antonio.martinez at huawei.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir
Log Message:
-----------
[mlir][vector] Refactor vector-transfer-to-vector-load-store.mlir (NFC) (#105509)
Overview of changes:
- All memref input arguments are re-named to %mem.
- All vector input arguments are re-named to %vec.
- All index input arguments are re-named to %idx.
- All tensor input arguments are re-named to %src/%dst.
- LIT variables were updated to be consistent with input arguments.
- Renamed all output arguments as %res.
- Removed unused argument in `transfer_write_broadcast_unit_dim`.
- Unified identation of `FileCheck` commands.
- Split `transfer_write_permutations` and `transfer_write_broadcast_unit_dim` into tensor and memref variants.
- Renamed `transfer_write_permutations_tensor` as `transfer_write_permutations_tensor_masked`.
Commit: 52b879594fa1e80c871fe227e96443c3c8a8cfc2
https://github.com/llvm/llvm-project/commit/52b879594fa1e80c871fe227e96443c3c8a8cfc2
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
Log Message:
-----------
[LoopUnroll] Avoid undef values in test (NFC)
Avoid most of the code being optimized away as a result of
optimization improvements.
Commit: 8861328303a5b1c45443bbd02338623e41df1da4
https://github.com/llvm/llvm-project/commit/8861328303a5b1c45443bbd02338623e41df1da4
Author: Nathan Gauër <brioche at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
R llvm/test/Other/spirv-sim/branch.spv
R llvm/test/Other/spirv-sim/call.spv
R llvm/test/Other/spirv-sim/constant.spv
R llvm/test/Other/spirv-sim/lit.local.cfg
R llvm/test/Other/spirv-sim/loop.spv
R llvm/test/Other/spirv-sim/simple-bad-result.spv
R llvm/test/Other/spirv-sim/simple.spv
R llvm/test/Other/spirv-sim/simulator-args.spv
R llvm/test/Other/spirv-sim/switch.spv
R llvm/test/Other/spirv-sim/wave-get-lane-index.spv
R llvm/test/Other/spirv-sim/wave-read-lane-first.spv
M llvm/test/lit.cfg.py
R llvm/utils/spirv-sim/instructions.py
R llvm/utils/spirv-sim/spirv-sim.py
Log Message:
-----------
Revert "[Utils][SPIR-V] Adding spirv-sim to LLVM" (#107084)
Reverts llvm/llvm-project#104020
Looks like it caused build failures.
Commit: 5e19e317c0c996b913fddf7f07b6b93285e8dea8
https://github.com/llvm/llvm-project/commit/5e19e317c0c996b913fddf7f07b6b93285e8dea8
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M libcxx/test/benchmarks/format.bench.cpp
M libcxx/test/benchmarks/format_to.bench.cpp
M libcxx/test/benchmarks/format_to_n.bench.cpp
M libcxx/test/benchmarks/formatted_size.bench.cpp
M libcxx/test/benchmarks/formatter_int.bench.cpp
M libcxx/test/benchmarks/lexicographical_compare_three_way.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
M libcxx/test/benchmarks/to_chars.bench.cpp
M libcxx/test/benchmarks/variant_visit_1.bench.cpp
M libcxx/test/benchmarks/variant_visit_2.bench.cpp
M libcxx/test/benchmarks/variant_visit_3.bench.cpp
Log Message:
-----------
[libc++][NFC] Canonicalize the benchmark suite a bit
This replaces `BENCHMARK_TEMPLATE` with `BENCHMARK` and uses
`BENCHMARK_MAIN()` when possible.
Commit: a5f03b4adcd147aeecc0e0d029660c12fb4d2951
https://github.com/llvm/llvm-project/commit/a5f03b4adcd147aeecc0e0d029660c12fb4d2951
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/TestDataFormatterGenericOptional.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/main.cpp
Log Message:
-----------
[lldb] Support "dereferencing" std::optional in `frame var` (#107077)
Commit: 4353530a6fc92c5748a73042371c2ddf487433e7
https://github.com/llvm/llvm-project/commit/4353530a6fc92c5748a73042371c2ddf487433e7
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/unittests/Host/MainLoopTest.cpp
Log Message:
-----------
[lldb/windows] Reset MainLoop events after handling them (#107061)
This prevents the callback function from being called in a busy loop.
Discovered by @slydiman on #106955.
Commit: 3d5e1ec6508c8425601d4cfaba4c8a8f18791e2b
https://github.com/llvm/llvm-project/commit/3d5e1ec6508c8425601d4cfaba4c8a8f18791e2b
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/include/lldb/Host/common/TCPSocket.h
M lldb/source/Host/common/TCPSocket.cpp
M lldb/unittests/Host/SocketTest.cpp
Log Message:
-----------
[lldb] Add a callback version of TCPSocket::Accept (#106955)
The existing function already used the MainLoop class, which allows one
to wait on multiple events at once. It needed to do this in order to
wait for v4 and v6 connections simultaneously. However, since it was
creating its own instance of MainLoop, this meant that it was impossible
to multiplex these sockets with anything else.
This patch simply adds a version of this function which uses an
externally provided main loop instance, which allows the caller to add
any events it deems necessary. The previous function becomes a very thin
wrapper over the new one.
Commit: 0748f4227cd6a4a32b155d4bb9ad3f07e1b54bfe
https://github.com/llvm/llvm-project/commit/0748f4227cd6a4a32b155d4bb9ad3f07e1b54bfe
Author: Him188 <tguan at nvidia.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/AArch64/fabs-fp128.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize 128-bit types for FABS (#104753)
This patch adds a common lower action for `G_FABS`, which generates `and
x8, x8, #0x7fffffffffffffff` to reset the sign bit. The action does not
support vectors since `G_AND` does not support fp128.
This approach is different than what SDAG is doing. SDAG stores the
value onto stack, clears the sign bit in the most significant byte, and
loads the value back into register. This involves multiple memory ops
and sounds slower.
Commit: aa4f81efb99c93da3283ff3178be8db51cd655e2
https://github.com/llvm/llvm-project/commit/aa4f81efb99c93da3283ff3178be8db51cd655e2
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/stack-addr-ps.cpp
Log Message:
-----------
[analyzer] Fix false positive for stack-addr leak on simple param ptr (#107003)
Assigning to a pointer parameter does not leak the stack address because
it stays within the function and is not shared with the caller.
Previous implementation reported any association of a pointer parameter
with a local address, which is too broad.
This fix enforces that the pointer to a stack variable is related by at
least one level of indirection.
CPP-5642
Fixes #106834
Commit: f77f60400f7a4c0c50bc3e3144cdade3bdf9aa3d
https://github.com/llvm/llvm-project/commit/f77f60400f7a4c0c50bc3e3144cdade3bdf9aa3d
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
Log Message:
-----------
[CodeGen] Remove checks that implicit operands are implicit
Commit: 0f5f440f24bc2af4e8ab481a99e03de438b12987
https://github.com/llvm/llvm-project/commit/0f5f440f24bc2af4e8ab481a99e03de438b12987
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
Log Message:
-----------
[clang][bytecode] Pass FPOptions to floating point ops (#107063)
So we don't have to retrieve them from the InterpFrame, which is slow.
Commit: c80cabfcbe88d2f67372bba982eadf45330a5e1b
https://github.com/llvm/llvm-project/commit/c80cabfcbe88d2f67372bba982eadf45330a5e1b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/SCCP/widening.ll
Log Message:
-----------
[SCCP] Avoid use of undef value in test (NFC)
Avoid optimization away most of the code if we resolve this to
a specific value.
Commit: 1a0cf245ac86c2f35c89cab47f83e9b474032e41
https://github.com/llvm/llvm-project/commit/1a0cf245ac86c2f35c89cab47f83e9b474032e41
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/plugins-nextgen/host/CMakeLists.txt
M offload/test/api/is_initial_device.c
M offload/test/lit.cfg
M offload/test/mapping/declare_mapper_nested_default_mappers_array.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_array_subscript.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_complex_structure.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_ptr_subscript.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_var.cpp
M offload/test/mapping/map_both_pointer_pointee.c
M offload/test/mapping/target_pointers_members_map.cpp
M offload/test/offloading/CUDA/basic_launch.cu
M offload/test/offloading/CUDA/basic_launch_blocks_and_threads.cu
M offload/test/offloading/CUDA/basic_launch_multi_arg.cu
M offload/test/offloading/CUDA/launch_tu.cu
M offload/test/offloading/dynamic-schedule-non-spmd.cpp
M offload/test/offloading/dynamic-schedule.cpp
M offload/test/offloading/fortran/dtype-array-constant-index-map.f90
M offload/test/offloading/fortran/dump_map_tables.f90
M offload/test/offloading/fortran/target-depend.f90
M offload/test/offloading/fortran/target-map-all-common-block-members.f90
M offload/test/offloading/fortran/target-map-common-block.f90
M offload/test/offloading/fortran/target-map-declare-target-link-common-block.f90
M offload/test/offloading/fortran/target-map-first-common-block-member.f90
M offload/test/offloading/fortran/target-map-mix-imp-exp-common-block-members.f90
M offload/test/offloading/fortran/target-map-second-common-block-member.f90
M offload/test/offloading/high_trip_count_block_limit.cpp
M offload/test/offloading/schedule.c
M offload/test/sanitizer/double_free.c
M offload/test/sanitizer/double_free_racy.c
M offload/test/sanitizer/free_host_ptr.c
M offload/test/sanitizer/free_wrong_ptr_kind.c
M offload/test/sanitizer/free_wrong_ptr_kind.cpp
M offload/test/sanitizer/kernel_crash.c
M offload/test/sanitizer/kernel_crash_async.c
M offload/test/sanitizer/kernel_crash_many.c
M offload/test/sanitizer/kernel_crash_single.c
M offload/test/sanitizer/kernel_trap.c
M offload/test/sanitizer/kernel_trap.cpp
M offload/test/sanitizer/kernel_trap_async.c
M offload/test/sanitizer/kernel_trap_many.c
M offload/test/sanitizer/ptr_outside_alloc_1.c
M offload/test/sanitizer/ptr_outside_alloc_2.c
M offload/test/sanitizer/use_after_free_1.c
M offload/test/sanitizer/use_after_free_2.c
Log Message:
-----------
[Offload] Change x86_64-pc-linux to x86_64-unknown-linux (#107023)
It appears that the RUNTIMES build prefers the x86-64-unknown-linux-gnu
triple notation for the host. This fixes runtime / test breakages when
compiler-rt is used as the CLANG_DEFAULT_RTLIB.
Commit: 70a19adbc60c738903bbbb8e6d5ef2d41b681089
https://github.com/llvm/llvm-project/commit/70a19adbc60c738903bbbb8e6d5ef2d41b681089
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformFuchsia.c
M compiler-rt/test/profile/ContinuousSyncMode/runtime-counter-relocation.c
M compiler-rt/test/profile/ContinuousSyncMode/set-file-object.c
Log Message:
-----------
[profile] Change __llvm_profile_counter_bias etc. types to match llvm (#102747)
As detailed in Issue #101667, two `profile` tests `FAIL` on 32-bit
SPARC, both Linux/sparc64 and Solaris/sparcv9 (where the tests work when
enabled):
```
Profile-sparc :: ContinuousSyncMode/runtime-counter-relocation.c
Profile-sparc :: ContinuousSyncMode/set-file-object.c
```
The Solaris linker provides the crucial clue as to what's wrong:
```
ld: warning: symbol '__llvm_profile_counter_bias' has differing sizes:
(file runtime-counter-relocation-17ff25.o value=0x8; file libclang_rt.profile-sparc.a(InstrProfilingFile.c.o) value=0x4);
runtime-counter-relocation-17ff25.o definition taken
```
In fact, the types in `llvm` and `compiler-rt` differ:
- `__llvm_profile_counter_bias`/`INSTR_PROF_PROFILE_COUNTER_BIAS_VAR` is
created in `llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp`
(`InstrLowerer::getCounterAddress`) as `int64_t`, while
`compiler-rt/lib/profile/InstrProfilingFile.c` uses `intptr_t`. While
this doesn't matter in the 64-bit case, the type sizes differ for
32-bit.
- `__llvm_profile_bitmap_bias`/`INSTR_PROF_PROFILE_BITMAP_BIAS_VAR` has
the same issue: created in `InstrProfiling.cpp`
(`InstrLowerer::getBitmapAddress`) as `int64_t`, while
`InstrProfilingFile.c` again uses `intptr_t`.
This patch changes the `compiler-rt` types to match `llvm`. At the same
time, the affected testcases are enabled on Solaris, too, where they now
just `PASS`.
Tested on `sparc64-unknown-linux-gnu`, `sparcv9-sun-solaris2.11`,
`x86_64-pc-linux-gnu`, and `amd64-pc-solaris2.11.
Commit: f381cd069965dabfeb277f30a4e532d7fd498f6e
https://github.com/llvm/llvm-project/commit/f381cd069965dabfeb277f30a4e532d7fd498f6e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/minbw-user-non-sizable.ll
Log Message:
-----------
[SLP]Fix PR107036: Check if the type of the user is sizable before requesting its size.
Only some instructions should be considered as potentially reducing the
size of the operands types, not all instructions should be considered.
Fixes https://github.com/llvm/llvm-project/issues/107036
Commit: 0797c184c636889f2897746dc71390ae28005c7c
https://github.com/llvm/llvm-project/commit/0797c184c636889f2897746dc71390ae28005c7c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
Log Message:
-----------
[SCCP] Explicitly mark gep as overdefined if ct eval fails
Don't just leave the result as unknown. I think this currently
works out thanks to undef resolution, but the correct thing to
do is set it to overdefined explicitly.
Commit: dd94537b40cfb8c480df27c08fc715ce91ba4089
https://github.com/llvm/llvm-project/commit/dd94537b40cfb8c480df27c08fc715ce91ba4089
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
Log Message:
-----------
[LV] Update call widening decision when scalarzing calls.
collectInstsToScalarize may decide to scalarize a call. If so, we have
to update the widening decision for the call, otherwise the call won't
be scalarized as expected during VPlan construction.
This issue was uncovered by f82543d509.
Commit: b74e09cb20e6218320013b54c9ba2f5c069d44b9
https://github.com/llvm/llvm-project/commit/b74e09cb20e6218320013b54c9ba2f5c069d44b9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/RISCV/unique-loads-insert-non-power-of-2.ll
Log Message:
-----------
[SLP]Check for the whole vector vectorization in unique scalars analysis
Need to check that thr whole number of register is attempted to
vectorize before actually trying to build the node to avoid compiler
crash.
Commit: ce8ec31298d5fbd81712af0f6bc34dae87f7f30c
https://github.com/llvm/llvm-project/commit/ce8ec31298d5fbd81712af0f6bc34dae87f7f30c
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/revec-shufflevector.ll
Log Message:
-----------
[SLP][REVEC] Support more mask pattern usage in shufflevector. (#106212)
Commit: a424b792053a48ef7e00636f28f3cc8faa23d637
https://github.com/llvm/llvm-project/commit/a424b792053a48ef7e00636f28f3cc8faa23d637
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_context.cpp
M compiler-rt/lib/rtsan/rtsan_context.h
M compiler-rt/lib/rtsan/rtsan_stack.cpp
M compiler-rt/lib/rtsan/rtsan_stack.h
M compiler-rt/test/rtsan/basic.cpp
Log Message:
-----------
[compiler-rt][rtsan] Record pc and bp higher up in the stack (#107014)
Functionally, this change affects only our printed stack traces. New
version does not expose any internal rtsan interworking
Commit: 20fa37bbfabca512b16a8497eb671a3bd4b5b96b
https://github.com/llvm/llvm-project/commit/20fa37bbfabca512b16a8497eb671a3bd4b5b96b
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[Vectorize] Fix -Wunused-variable in SLPVectorizer.cpp (NFC)
/llvm-project/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:10310:26:
error: unused variable 'isExtractSubvectorMask' [-Werror,-Wunused-variable]
bool isExtractSubvectorMask =
^
1 error generated.
Commit: d7c44eff42f7c05d364e4a00048c534a30cea24b
https://github.com/llvm/llvm-project/commit/d7c44eff42f7c05d364e4a00048c534a30cea24b
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/revec.ll
Log Message:
-----------
[SLP][REVEC] Update test. NFC.
Commit: 7852ebc088b925ef1c1940cbd56a93d9f8e3e330
https://github.com/llvm/llvm-project/commit/7852ebc088b925ef1c1940cbd56a93d9f8e3e330
Author: yonghong-song <yhs at fb.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/BPF.cpp
M clang/test/Preprocessor/bpf-predefined-macros.c
M llvm/lib/Target/BPF/BPFSubtarget.cpp
M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-3.ll
M llvm/test/CodeGen/BPF/CORE/no-narrow-load.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp2.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp3.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp4.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp5.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp6.ll
M llvm/test/CodeGen/BPF/adjust-opt-speculative1.ll
M llvm/test/CodeGen/BPF/adjust-opt-speculative2.ll
M llvm/test/CodeGen/BPF/alu8.ll
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/basictest.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
M llvm/test/CodeGen/BPF/cc_args.ll
M llvm/test/CodeGen/BPF/cc_args_be.ll
M llvm/test/CodeGen/BPF/cc_ret.ll
M llvm/test/CodeGen/BPF/cmp.ll
M llvm/test/CodeGen/BPF/cttz-ctlz.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/fi_ri.ll
M llvm/test/CodeGen/BPF/i128.ll
M llvm/test/CodeGen/BPF/intrinsics.ll
M llvm/test/CodeGen/BPF/load.ll
M llvm/test/CodeGen/BPF/loops.ll
M llvm/test/CodeGen/BPF/many_args1.ll
M llvm/test/CodeGen/BPF/objdump_atomics.ll
M llvm/test/CodeGen/BPF/objdump_cond_op.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/BPF/objdump_imm_hex.ll
M llvm/test/CodeGen/BPF/objdump_intrinsics.ll
M llvm/test/CodeGen/BPF/objdump_nop.ll
M llvm/test/CodeGen/BPF/objdump_static_var.ll
M llvm/test/CodeGen/BPF/objdump_trivial.ll
M llvm/test/CodeGen/BPF/pr57872.ll
M llvm/test/CodeGen/BPF/reloc-2.ll
M llvm/test/CodeGen/BPF/remove_truncate_1.ll
M llvm/test/CodeGen/BPF/remove_truncate_2.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/remove_truncate_6.ll
M llvm/test/CodeGen/BPF/remove_truncate_8.ll
M llvm/test/CodeGen/BPF/rodata_1.ll
M llvm/test/CodeGen/BPF/rodata_2.ll
M llvm/test/CodeGen/BPF/rodata_3.ll
M llvm/test/CodeGen/BPF/rodata_4.ll
M llvm/test/CodeGen/BPF/rodata_6.ll
M llvm/test/CodeGen/BPF/rodata_7.ll
M llvm/test/CodeGen/BPF/sanity.ll
M llvm/test/CodeGen/BPF/setcc.ll
M llvm/test/CodeGen/BPF/shifts.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/undef.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/tools/llvm-objdump/BPF/interleaved-source-test.ll
Log Message:
-----------
[BPF] Make -mcpu=v3 as the default (#107008)
Before llvm20, (void)__sync_fetch_and_add(...) always generates locked
xadd insns. In linux kernel upstream discussion [1], it is found that
for arm64 architecture, the original semantics of
(void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is
preferred in order for jit to emit proper native barrier insns.
In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will
generate the following insns:
- for cpu v1/v2: locked xadd insns to keep backward compatibility
- for cpu v3/v4: __atomic_fetch_add() insns
To ensure proper barrier semantics for (void)__sync_fetch_and_add(...),
cpu v3/v4 is recommended.
This patch enables cpu=v3 as the default cpu version. For users wanting
to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc
command line.
[1]
https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f
[2] https://github.com/llvm/llvm-project/pull/101428
[3] https://github.com/llvm/llvm-project/pull/106494
Commit: f70ccdaeb4ef9681ea490ea7779efbe72e643eda
https://github.com/llvm/llvm-project/commit/f70ccdaeb4ef9681ea490ea7779efbe72e643eda
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode][NFC] Move Call ops into Interp.cpp (#107104)
They are quite long and not templated.
Commit: df159d3cf8e681f8d225bd0b4ed0cbd97b16c588
https://github.com/llvm/llvm-project/commit/df159d3cf8e681f8d225bd0b4ed0cbd97b16c588
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
Log Message:
-----------
[GISEL][AArch64][NFC] Stop using wip_match_opcode for some opcodes (#106702)
This patch moves to the new style of writing
pattern for matching opcodes and thus deprecates using wip_match_opcoee.
It moves G_FCONSTANT, G_ICMP, G_STORE, and G_OR.
Commit: 05f5a91d00b02f4369f46d076411c700755ae041
https://github.com/llvm/llvm-project/commit/05f5a91d00b02f4369f46d076411c700755ae041
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/sink-foldable.ll
Log Message:
-----------
LICM: use IRBuilder in hoist BO assoc (#106978)
Use IRBuilder when creating the new invariant instruction, so that the
constant-folder has an opportunity to constant-fold the new Instruction
that we desire to create.
Commit: fedc7556ad5237cd11e29b8e70d412bdc39a4fa6
https://github.com/llvm/llvm-project/commit/fedc7556ad5237cd11e29b8e70d412bdc39a4fa6
Author: Nick Sarnie <sarnex at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/LTO/LTO.cpp
Log Message:
-----------
[ThinLTO] Don't always print ModulesToCompile debugging information (#106769)
Nothing went wrong in this case, we just successfully matched a module
by identifier. No need to print to std::error like we would for
something that should be user-visible.
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 3b6e255c8339b0945f5f55757ee193fe23b47e2c
https://github.com/llvm/llvm-project/commit/3b6e255c8339b0945f5f55757ee193fe23b47e2c
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/LICM/update-scev-after-hoist.ll
Log Message:
-----------
LICM/test: regen a test with UTC (NFC) (#107117)
Commit: b7017ef44827314758ba32c97eacb2d3f08c18e6
https://github.com/llvm/llvm-project/commit/b7017ef44827314758ba32c97eacb2d3f08c18e6
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV] Rename sf_vcix_state to sf.vcix_state. NFC (#107115)
This PR: https://github.com/llvm/llvm-project/pull/106995 names the
vendor CSR in a wrong way, it should be `sf.` rather than `sf_` for
prefix.
Commit: e1bde1c5b203224b0fa68ee141ec2c7a079f5eac
https://github.com/llvm/llvm-project/commit/e1bde1c5b203224b0fa68ee141ec2c7a079f5eac
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SDAG] Fix a typo in comment
Commit: 2a9f93bf13c717af3fe06bc226047f96b3f9c21a
https://github.com/llvm/llvm-project/commit/2a9f93bf13c717af3fe06bc226047f96b3f9c21a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/MC/RISCV/fp-default-rounding-mode.s
M llvm/test/MC/RISCV/rv32zfbfmin-valid.s
Log Message:
-----------
[RISCV] Use RNE rounding mode for fcvt.s.bf16. Don't print the rounding mode if RNE. (#106948)
The rounding mode has no effect on the instruction behavior. Using RNE
matches what we do for fcvt.s.h, fcvt.d.f, fcvt.d.h which are similarily
not affected by the rounding mode.
This appears to match the behavior of binutils. According to compiler
explore, objdump is unable to disassembler fcvt.s.bf16 with a non-zero
rounding mode.
Commit: 59a3b4156836c3ea8589d7a39e7b4712fc8698ec
https://github.com/llvm/llvm-project/commit/59a3b4156836c3ea8589d7a39e7b4712fc8698ec
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M llvm/include/llvm/ADT/DenseMap.h
M mlir/lib/Transforms/SROA.cpp
Log Message:
-----------
[ADT] Deprecate DenseMap::getOrInsertDefault (#107040)
This patch deprecates DenseMap::getOrInsertDefault in favor of
DenseMap::operator[], which does the same thing, has been around
longer, and is also a household name as part of std::map and
std::unordered_map.
Note that DenseMap provides several equivalent ways to insert or
default-construct a key-value pair:
- operator[Key]
- try_emplace(Key).first->second
- getOrInsertDefault(Key)
- FindAndConstruct(Key).second
Commit: 86835d2d5a24ed00ed3747b77029c896ba935036
https://github.com/llvm/llvm-project/commit/86835d2d5a24ed00ed3747b77029c896ba935036
Author: Daniel Grumberg <dgrumberg at apple.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
Log Message:
-----------
[clang][ExtractAPI] Remove erroneous module name check in MacroCallbacks (#107059)
rdar://135044923
Commit: 93857afc24abeeacdd58277b4ab32d38daa1e531
https://github.com/llvm/llvm-project/commit/93857afc24abeeacdd58277b4ab32d38daa1e531
Author: Christian Sigg <csigg at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/unittests/Driver/SimpleDiagnosticConsumer.h
Log Message:
-----------
[clang][Driver] Add missing include after 26bf0b4ae7df7f5350f71afd40a57cdf8f98c588.
https://github.com/llvm/llvm-project/commit/26bf0b4ae7df7f5350f71afd40a57cdf8f98c588
Commit: 903d1c6ee5de4ee87c1737906c264e219c05d4cb
https://github.com/llvm/llvm-project/commit/903d1c6ee5de4ee87c1737906c264e219c05d4cb
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/tools/driver/CMakeLists.txt
M libclc/CMakeLists.txt
M llvm/tools/llvm-as/CMakeLists.txt
M llvm/tools/llvm-link/CMakeLists.txt
M llvm/tools/opt/CMakeLists.txt
Log Message:
-----------
[libclc] More cross compilation fixes (#97811)
* Move the setup_host_tool calls to the directories of their tool.
Although it works to call it in libclc, it can only appear in a single
location so it fails the "what if everyone did this?" test and causes
problems for downstream code that also wants to use native versions of
these tools from other projects.
* Correct the TARGET "${${tool}_target}" check. "${${tool}_target}" may
be set to the path to the executable, which works in dependencies but
cannot be tested using if(TARGET). For lack of a better alternative,
just check that "${${tool}_target}" is non-empty and trust that if it
is, it is set to a meaningful value. If somehow it turns out to be a
valid target, its value will still show up in error messages anyway.
* Account for llvm-spirv possibly being provided in-tree. Per
https://github.com/KhronosGroup/SPIRV-LLVM-Translator?tab=readme-ov-file#llvm-in-tree-build
it is possible to drop llvm-spirv into LLVM and have it built as part of
LLVM's build. In this configuration, cross builds of LLVM require a
native version of llvm-spirv to be built.
Commit: f1ef67ded5371ddeb0ee72ea435f61f58c9127c6
https://github.com/llvm/llvm-project/commit/f1ef67ded5371ddeb0ee72ea435f61f58c9127c6
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-binop.ll
M llvm/test/Transforms/LICM/update-scev-after-hoist.ll
Log Message:
-----------
LICM: extend hoist BO assoc to mul case (#106991)
Trivially extend hoistBOAssociation to also handle the BinaryOperator
Mul.
Alive2 proofs: https://alive2.llvm.org/ce/z/zjtR5g
Commit: 4da0aa382a706b002504134d38385e377bf20c89
https://github.com/llvm/llvm-project/commit/4da0aa382a706b002504134d38385e377bf20c89
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/lld/test/BUILD.gn
Log Message:
-----------
[gn build] Add missing llvm-strings dependency to check-lld (#106896)
This has been required by `lld/test/ELF/zsectionheader.s` since it was
added in 5d972c58.
Commit: df4746d1d076016095059da4af2a3c3cc54657fe
https://github.com/llvm/llvm-project/commit/df4746d1d076016095059da4af2a3c3cc54657fe
Author: Christian Sigg <csigg at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Change cache-silo-key to fix blob fetch issue.
Bazel builds currently fail with `Failed to fetch blobs because they do not exist remotely.`.
Set a cache-silo-key to start a new cache.
Commit: 2c7786e94a1058bd4f96794a1d4f70dcb86e5cc5
https://github.com/llvm/llvm-project/commit/2c7786e94a1058bd4f96794a1d4f70dcb86e5cc5
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/sphinx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelements-vector-ops-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Log Message:
-----------
Prefer use of 0.0 over -0.0 for fadd reductions w/nsz (in IR) (#106770)
This is a follow up to 924907bc6, and is mostly motivated by consistency
but does include one additional optimization. In general, we prefer 0.0
over -0.0 as the identity value for an fadd. We use that value in
several places, but don't in others. So, let's be consistent and use the
same identity (when nsz allows) everywhere.
This creates a bunch of test churn, but due to 924907bc6, most of that
churn doesn't actually indicate a change in codegen. The exception is
that this change enables the use of 0.0 for nsz, but *not* reasoc, fadd
reductions. Or said differently, it allows the neutral value of an
ordered fadd reduction to be 0.0.
Commit: 8e4b8155c1b80a68fcf854c305f06602b37da218
https://github.com/llvm/llvm-project/commit/8e4b8155c1b80a68fcf854c305f06602b37da218
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/CodeGen/M68k/pipeline.ll
Log Message:
-----------
[M68k] Fix compilation pipeline check
- After 'RemoveLoadsIntoFakeUses' is enabled to support llvm.fake.use
Commit: 9626e84faeaab200665bae9694458c2beb3d49c7
https://github.com/llvm/llvm-project/commit/9626e84faeaab200665bae9694458c2beb3d49c7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode][NFC] Simplify builtin-functions.cpp (#107118)
The effect is the same, but this version doesn't take as long to
evaluate.
Commit: 0b2f2537a5b717539b200bd7fa31cbc24679e96f
https://github.com/llvm/llvm-project/commit/0b2f2537a5b717539b200bd7fa31cbc24679e96f
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[LV] Separate AnyOf recurrence from getRecurrenceIdentity [NFC]
These recurrence types don't have a meaningful identity, and the
routine was abused to return the start value instead. Out of the
three callers to this routine, only one actually wants this
behavior. This is a prep change for removing the routine entirely
and commoning it with other copies of the same logic.
Commit: a8e1c6f99abc273677afed5eaaeee2c0296db59f
https://github.com/llvm/llvm-project/commit/a8e1c6f99abc273677afed5eaaeee2c0296db59f
Author: Giuseppe Rossini <giuseppe.rossini at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
A mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx12.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[MLIR][AMDGPU] Add support for fp8 ops on gfx12 (#106388)
This PR is adding support for `fp8` and `bfp8` on gfx12
Commit: ebdadcfeb9c63f56703bf47dfeb6aff5a66ddfa1
https://github.com/llvm/llvm-project/commit/ebdadcfeb9c63f56703bf47dfeb6aff5a66ddfa1
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchEmpty.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
M llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll
M llvm/test/CodeGen/SPIRV/transcoding/GlobalFunAnnotate.ll
Log Message:
-----------
[SPIR-V] Improve correctness of emitted MIR between passes for branching instructions (#106966)
This PR improves correctness of emitted MIR between passes for branching
instructions and thus increase number of passing tests when expensive
checks are on. Specifically, we address here such issues with machine
verifier as:
* fix switch generation: generate correct successors and undo the
"address taken" status to reflect that a successor doesn't actually
correspond to an IR-level basic block;
* fix incorrect definition of OpBranch and OpBranchConditional in
TableGen (SPIRVInstrInfo.td) to set isBarrier status properly and set a
correct type of virtual registers;
* fix a case when Phi refers to a type definition that goes after the
Phi instruction, so that the virtual register definition of the type
doesn't dominate all uses.
This PR decrease number of failing tests under expensive checks from 56
to 50.
Commit: 4f403e88f260cd1df3633fbcbe8fa8d1c8e0a745
https://github.com/llvm/llvm-project/commit/4f403e88f260cd1df3633fbcbe8fa8d1c8e0a745
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/debug-info/no-misplaced-opextinst.ll
Log Message:
-----------
[SPIR-V] Ensure that OpExtInst instructions generated by NonSemantic_Shader_DebugInfo_100 are not mixed up with other OpExtInst instructions (#107007)
This PR is to ensure that OpExtInst instructions generated by
NonSemantic_Shader_DebugInfo_100 are not mixed up with other OpExtInst
instructions.
Original implementation
(https://github.com/llvm/llvm-project/pull/97558) has introduced an
issue by moving OpExtInst instruction with the 3rd operand equal to
DebugSource (value 35) or DebugCompilationUnit (value 1) even if
OpExtInst is not generated by NonSemantic_Shader_DebugInfo_100
implementation code.
The reproducer is attached as a new test case. The code of the test case
reproduces the issue, because "lgamma" has the same code (35) inside
OpenCL_std as DebugSource inside NonSemantic_Shader_DebugInfo_100.
Commit: e89bcfc0e86cd4952c03fdf920d11c598ae6e16a
https://github.com/llvm/llvm-project/commit/e89bcfc0e86cd4952c03fdf920d11c598ae6e16a
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
Log Message:
-----------
[SandboxIR] Add tracking for ShuffleVectorInst::commute. (#106644)
Track it as an operand swap + a `setShuffleMask` and delegate to the
`llvm::ShuffleVectorInst` implementation.
Commit: fdc1b5d290edfefe93c2bf0582e8e4363bda63ee
https://github.com/llvm/llvm-project/commit/fdc1b5d290edfefe93c2bf0582e8e4363bda63ee
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/tools/opt/NewPMDriver.cpp
M llvm/tools/opt/NewPMDriver.h
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
[NFC][opt] Rename VerifierKind enums (#106789)
Make into enum class.
Output really should be InputOutput since it also verifies the input IR.
Commit: 46407366166dc84c95075cf273acc005605967fe
https://github.com/llvm/llvm-project/commit/46407366166dc84c95075cf273acc005605967fe
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M libcxx/modules/std/type_traits.inc
Log Message:
-----------
[libc++] Add missing `std::is_virtual_base_of` to `type_traits.inc` (#107009)
std::is_virtual_base_of was implemented in https://github.com/llvm/llvm-project/pull/105847
Commit: 26a4edf655aac138ef4f8cebf865d34b9ab4ff2d
https://github.com/llvm/llvm-project/commit/26a4edf655aac138ef4f8cebf865d34b9ab4ff2d
Author: Petr Hosek <phosek at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M cmake/Modules/HandleCompilerRT.cmake
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
Log Message:
-----------
[CMake][compiler-rt] Support for using compiler-rt atomic library (#106603)
Not every toolchain provides and want to use libatomic which is a part
of GCC, some toolchains may opt into using compiler-rt atomic library.
Commit: b91b1f0bd38c8e5d8f7eb30413ec799581e3d46e
https://github.com/llvm/llvm-project/commit/b91b1f0bd38c8e5d8f7eb30413ec799581e3d46e
Author: vporpo <vporpodas at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[SandboxIR] Implement remaining ConstantInt functions (#106775)
This patch adds the remaining ConstantInt:: functions and it also
implements the IntegerType class.
Commit: fb14f1df54c3e4edaaf3aa34268147f4da11d3b4
https://github.com/llvm/llvm-project/commit/fb14f1df54c3e4edaaf3aa34268147f4da11d3b4
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/CodeGen/pgo-force-function-attrs.ll
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Instrumentation/PGOForceFunctionAttrs/basic.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
Log Message:
-----------
[PGO][Pipeline] Enable PGOForceFunctionAttrs in PGO optimization pipelines (#106790)
Remove flag that turns on the PGOForceFunctionAttrs pass and always add
it to default pipelines when using PGO.
This is NFC by default since PGOOpt->ColdOptType is by default
ColdFuncOpt::Default.
Remove -O2 RUN line in basic.ll since we now have the pipeline tests.
Commit: 42f5277de16cd7fad01285ade9004675b8253ced
https://github.com/llvm/llvm-project/commit/42f5277de16cd7fad01285ade9004675b8253ced
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M libcxx/include/__config
M libcxx/include/__type_traits/datasizeof.h
M libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp
Log Message:
-----------
[libc++] Fix __datasizeof_v for Clang17 and 18 in C++03 (#106832)
This also disables the use of `__datasizeof`, since it's currently
broken for empty types.
Commit: 24b6b82487f15dd9d6cbe8a716dd13a6808a2528
https://github.com/llvm/llvm-project/commit/24b6b82487f15dd9d6cbe8a716dd13a6808a2528
Author: Damyan Pepper <damyanp at microsoft.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
Log Message:
-----------
[NFC] Add llvm_unreachable to getRCPrefix (#106822)
Commit: 884d7c137a587fdd7549bd8a26f887bbeda0cc86
https://github.com/llvm/llvm-project/commit/884d7c137a587fdd7549bd8a26f887bbeda0cc86
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
R llvm/test/Transforms/SLPVectorizer/RISCV/unique-loads-insert-non-power-of-2.ll
Log Message:
-----------
Revert "[SLP]Check for the whole vector vectorization in unique scalars analysis"
This reverts commit b74e09cb20e6218320013b54c9ba2f5c069d44b9 after
post-commit review. The number of parts is calculated incorrectly.
Commit: 571c8c2c88122d318ed84cd9e948613e3f1aac5f
https://github.com/llvm/llvm-project/commit/571c8c2c88122d318ed84cd9e948613e3f1aac5f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
Log Message:
-----------
Revert "[SLP]Initial support for non-power-of-2 (but still whole register) number of elements in operands."
This reverts commit a3ea90ffbbe47d9a1b3eab03324f09d7b8e0dcb3 after the
post commit review. The number of parts is calculated incorrectly.
Commit: 126940bde3e48ad9bf0a6966fc473e22d4dade7d
https://github.com/llvm/llvm-project/commit/126940bde3e48ad9bf0a6966fc473e22d4dade7d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] Use DenseMap::{find,try_emplace} (NFC) (#107123)
I'm planning to deprecate and eventually remove
DenseMap::FindAndConstruct in favor of operator[].
Commit: 15fa3ba547bc3ee04af5c32b8f723a97e3feefd8
https://github.com/llvm/llvm-project/commit/15fa3ba547bc3ee04af5c32b8f723a97e3feefd8
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M bolt/lib/Profile/YAMLProfileReader.cpp
A bolt/test/X86/yaml-unknown-keys.test
M bolt/tools/merge-fdata/merge-fdata.cpp
Log Message:
-----------
[BOLT][YAML] Allow unknown keys in the input (#100824)
This ensures forward compatibility, where old BOLT versions can consume
the profile created by newer versions with extra keys.
Test Plan: added yaml-unknown-keys.test
Commit: eec1fac9b51d06c8afafe9952a20ba7cd4c3ce1c
https://github.com/llvm/llvm-project/commit/eec1fac9b51d06c8afafe9952a20ba7cd4c3ce1c
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
Log Message:
-----------
[Clang] Fix handling of placeholder variables name in init captures (#107055)
We were incorrectly not deduplicating results when looking up `_` which,
for a lambda init capture, would result in an ambiguous lookup.
The same bug caused some diagnostic notes to be emitted twice.
Fixes #107024
Commit: 1fbb6b4efc9e9d257f0f7e5065f40f9b9677ca7c
https://github.com/llvm/llvm-project/commit/1fbb6b4efc9e9d257f0f7e5065f40f9b9677ca7c
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
Log Message:
-----------
[LV] Prefer FLT_MIN/MAX for fmin/fmax reductions with ninf (#107141)
Analogous to 2c7786e94a1058bd4f96794a1d4f70dcb86e5cc5, cleanup a case
where the vectorizer is emitting a non-canonical identity value given
the available flags. We use largest/smallest value during ISEL, and VP
expansion, but not during vectorization.
Since the fmin/fmax/fminimum/fmaximum intrinsics don't require a start
value, this difference is only visible when masking of inactive lanes is
required.
Primary motivation of this change is simply to remove a difference
between version of code which reason about the identity value of a
reduction so I can kill all but one off.
In review, it was pointed out that this is actually a functional fix as well.
The old code used inf on a noinf reduction instruction - whose
result is poison! That wasn't the intent of the code.
Commit: 451a3135a7afece0b6e7605376ce208435605934
https://github.com/llvm/llvm-project/commit/451a3135a7afece0b6e7605376ce208435605934
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/DominanceFrontier.h
M llvm/include/llvm/Analysis/DominanceFrontierImpl.h
M llvm/include/llvm/CodeGen/MachineDominanceFrontier.h
Log Message:
-----------
[DominanceFrontier] Remove unused functions (#106913)
Commit: eb05e8fde1ebc4cda2106b1236620a8a89b36b7c
https://github.com/llvm/llvm-project/commit/eb05e8fde1ebc4cda2106b1236620a8a89b36b7c
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/www/c_status.html
Log Message:
-----------
[clang] [docs] Clarify the issue with compiler-rt on Windows/MSVC (#106875)
Compiler-rt does support Windows just fine, even if outdated docs pages
didn't list it as one of the supported OSes, this is being rectified in
https://github.com/llvm/llvm-project/pull/106874.
MinGW is another environment configuration on Windows, where compiler-rt
or libgcc is linked in automatically, so there's no issue with having
such builtins functions available.
For MSVC style environments, compiler-rt builtins do work just fine, but
Clang doesn't automatically link them in. See e.g.
https://discourse.llvm.org/t/improve-autolinking-of-compiler-rt-and-libc-on-windows-with-lld-link/71392
for a discussion on how to improve this situation. But none of that
issue is that compiler-rt itself wouldn't support Windows.
Commit: fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10
https://github.com/llvm/llvm-project/commit/fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] Don't add DWARF debug info when assembling .s with clang-cl /Z7 (#106686)
This fixes a regression from f58330cbe44598eb2de0cca3b812f67fea0a71ca.
That commit changed the clang-cl options /Zi and /Z7 to be implemented
as aliases of -g rather than having separate handling.
This had the unintended effect, that when assembling .s files with
clang-cl, the /Z7 option (which implies using CodeView debug info) was
treated as a -g option, which causes `ClangAs::ConstructJob` to pick up
the option as part of `Args.getLastArg(options::OPT_g_Group)`, which
sets the `WantDebug` variable.
Within `Clang::ConstructJob`, we check for whether explicit `-gdwarf` or
`-gcodeview` options have been set, and if not, we pick the default
debug format for the current toolchain. However, in `ClangAs`, if debug
info has been enabled, it always adds DWARF debug info.
Add similar logic in `ClangAs` - check if the user has explicitly
requested either DWARF or CodeView, otherwise look up the toolchain
default. If we (either implicitly or explicitly) should be producing
CodeView, don't enable the default `ClangAs` DWARF generation.
This fixes the issue, where assembling a single `.s` file with clang-cl,
with the /Z7 option, causes the file to contain some DWARF sections.
This causes the output executable to contain DWARF, in addition to the
separate intended main PDB file.
By having the output executable contain DWARF sections, LLDB only looks
at the (very little) DWARF info in the executable, rather than looking
for a separate standalone PDB file. This caused an issue with LLDB's
tests, https://github.com/llvm/llvm-project/issues/101710.
Commit: 3bd161e98d89d31696002994771b7761f1c74859
https://github.com/llvm/llvm-project/commit/3bd161e98d89d31696002994771b7761f1c74859
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
Log Message:
-----------
[LV] Honor forced scalars in setVectorizedCallDecision.
Similarly to dd94537b4, setVectorizedCallDecision also did not consider
ForcedScalars. This lead to VPlans not reflecting the decision by the
legacy cost model (cost computation would use scalar cost, VPlan would
have VPWidenCallRecipe).
To fix this, check if the call has been forced to scalar in
setVectorizedCallDecision.
Note that this requires moving setVectorizedCallDecision after
collectLoopUniforms (which sets ForcedScalars). collectLoopUniforms does
not depend on call decisions and can safely be moved.
Fixes https://github.com/llvm/llvm-project/issues/107051.
Commit: 70f3511adaea4d3a9f8fadb23e84f518cc0654ab
https://github.com/llvm/llvm-project/commit/70f3511adaea4d3a9f8fadb23e84f518cc0654ab
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] [test] Fix the debug-options-as.c test on macOS
Separate the path, which may begin with e.g. /Users, with "--" from
the other options, to make it clear that it is a path, not an
option.
This fixes a test from fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10.
Commit: ec8e1c623a78536b956cc2c1d42ae75c4024ad66
https://github.com/llvm/llvm-project/commit/ec8e1c623a78536b956cc2c1d42ae75c4024ad66
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
Log Message:
-----------
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
This avoids having isel patterns that emit two instrutions. It also
allows us to remove sext.w and slli+srli pairs by using fcvt.s.w(u) on
RV64.
Commit: 319e8cd201e6744199da377fba237dd276063e49
https://github.com/llvm/llvm-project/commit/319e8cd201e6744199da377fba237dd276063e49
Author: Ian Anderson <iana at apple.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/Sema/SemaAvailability.cpp
M clang/test/FixIt/fixit-availability-maccatalyst.m
M clang/test/FixIt/fixit-availability.mm
Log Message:
-----------
[Clang][Sema] clang generates incorrect fix-its for API_AVAILABLE (#105855)
Apple's API_AVAILABLE macro has its own notion of platform names which
are supported by \_\_API_AVAILABLE_PLATFORM_<name> macros. They don't
follow a consistent naming convention, but there's at least one that
matches a valid availability attribute platform name. Instead of
lowercasing the source spelling name, search for a defined macro and use
that in the fix-it.
Commit: cdab6ffd6d32566277f71d9733e4b21750ea38c8
https://github.com/llvm/llvm-project/commit/cdab6ffd6d32566277f71d9733e4b21750ea38c8
Author: weiguozhi <57237827+weiguozhi at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
Log Message:
-----------
[X86] Don't save/restore fp/bp around terminator (#106462)
In function spillFPBP we already try to skip terminator, but there is a
logic error, so when there is only terminator instruction in the MBB, it
still tries to save/restore fp/bp around it if the terminator clobbers
fp/bp, for example a tail call with ghc calling convention.
Now this patch really skips terminator even if it is the only
instruction in the MBB.
Commit: cbb5f03f5042aa6d7c5d17963eba192861c9165c
https://github.com/llvm/llvm-project/commit/cbb5f03f5042aa6d7c5d17963eba192861c9165c
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] [test] Fix the debug-options-as.c test on PowerPC
Use an explicit MSVC triple with an architecture that does
have proper handling for MSVC style targets.
This fixes a test from fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10.
Commit: 0ef7b1d21ca7ce55f1c8d3ec739e64775572e9cc
https://github.com/llvm/llvm-project/commit/0ef7b1d21ca7ce55f1c8d3ec739e64775572e9cc
Author: Joshua Baehring <98630690+JoshuaMBa at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/secondary.h
Log Message:
-----------
[scudo] Update secondary cache released pages bound. (#106466)
`MaxReleasedCachePages` has been set to 4. Initially, in #105009 , we
set `MaxReleasedCachePages` to 0 so that the partial chunk heuristic
could be introduced incrementally as we observed its impact on retrieval
order and more generally, performance.
Co-authored-by: Joshua Baehring <josh.baehring at yale.edu>
Commit: 334d1238aafa8ca017d433caaf8f6e00f2622111
https://github.com/llvm/llvm-project/commit/334d1238aafa8ca017d433caaf8f6e00f2622111
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
Log Message:
-----------
[HLSL] Adjust resource binding diagnostic flags code (#106657)
Adjust register binding diagnostic flags code in a couple of ways:
- Store the resource class in the Flags struct to avoid duplicated
scanning for HLSLResourceClassAttribute
- Avoid unnecessary indirection when converting resource class to
register type
- Remove recursion and reduce duplicated code
Also fixes a case where struct with an array was incorrectly diagnosed
unfit for `c` register binding.
This will also simplify work that is needed to be done in this area for
llvm/llvm-project#104861.
Commit: dfc21acdfa0eb7f6f6bb563445959fb18ea863da
https://github.com/llvm/llvm-project/commit/dfc21acdfa0eb7f6f6bb563445959fb18ea863da
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] Convert global allocation for pinned variable (#106807)
ALLOCATE/DEALLOCATE statements for module allocatable variable with the
pinned attribute can be lowered to the standard runtime call and do not
need further action since these variables will have a unique descriptor
that is on the host.
Commit: b2dabd2b06cb0ca5ea534bafe33c5cff5521be18
https://github.com/llvm/llvm-project/commit/b2dabd2b06cb0ca5ea534bafe33c5cff5521be18
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[Sema] Fix warnings
This patch fixes:
clang/lib/Sema/SemaHLSL.cpp:838:12: error: unused variable
'TheVarDecl' [-Werror,-Wunused-variable]
clang/lib/Sema/SemaHLSL.cpp:840:19: error: unused variable
'CBufferOrTBuffer' [-Werror,-Wunused-variable]
Commit: d966d4708fe5084e47ca3d9d411935d6870aefff
https://github.com/llvm/llvm-project/commit/d966d4708fe5084e47ca3d9d411935d6870aefff
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/SupportFile.h
Log Message:
-----------
[lldb] Make SupportFile's FileSpec and Checksum const (NFC)
Commit: 98bde7fd872c10e49035d5dc5d2f2b44489f6a07
https://github.com/llvm/llvm-project/commit/98bde7fd872c10e49035d5dc5d2f2b44489f6a07
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Symbol/LineTable.cpp
Log Message:
-----------
[lldb] Avoid FileSpec indirection where we can use SupportFiles directly
Now that more parts of LLDB know about SupportFiles, avoid going through
FileSpec (and losing the Checksum in the process). Instead, use the
SupportFile directly.
Commit: 53d3d1ab9abf28e92a27fce0a99ae83720d27d75
https://github.com/llvm/llvm-project/commit/53d3d1ab9abf28e92a27fce0a99ae83720d27d75
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] Avoid two successive hash lookups on the same key (#107143)
This patch replaces the find-try_emplace sequence with just one call
to try_emplace, thereby avoiding two successive hash lookups on the
same key. I am not using the "inserted" boolean from try_emplace to
preserve the original behavior (that is, before PR 107123) that checks
to see if the value is nullptr or not.
Commit: db8ca88f578c2270ab2d461fa0dd5e7a1d1bad43
https://github.com/llvm/llvm-project/commit/db8ca88f578c2270ab2d461fa0dd5e7a1d1bad43
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/utils/TableGen/VTEmitter.cpp
Log Message:
-----------
[TableGen] Print all arguments to GET_VT_ATTR in the comment in GenVT.inc. NFC
Commit: 18cf14efe3e82b2343817fd174bcac48244c8f50
https://github.com/llvm/llvm-project/commit/18cf14efe3e82b2343817fd174bcac48244c8f50
Author: Scott Linder <Scott.Linder at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/docs/conf.py
M llvm/docs/conf.py
Log Message:
-----------
[Docs] Use cacheable myst_heading_slug_func value
Avoid creating an uncacheable conf variable by using a string instead of
a function reference. Also has the effect of avoiding triggering the
"config.cache" sphinx warning.
Requires myst_parser 0.19.0 (specifically
https://github.com/executablebooks/MyST-Parser/pull/696) which is over a
year old by now. Do we mandate any minimum version for these
dependencies?
Commit: db3792b87a4fd759e336c44946a3e2ec0008c993
https://github.com/llvm/llvm-project/commit/db3792b87a4fd759e336c44946a3e2ec0008c993
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
Log Message:
-----------
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
All of the test changes are because integer type legalization prefers to promote
fp_to_uint to fp_to_sint if neither is "Legal".
Commit: 7d3b81d06f96bc27673f31a7bd7d141ce4a2777b
https://github.com/llvm/llvm-project/commit/7d3b81d06f96bc27673f31a7bd7d141ce4a2777b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb] Bump the lldb-dap version number
Bump the lldb-dap version number so that we can publish and updated
version in the Visual Studio Marketplace.
Commit: 98bb354a0add4aeb614430f48a23f87992166239
https://github.com/llvm/llvm-project/commit/98bb354a0add4aeb614430f48a23f87992166239
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
Log Message:
-----------
[SLP]Fix PR107037: correctly track origonal/modified after vectorizations reduced values
Need to correctly track reduced values with multiple uses in the same
reduction emission attempt. Otherwise, the number of the reuses might be
calculated incorrectly, and may cause compiler crash.
Fixes https://github.com/llvm/llvm-project/issues/107037
Commit: d3c10b51a99d4476261f57ceaa7db60960cd5493
https://github.com/llvm/llvm-project/commit/d3c10b51a99d4476261f57ceaa7db60960cd5493
Author: Peter Lafreniere <peter at n8pjl.ca>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/test/CodeGen/M68k/Arith/add.ll
R llvm/test/CodeGen/M68k/Arith/sext-i1.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
A llvm/test/CodeGen/M68k/Data/link-unlnk.ll
A llvm/test/CodeGen/M68k/Data/load-extend.ll
A llvm/test/CodeGen/M68k/Data/load-imm.ll
A llvm/test/CodeGen/M68k/Data/sext-i1.ll
R llvm/test/CodeGen/M68k/link-unlnk.ll
R llvm/test/CodeGen/M68k/load-extend.ll
Log Message:
-----------
[M68k] Introduce more MOVI cases (#98377)
Add three more special cases for loading registers with immediates.
The first allows values in the range of [-255, 255] to be loaded with
MOVEQ, even if the register is more than 8 bits and the sign extention
is unwanted. This is done by loading the bitwise complement of the
desired value, then performing a NOT instruction on the loaded register.
This special case is only used when a simple MOVEQ cannot be used, and
is only used for 32 bit data registers. Address registers cannot support
MOVEQ, and the two-instruction sequence is no faster or smaller than a
plain MOVE instruction when loading 16 bit immediates on the 68000, and
likely slower for more sophisticated microarchitectures. However, the
instruction sequence is both smaller and faster than the corresponding
MOVE instruction for 32 bit register widths.
The second special case is for zeroing address registers. This simply
expands to subtracting a register with itself, consuming one instruction
word rather than 2-3, with a small improvement in speed as well.
The last special case is for assigning sign-extended 16-bit values to a
full address register. This takes advantage of the fact that the movea.w
instruction sign extends the output, permitting the immediate to be
smaller. This is similar to using lea with a 16-bit address, which is
not added in this patch as 16-bit absolute addressing is not yet
implemented.
This is a v2 submission of #90817. It also creates a 'Data' test
directory to better align with the backend's tablegen layout.
Commit: 1c874bbbd67c5795113fa307512ea514f06dac29
https://github.com/llvm/llvm-project/commit/1c874bbbd67c5795113fa307512ea514f06dac29
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/half-select-icmp.ll
Log Message:
-----------
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
Select only needs branches and moves so we don't need to promote it.
Promoting would canonicalize NaNs which select shouldn't do.
Commit: b24a304435632710bb54a0cd9cda1757abb8c160
https://github.com/llvm/llvm-project/commit/b24a304435632710bb54a0cd9cda1757abb8c160
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
Log Message:
-----------
[lld-macho] Always store symbol name length eagerly (NFC) (#106906)
The only instance where we weren't already passing a `StringRef` with a
known length to `Symbol`'s constructor is where the argument is a string
literal. Even in that case, lazy `strlen` calls don't make sense, as the
compiler can constant-evaluate the `StringRef(const char*)` constructor.
For symbols that go into the symbol table we need the length when
calculating the hash anyway. We could get away with not calling
`getName()` for local symbols, but the total contribution of `strlen` to
the run time is already below 1%, so that would just complicate the code
for a negligible benefit.
Commit: 3209766608d14fbb0add96916a28c3f98fed9460
https://github.com/llvm/llvm-project/commit/3209766608d14fbb0add96916a28c3f98fed9460
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Transforms/IPO/ModuleInliner.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
A llvm/test/Analysis/CtxProfAnalysis/inline.ll
A llvm/test/Analysis/CtxProfAnalysis/json_equals.py
M llvm/test/Analysis/CtxProfAnalysis/load.ll
M llvm/unittests/Transforms/Utils/CallPromotionUtilsTest.cpp
Log Message:
-----------
[ctx_prof] Add Inlining support (#106154)
Add an overload of `InlineFunction` that updates the contextual profile. If there is no contextual profile, this overload is equivalent to the non-contextual profile variant.
Post-inlining, the update mainly consists of:
- making the PGO instrumentation of the callee "the caller's": the owner function (the "name" parameter of the instrumentation instructions) becomes the caller, and new index values are allocated for each of the callee's indices (this happens for both increment and callsite instrumentation instructions)
- in the contextual profile:
- each context corresponding to the caller has its counters updated to incorporate the counters inherited from the callee at the inlined callsite. Counter values are copied as-is because no scaling is required since the profile is contextual.
- the contexts of the callee (at the inlined callsite) are moved to the caller.
- the callee context at the inlined callsite is deleted.
Commit: dce73e115e11cf75c0e50fb96a9ba046c880838e
https://github.com/llvm/llvm-project/commit/dce73e115e11cf75c0e50fb96a9ba046c880838e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
R llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
Log Message:
-----------
Revert "[SLP]Fix PR107037: correctly track origonal/modified after vectorizations reduced values"
This reverts commit 98bb354a0add4aeb614430f48a23f87992166239 to fix
buildbots https://lab.llvm.org/buildbot/#/builders/155/builds/2056 and https://lab.llvm.org/buildbot/#/builders/11/builds/4407
Commit: 18263c319092b878f25dd4025830f8e6691245d4
https://github.com/llvm/llvm-project/commit/18263c319092b878f25dd4025830f8e6691245d4
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_context.cpp
Log Message:
-----------
[compiler-rt][rtsan] Add scoped reporting lock (#107167)
Uses a static lock to ensure multiple threads reporting issues at the
same time don't have printing collisions. This isn't so important now,
but will be with continue mode in the future.
Commit: b076f6640e3c2781410588f4a8e4ccfeed8eb606
https://github.com/llvm/llvm-project/commit/b076f6640e3c2781410588f4a8e4ccfeed8eb606
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Target/TargetProperties.td
M lldb/test/API/functionalities/memory/big-read/TestMemoryReadMaximumSize.py
Log Message:
-----------
[lldb] Remove limit on max memory read size (#105765)
`memory read` will return an error if you try to read more than 1k bytes
in a single command, instructing you to set
`target.max-memory-read-size` or use `--force` if you intended to read
more than that. This is a safeguard for a command where people are being
explicit about how much memory they would like lldb to read (either to
display, or save to a file) and is an annoyance every time you need to
read more than a small amount. If someone confuses the --count argument
with the start address, lldb may begin dumping gigabytes of data but I'd
rather that behavior than requiring everyone to special-case their way
around a common use case.
I don't want to remove the setting because many people have added (much
larger) default max read sizes to their ~/.lldbinit files after hitting
this behavior. Another option would be to stop reading/using the value
in Target.cpp, but I see no harm in leaving the setting if someone
really does prefer to have a small cap on their memory read size.
Commit: 3e8840ba71bfcceeb598c2ca28d2d8784e24ba1e
https://github.com/llvm/llvm-project/commit/3e8840ba71bfcceeb598c2ca28d2d8784e24ba1e
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/VectorBuilder.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/IR/VectorBuilder.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
Remove "Target" from createXReduction naming [nfc]
Despite the stale comments, none of these actually use TTI, and they're
solely generating standard LLVM IR.
Commit: eaa95a1c2bd38332c1a4e634595f29d22b28ffea
https://github.com/llvm/llvm-project/commit/eaa95a1c2bd38332c1a4e634595f29d22b28ffea
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/test/CXX/drs/cwg24xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add test for CWG2486 (`noexcept` and function pointer conversion) (#107131)
[CWG2486](https://cplusplus.github.io/CWG/issues/2486.html) "Call to
`noexcept` function via `noexcept(false)` pointer/lvalue" allows
`noexcept` functions to be called via `noexcept(false)` pointers or
values. There appears to be no implementation divergence whatsoever:
https://godbolt.org/z/3afTfeEM8. That said, in C++14 and earlier we do
not issue all the diagnostics we issue in C++17 and newer, so I'm
specifying the status of the issue accordingly.
Commit: 83ad644afaac23577e3563d3ec1fac1b1fde37f4
https://github.com/llvm/llvm-project/commit/83ad644afaac23577e3563d3ec1fac1b1fde37f4
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.def
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10_2_512bf16intrin.h
A clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c
A clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
A llvm/test/CodeGen/X86/avx10.2-fma-commute.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt
A llvm/test/MC/X86/avx10.2-bf16-32-att.s
A llvm/test/MC/X86/avx10.2-bf16-32-intel.s
A llvm/test/MC/X86/avx10.2-bf16-64-att.s
A llvm/test/MC/X86/avx10.2-bf16-64-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86][AVX10.2] Support AVX10.2-BF16 new instructions. (#101603)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
Commit: 814aa432abf8e9f644903061029e6e27f6a418a8
https://github.com/llvm/llvm-project/commit/814aa432abf8e9f644903061029e6e27f6a418a8
Author: vporpo <vporpodas at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantAggregate (#107136)
This patch implements sandboxir:: ConstantAggregate, ConstantStruct,
ConstantArray and ConstantVector, mirroring LLVM IR.
Commit: 48bc8b0f7f49f5b23884a0d9d21056ec0bfffe24
https://github.com/llvm/llvm-project/commit/48bc8b0f7f49f5b23884a0d9d21056ec0bfffe24
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 83ad644afaac
Commit: ff0f2011e475141454028bce9cf7c6ff37a49620
https://github.com/llvm/llvm-project/commit/ff0f2011e475141454028bce9cf7c6ff37a49620
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
Log Message:
-----------
[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)
Previously, if Zfbfmin/Zfhmin were enabled, we only handled
build_vectors that could be turned into splat_vectors. We promoted them
to f32 splats by extending in the scalar domain and narrowing in the
vector domain.
This patch fixes a crash where we failed to account for whether the f32
vector type fit in LMUL<=8.
Because the new lowering occurs after type legalization, we have to be
careful to use XLenVT for the scalar integer type and use custom cast
nodes.
Commit: f1615e32379ff1ea125a8b3ac8792c3e0b5e6f2c
https://github.com/llvm/llvm-project/commit/f1615e32379ff1ea125a8b3ac8792c3e0b5e6f2c
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
Log Message:
-----------
[WebAssembly] Remove Kind argument from WebAssemblyOperand (NFC) (#107157)
The `Kind` argument does not need to passed separately.
Commit: c8763f04bf2162d3f0f4f967dfeb2f0feda0c75b
https://github.com/llvm/llvm-project/commit/c8763f04bf2162d3f0f4f967dfeb2f0feda0c75b
Author: Yun-Fly <yunfei.song at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
[mlir][tensor] Fix consumer fusion for `tensor.pack` without explicit `outer_dims_perm` attribute (#106687)
Commit: 99f02a874984f2b79c3fbd8ae6bbceb7366521ad
https://github.com/llvm/llvm-project/commit/99f02a874984f2b79c3fbd8ae6bbceb7366521ad
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A clang/test/CXX/drs/cwg1818.cpp
M clang/test/CXX/drs/cwg18xx.cpp
A clang/test/CXX/drs/cwg563.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add tests for CWG issues about language linkage (#107019)
This patch covers Core issues about language linkage during declaration
matching resolved in
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html),
namely [CWG563](https://cplusplus.github.io/CWG/issues/563.html) and
[CWG1818](https://cplusplus.github.io/CWG/issues/1818.html).
[CWG563](https://cplusplus.github.io/CWG/issues/563.html) "Linkage
specification for objects"
-----------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
> [CWG563](https://cplusplus.github.io/CWG/issues/563.html) is resolved
by simplifications that follow its suggestions.
Wording ([[dcl.link]/5](https://eel.is/c++draft/dcl.link#5)):
> In a
[linkage-specification](https://eel.is/c++draft/dcl.link#nt:linkage-specification),
the specified language linkage applies to the function types of all
function declarators and to all functions and variables whose names have
external linkage[.](https://eel.is/c++draft/dcl.link#5.sentence-5)
Now the wording clearly says that linkage-specification applies to
variables with external linkage.
[CWG1818](https://cplusplus.github.io/CWG/issues/1818.html) "Visibility
and inherited language linkage"
------------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
>
[CWG386](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#386),
[CWG1839](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1839),
[CWG1818](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1818),
[CWG2058](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#2058),
[CWG1900](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1900),
and Richard’s observation in [“are non-type names ignored in a
class-head-name or
enum-head-name?”](http://lists.isocpp.org/core/2017/01/1604.php) are
resolved by describing the limited lookup that occurs for a
declarator-id, including the changes in Richard’s [proposed resolution
for
CWG1839](http://wiki.edg.com/pub/Wg21cologne2019/CoreWorkingGroup/cwg1839.html)
(which also resolves CWG1818 and what of CWG2058 was not resolved along
with CWG2059) and rejecting the example from
[CWG1477](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#1477).
Wording ([[dcl.link]/6](https://eel.is/c++draft/dcl.link#6)):
> A redeclaration of an entity without a linkage specification inherits
the language linkage of the entity and (if applicable) its
type[.](https://eel.is/c++draft/dcl.link#6.sentence-2).
Answer to the question in the example is `extern "C"`, and not linkage
mismatch. Further analysis of the example is provided as inline comments
in the test itself. Note that https://eel.is/c++draft/dcl.link#7 does
NOT apply in this example, as it's focused squarely at declarations that
are already known to have C language linkage, and declarations of
variables in the global scope.
Commit: b057e16740311b9c690c0c991c48b5087bf24d9a
https://github.com/llvm/llvm-project/commit/b057e16740311b9c690c0c991c48b5087bf24d9a
Author: Reid Kleckner <rnk at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemorySSA.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/OperandTraits.h
M llvm/include/llvm/IR/Operator.h
M llvm/include/llvm/IR/User.h
M llvm/lib/IR/ConstantsContext.h
Log Message:
-----------
[IR] Remove unused MINARITY operand trait tpl args, NFC (#107165)
These don't look like they've been used since the original 'use-diet'
branch was merged in 2008 ( f6caff66a1bfa6464e6a17c0bcfcf06a09a9b909)
Commit: ed220e15718498d0f854f1044ddcbfee00739aa7
https://github.com/llvm/llvm-project/commit/ed220e15718498d0f854f1044ddcbfee00739aa7
Author: Elvis Wang <110374989+ElvisWang123 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan][NFC] Implement `VPWidenMemoryRecipe::computeCost()`. (#105614)
In this patch, we implement the `computeCost()` function in
`VPWidenMemoryRecipe`.
Commit: 9b5971ad0355d43a9bd37b1067d93ff8b08eba81
https://github.com/llvm/llvm-project/commit/9b5971ad0355d43a9bd37b1067d93ff8b08eba81
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-extmul.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
[AArch64][GlobalISel] Lower G_BUILD_VECTOR to G_INSERT_VECTOR_ELT (#105686)
The lowering happens in post-legalizer lowering if any source registers
from G_BUILD_VECTOR are not constants.
Add pattern pragment setting `scalar_to_vector ($src)` asequivalent to
`vector_insert (undef), ($src), (i61 0)`
Commit: 12c0823d67a8d5a61d6430aac609ef5e468267a6
https://github.com/llvm/llvm-project/commit/12c0823d67a8d5a61d6430aac609ef5e468267a6
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/tools/clang-format/git-clang-format.bat
Log Message:
-----------
[clang-format] Handle spaces in file paths in git-clang-format.bat (#107041)
This patch is provided by @jeliebig.
Fixes #107017.
Commit: a27ff17034d66d852ba83be7d237d6a623cb4ff4
https://github.com/llvm/llvm-project/commit/a27ff17034d66d852ba83be7d237d6a623cb4ff4
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a regression in annotating ObjCBlockLParen (#107021)
Fixes #106994.
Commit: b55186eefd73b3848e01c8471c47a9354969d652
https://github.com/llvm/llvm-project/commit/b55186eefd73b3848e01c8471c47a9354969d652
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/test/Preprocessor/init-ppc.c
M clang/test/Preprocessor/init-ppc64.c
Log Message:
-----------
[clang][Driver] Define soft float macros for PPC. (#106012)
Fixes #105972.
Co-authored-by: Qiu Chaofan <qcf at ecnelises.com>
Commit: 8d0816615f920b0783bafa903804b9e2a2fa4e91
https://github.com/llvm/llvm-project/commit/8d0816615f920b0783bafa903804b9e2a2fa4e91
Author: yifeizh2 <yifei.zhang at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[MLIR][Tensor] Fix source/dest type check in UnPackOp canonicalize (#106094)
Fix `RankedTensorType` equality check in unpack op canonicalization.
Commit: 812c96e8b9354e5e84d513f5b03172db5ad3b491
https://github.com/llvm/llvm-project/commit/812c96e8b9354e5e84d513f5b03172db5ad3b491
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Handle pointer/reference in macro definitions (#107074)
A macro definition needs its own scope stack in the annotator, so we add
the MacroBodyScopes stack and use ScopeStack to refer to it when in the
macro definition body.
Also, we need to have a scope type for a child block because its parent
line is parsed (and thus the scope type for the braces is popped off the
scope stack) before the lines in the child block are.
Fixes #99271.
Commit: f4b9839d6f7c9ec2967a42f2d5546a2a2ae77ca4
https://github.com/llvm/llvm-project/commit/f4b9839d6f7c9ec2967a42f2d5546a2a2ae77ca4
Author: Longsheng Mou <moulongsheng at huawei.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Conversion/TensorToSPIRV/TensorToSPIRV.cpp
M mlir/test/Conversion/TensorToSPIRV/tensor-ops-to-spirv.mlir
Log Message:
-----------
[mlir][TensorToSPIRV] Add type check for `tensor.extract` in TensorToSPIRV (#107110)
This patch add a type check for `tensor.extract` in TensorToSPIRV.
Only convert `tensor.extract` with supported element type. Fix #74466.
Commit: 37263b6c6741894ffbc0f61979c5c85db515ef2d
https://github.com/llvm/llvm-project/commit/37263b6c6741894ffbc0f61979c5c85db515ef2d
Author: Longsheng Mou <moulongsheng at huawei.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
[mlir][tosa] Add verifier for `tosa.pad` (#106351)
This patch adds verifier to `tosa.pad` which fixes a crash. `tosa.pad`
expect:
- same input and output tensor rank.
- 'padding' tensor rank equal to 2.
Fix #106168.
Commit: a628bc3c2e7314e4b7c9af0d10cf39a70c731d15
https://github.com/llvm/llvm-project/commit/a628bc3c2e7314e4b7c9af0d10cf39a70c731d15
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
Log Message:
-----------
[AArch64] Fix a warning
This patch fixes:
lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc:506:14:
error: unused variable 'GIMatchData_matchinfo'
[-Werror,-Wunused-variable]
Commit: 9a17a6016d02afa6e973f141ab1cada68571f2d2
https://github.com/llvm/llvm-project/commit/9a17a6016d02afa6e973f141ab1cada68571f2d2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Log Message:
-----------
[PowerPC] Use DenseMap::operator[] (NFC) (#107044)
Commit: f15e3e58c59b4d31eee24fa9debc5dfad0c20028
https://github.com/llvm/llvm-project/commit/f15e3e58c59b4d31eee24fa9debc5dfad0c20028
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
[CGOpenMPRuntime] Use DenseMap::operator[] (NFC) (#107158)
I'm planning to deprecate DenseMap::FindAndConstruct in favor of
DenseMap::operator[].
Commit: 86627149f6fd5148311b7b0aa1c7195a05a5d6a8
https://github.com/llvm/llvm-project/commit/86627149f6fd5148311b7b0aa1c7195a05a5d6a8
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
A llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
A llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
Log Message:
-----------
[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)
Any SGPR read by a VALU can potentially obscure SALU writes to the same
register.
Insert s_wait_alu instructions to mitigate the hazard on affected paths.
Compute a global cache of SGPRs with any VALU reads and use this to
avoid inserting mitigation for SGPRs never accessed by VALUs.
To avoid excessive search when compile time is priority implement
secondary mode where all SALU writes are mitigated.
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: a5ce66423bfff6f2185e5fe48bc6ffc0ade7df4d
https://github.com/llvm/llvm-project/commit/a5ce66423bfff6f2185e5fe48bc6ffc0ade7df4d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
Log Message:
-----------
[RISCV] Remove RISCVISD::FP_ROUND_BF16.
Use isel patterns on regular FP_ROUND. For double->bf16 we need
to emit two instructions. Note the double->bf16 conversion does
double rounding, but I don't know a good way to fix that.
Commit: 0ad6cee926865d7210eed9e67bfb20dce19c6633
https://github.com/llvm/llvm-project/commit/0ad6cee926865d7210eed9e67bfb20dce19c6633
Author: Elvis Wang <110374989+ElvisWang123 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/cast.ll
Log Message:
-----------
[RISCV] Fix missing `i64` to `double` tests in the cast.ll. (NFC) (#106972)
Commit: 8b28e2ebb36d72cfffe04904e3e1b9fdfa36ef94
https://github.com/llvm/llvm-project/commit/8b28e2ebb36d72cfffe04904e3e1b9fdfa36ef94
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
Log Message:
-----------
[WebAssembly] Rename legacy EH tests (#107166)
Give each test in `cfg-stackify-eh-legacy.ll` a name rather than
something like `test5`, because I plan to copy many of these test into a
new file that tests for the new EH (exnref) and some of the tests here
are not applicable to the new EH so the numbering will be different,
which can make things confusing.
Also this removes `test_` prefixes in the test function names in
`exception-legacy.ll`, because, well, we all know they are tests.
Commit: 9fef09fd2918e7d8c357b98a9a798fe207941f73
https://github.com/llvm/llvm-project/commit/9fef09fd2918e7d8c357b98a9a798fe207941f73
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
M clang/test/CodeGen/X86/x86-atomic-double.c
M clang/test/CodeGen/X86/x86-atomic-long_double.c
Log Message:
-----------
[Clang][CodeGen] Fix type for atomic float incdec operators (#107075)
`llvm::ConstantFP::get(llvm::LLVMContext&, APFloat(float))` always
returns a f32 constant.
Fix https://github.com/llvm/llvm-project/issues/107054.
Commit: 6c607cfb2c2d8acd2b92d7ed8106ab1e4fc0d79d
https://github.com/llvm/llvm-project/commit/6c607cfb2c2d8acd2b92d7ed8106ab1e4fc0d79d
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
Log Message:
-----------
[RISCV] Preserve tail agnostic policy in foldVMV_V_V (#105788)
This patch helps avoid regressions in an upcoming patch by making sure
we don't accidentally lose a tail agnostic policy when folding a vmv.v.v
into its source.
The previous comment about RISCVInsertVSETVLI relaxing the policy didn't
take into account the fact that there's a policy operand on vmv.v.v,
which can be tail agnostic.
If the tail is agnostic (via either the policy operand or the passthru
being undef) and vmv.v.v's VL <= Src's VL, then Src's tail can be made
agnostic.
Commit: c94bd96c277e0b48e198fdc831bb576d9a04aced
https://github.com/llvm/llvm-project/commit/c94bd96c277e0b48e198fdc831bb576d9a04aced
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGStmt.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
Log Message:
-----------
[Clang][CodeGen] Don't emit assumptions if current block is unreachable. (#106936)
Fixes https://github.com/llvm/llvm-project/issues/106898.
When emitting an infinite loop, clang codegen will delete the whole
block and leave builder's current block as nullptr:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/clang/lib/CodeGen/CGStmt.cpp#L597-L600
Then clang will create `zext (icmp slt %a, %b)` without parent block for
`a < b`. It will crash here:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/clang/lib/CodeGen/CGExprScalar.cpp#L416-L420
Even if we disabled this optimization, it still crashes in
`Builder.CreateAssumption`:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/llvm/lib/IR/IRBuilder.cpp#L551-L561
This patch disables assumptions emission if current block is null.
Commit: 3e798476de466e8a051d3e753db379731a8d9705
https://github.com/llvm/llvm-project/commit/3e798476de466e8a051d3e753db379731a8d9705
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
Log Message:
-----------
[LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32 when we don't have Zvfh. (#106652)
The fp_extend will canonicalize NaNs which is not the semantics of
FNEG/FABS/FCOPYSIGN.
For fixed vectors I'm scalarizing due to test changes on other targets
where the scalarization is expected. I will try to address in a follow
up.
For scalable vectors, we bitcast to integer and use integer logic ops.
Commit: 41402c6a8aa3a4336122bdb4530fb05538efedba
https://github.com/llvm/llvm-project/commit/41402c6a8aa3a4336122bdb4530fb05538efedba
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
Log Message:
-----------
[RISCV][GISel] Use CCValAssign::getCustomReg for converting f16/f32<->GPR. (#105700)
This gives us much better control of the generated code for GISel. I've
tried to closely match the current gisel code, but it looks like we had
2 layers of G_ANYEXT in some cases before.
SelectionDAG now checks needsCustom() instead of detecting the special
cases in the Bitcast handler.
Unfortunately, IRTranslator for bitcast still generates copies between
register classes of different sizes. Because of this we can't handle
i16<->f16 bitcasts without crashing. Not sure if I should teach
RISCVInstrInfo::copyPhysReg to allow copies between FPR16 and GPR or if
I should convert the copies to instructions in GISel.
Commit: 4a44898be5d46694b59aa411f2b45a52f2ce8411
https://github.com/llvm/llvm-project/commit/4a44898be5d46694b59aa411f2b45a52f2ce8411
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
Log Message:
-----------
[RISCV] Add passthru to vmv.v.v intrinsic tests. NFC
This prevents them from being optimized away in an upcoming peephole
Commit: 3449ed8dece600f387357b71ff74ae4bc46828b6
https://github.com/llvm/llvm-project/commit/3449ed8dece600f387357b71ff74ae4bc46828b6
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
Revert "[clang-format] Correctly annotate braces in macro definition (#106662)"
This reverts commit 0fa78b6c7bd43c2498700a98c47a02cf4fd06388 due to
regression.
Fixes #107096.
Commit: 7deda4ed0c712fb830d25f4e3090ff04f7adbcf9
https://github.com/llvm/llvm-project/commit/7deda4ed0c712fb830d25f4e3090ff04f7adbcf9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Use MCRegister for variables returned from AllocateReg. NFC
Avoids a cast from Register to MCRegister for the CCValAssign
functions.
Commit: 06286832db0c4ee1899f9cee1b8f6234e45f16c7
https://github.com/llvm/llvm-project/commit/06286832db0c4ee1899f9cee1b8f6234e45f16c7
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
Reland "Revert "AtomicExpand: Allow incrementally legalizing atomicrmw"" (#106793)
Reverts llvm/llvm-project#106792
The first commit of PR is pure revert, the rest is a possible fix.
Commit: 427e202a401514cb28bf2ca621baae8e1b2f552f
https://github.com/llvm/llvm-project/commit/427e202a401514cb28bf2ca621baae8e1b2f552f
Author: Princeton Ferro <princetonferro at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Support/APInt.cpp
Log Message:
-----------
[APInt] improve initialization performance (#106945)
The purpose is to save an extra memset in both cases:
1. When `int64_t(val) < 0`, zeroing out is redundant as the subsequent
for-loop will initialize to `val .. 0xFFFFF ....`. Instead we should
only create an uninitialized buffer, and transform the slow for-loop
into a memset to initialize the higher words to `0xFF`.
2. In the other case, first we create an uninitialized array (`new
int64_t[]`) and _then_ we zero it out with `memset`. But this can be
combined in one operation with `new int64_t[]()`, which
default-initializes the array.
On one example where use of APInt was heavy, this improved compile time
by 1%.
Commit: 4bccb01355edcfedacafede3e7878d74e2b0a28f
https://github.com/llvm/llvm-project/commit/4bccb01355edcfedacafede3e7878d74e2b0a28f
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaCXX/source_location.cpp
Log Message:
-----------
[Clang] Workaround dependent source location issues (#106925)
In #78436 we made some SourceLocExpr dependent to
deal with the fact that their value should reflect the name of
specialized function - rather than the rtemplate in which they are first
used.
However SourceLocExpr are unusual in two ways
- They don't depend on template arguments
- They morally depend on the context in which they are used (rather than
called from).
It's fair to say that this is quite novels and confuses clang. In
particular, in some cases, we used to create dependent SourceLocExpr and
never subsequently transform them, leaving dependent objects in
instantiated functions types. To work around that we avoid replacing
SourceLocExpr when we think they could remain dependent.
It's certainly not perfect but it fixes a number of reported bugs, and
seem to only affect scenarios in which the value of the SourceLocExpr
does not matter (overload resolution).
Fixes #106428
Fixes #81155
Fixes #80210
Fixes #85373
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: de37da8e37c4c9042563e186068adca98bf59e07
https://github.com/llvm/llvm-project/commit/de37da8e37c4c9042563e186068adca98bf59e07
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/MachineOutliner.cpp
A llvm/test/CodeGen/AArch64/machine-outliner-bundle.mir
Log Message:
-----------
[MachineOutliner] Preserve instruction bundles (#106402)
When the machine outliner copies instructions from a source function
into an outlined function, it was doing it using `CloneMachineInstr`,
which is documented as not preserving the interior of any instruction
bundle. So outlining code that includes an instruction bundle would
fail, because in the outlined version, the bundle would be empty, so
instructions would go missing in the move.
This occurs when any bundled instruction appears in the outlined code,
so there was no need to construct an unusual test case: I've just copied
a function from the existing `stp-opt-with-renaming.mir`, which happens
to contain an SVE instruction bundle. Including two identical copies of
that function makes the outliner merge them, and then we check that it
didn't destroy the interior of the bundle in the process.
Commit: 01e56849001b4ace984e9557abc82bc051e03677
https://github.com/llvm/llvm-project/commit/01e56849001b4ace984e9557abc82bc051e03677
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCXX/attr-lifetimebound.cpp
Log Message:
-----------
[clang] Respect the lifetimebound in assignment operator. (#106997)
Fixes #106372
Commit: 771b7af1db15e59f370ccadaa98bee8e5270b5f1
https://github.com/llvm/llvm-project/commit/771b7af1db15e59f370ccadaa98bee8e5270b5f1
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFDie.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFDieTest.cpp
Log Message:
-----------
Reapply "[llvm/DWARF] Recursively resolve DW_AT_signature references"… (#99495)
… (#99444)
The previous version introduced a bug (caught by cross-project tests).
Explicit signature resolution is still necessary when one wants to
access the children (not attributes) of a given DIE.
The new version keeps just the findRecursively extension, and reverts
all the DWARFTypePrinter modifications.
Commit: 009184fc3920f8a14dff9971edf68754ba28da5f
https://github.com/llvm/llvm-project/commit/009184fc3920f8a14dff9971edf68754ba28da5f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/ModuleSummaryIndexYAML.h
Log Message:
-----------
[ThinLTO] Avoid repeated std::map lookups (NFC) (#107156)
This patch avoids repeated std::map lookups with try_emplace.
While I am at it, this patch adds a couple of calls to
std::vector::reserve.
Commit: 8bfd6b953fc119bbc37c1755e701261fcfb31ad2
https://github.com/llvm/llvm-project/commit/8bfd6b953fc119bbc37c1755e701261fcfb31ad2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SSAUpdaterImpl.h
Log Message:
-----------
[SSAUpdater] Use DenseMap::operator[] (NFC) (#107179)
I'm planning to deprecate DenseMap::FindAndConstruct in favor of
DenseMap::operator[]. I thought about renaming the variable to
PredInfo, but the name is taken, so I am leaving the name as is.
Commit: e99eb89d5d97efc709f18f9369f2ec087352baaa
https://github.com/llvm/llvm-project/commit/e99eb89d5d97efc709f18f9369f2ec087352baaa
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Log Message:
-----------
[SimplifyCFG] Use range-based for loops (NFC) (#107180)
Commit: aacdc657fc255b2547bb37ee9bacde2df0452298
https://github.com/llvm/llvm-project/commit/aacdc657fc255b2547bb37ee9bacde2df0452298
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
Log Message:
-----------
[Clang] Preserve the ExpandsToEmpty flag in PackIndexingType (#107181)
Similar to PackIndexingExpr, we should avoid another round of
transformation of the pattern if the pattern has already turned out to
be an empty pack. As an outcome, the empty SubstTemplateTypeParmPackType
won't occur, and we don't need to collect any unexpanded packs.
Fixes https://github.com/llvm/llvm-project/issues/105903
Commit: 331f8225f37b714a4df7ff3176b574b756f4d965
https://github.com/llvm/llvm-project/commit/331f8225f37b714a4df7ff3176b574b756f4d965
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/AsmParser/AsmParserImpl.h
Log Message:
-----------
[mlir][AsmParser] Expose `parseMinus()` (#106881)
Found while working on parser for custom expression type for my dialect.
Builtin `AffineExpr` uses low-level parser API which is not available
for external users.
Commit: 8133d47632f35df00933bfd3d3626b003206ede4
https://github.com/llvm/llvm-project/commit/8133d47632f35df00933bfd3d3626b003206ede4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
[CGOpenMPRuntime] Use DenseMap::operator[] (NFC) (#107185)
I'm planning to deprecate DenseMap::FindAndConstruct in favor of
DenseMap::operator[].
Commit: 12d678a8eb11821e20eab86445f0cc9b66c24990
https://github.com/llvm/llvm-project/commit/12d678a8eb11821e20eab86445f0cc9b66c24990
Author: David Green <david.green at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/zext-shuffle.ll
Log Message:
-----------
[AArch64] Add codegen tests for zext(deinterleave). NFC
Commit: 030e4d0cdf4c43a6ec1ca301b5a358991fa2ac4f
https://github.com/llvm/llvm-project/commit/030e4d0cdf4c43a6ec1ca301b5a358991fa2ac4f
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseTemplate.cpp
M clang/test/SemaCXX/cxx2a-template-lambdas.cpp
Log Message:
-----------
[Clang] Treat default template argument as constant expressions (#107073)
We only check that a default argument is a converted constant expression
when using the default argument.
However, when parsing a default argument, we need to make sure to parse
it as a constant expression such as not ODR-use variables. (otherwise,
we would try to capture default template arguments of generic lambdas)
Fixes #107048
Commit: 50febdeb64fce345b0fb669e9688d34c8ffe7912
https://github.com/llvm/llvm-project/commit/50febdeb64fce345b0fb669e9688d34c8ffe7912
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
M mlir/test/Dialect/Vector/linearize.mlir
Log Message:
-----------
[mlir][vector] Bugfix of linearize `vector.extract` (#106836)
This patch add check for `vector.extract` with scalar type, which is not
allowed when linearize `vector.extract`. Fix #106162.
Commit: 58f289612f1959256fa2228f013cfe96304b45c4
https://github.com/llvm/llvm-project/commit/58f289612f1959256fa2228f013cfe96304b45c4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/XRay/Graph.h
Log Message:
-----------
[XRay] Use DenseMap::{operator[],try_emplace} (NFC) (#107178)
I'm planning to deprecate DenseMap::FindAndConstruct in favor of
operator[]. I'm using try_emplace because "Vertices[I.first];" on its
own might look like a nop statement.
Commit: 9e08db796b7fc1aa21ec0a0c16a0213229e02010
https://github.com/llvm/llvm-project/commit/9e08db796b7fc1aa21ec0a0c16a0213229e02010
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
A flang/test/Integration/debug-target-region-vars.f90
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
A mlir/test/Target/LLVMIR/omptarget-debug.mlir
A mlir/test/Target/LLVMIR/omptarget-debug2.mlir
Log Message:
-----------
[OpenMPIRBuilder] Don't drop debug info for target region. (#80692)
When an outlined function is generated for omp target region, a
corresponding DISubprogram was not being generated. This resulted in all
the debug information for the target region being dropped.
This commit adds DISubprogram for the outlined function if there is one
available for the parent function. It also updates the current debug
location so that the right scope is used for the entries in the outlined
function.
There are places in the OpenMPIRBuilder which changes insertion point but
don't update the debug location accordingly. They cause issue when debug info
is enabled. I have fixed a few that I observed to cause issue. But there may be
more and a systematic cleanup may be required.
With this change in place, I can set source line breakpoint in target
region and run to them in debugger.
Commit: 5914566474de29309b0b4815ecd406805793de1f
https://github.com/llvm/llvm-project/commit/5914566474de29309b0b4815ecd406805793de1f
Author: Nathan Gauër <brioche at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A llvm/test/Other/spirv-sim/branch.spv
A llvm/test/Other/spirv-sim/call.spv
A llvm/test/Other/spirv-sim/constant.spv
A llvm/test/Other/spirv-sim/lit.local.cfg
A llvm/test/Other/spirv-sim/loop.spv
A llvm/test/Other/spirv-sim/simple-bad-result.spv
A llvm/test/Other/spirv-sim/simple.spv
A llvm/test/Other/spirv-sim/simulator-args.spv
A llvm/test/Other/spirv-sim/switch.spv
A llvm/test/Other/spirv-sim/wave-get-lane-index.spv
A llvm/test/Other/spirv-sim/wave-read-lane-first.spv
M llvm/test/lit.cfg.py
A llvm/utils/spirv-sim/instructions.py
A llvm/utils/spirv-sim/spirv-sim.py
Log Message:
-----------
[Utils][SPIR-V] Adding spirv-sim to LLVM (#107094)
### 2nd submission
The buildbots are using python 3.8, and some type annotations I was
using are only available starting 3.9. The last commit on the pile is
the additional changes compared to the original submission
https://github.com/llvm/llvm-project/pull/104020.
### Original text:
Currently, the testing infrastructure for SPIR-V is based on FileCheck.
Those tests are great to check some level of codegen, but when the test
needs check both the CFG layout and the content of each basic-block,
things becomes messy.
Because the CHECK/CHECK-DAG/CHECK-NEXT state is limited, it is sometimes
hard to catch the good block: if 2 basic blocks have similar
instructions, FileCheck can match the wrong one.
Cross-lane interaction can be a bit difficult to understand, and
writting a FileCheck test that is strong enough to catch bad CFG
transforms while not being broken everytime some unrelated codegen part
changes is hard.
And lastly, the spirv-val tooling we have checks that the generated
SPIR-V respects the spec, not that it is correct in regards to the
source IR.
For those reasons, I believe the best way to test the structurizer is
to:
run spirv-val to make sure the CFG respects the spec.
simulate the function to validate result for each lane, making sure the
generated code is correct.
This simulator has no other dependencies than core python. It also only
supports a very limited set of instructions as we can test most features
through control-flow and some basic cross-lane interactions.
As-is, the added tests are just a harness for the simulator itself. If
this gets merged, the structurizer PR will benefit from this as I'll be
able to add extensive testing using this.
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: afb6dafc6b680fb204d40c7fee4b339aa8471010
https://github.com/llvm/llvm-project/commit/afb6dafc6b680fb204d40c7fee4b339aa8471010
Author: Nathan Gauër <brioche at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
A clang/test/CodeGenHLSL/builtins/wave_is_first_lane.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
A llvm/test/CodeGen/DirectX/wave_is_first_lane.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveIsFirstLane.ll
Log Message:
-----------
[clang][HLSL] Add WaveIsFirstLane() intrinsic (#103299)
This commits add the WaveIsFirstLane() hlsl intrinsinc. This intrinsic
uses the convergence intrinsincs for the SPIR-V backend. On the DXIL
side, I'm not sure what the strategy is for convergence, so I
implemented that like in DXC: a normal builtin function.
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: cc5c526c80a4cacf7ed5b7fbe50072594ec1aeaf
https://github.com/llvm/llvm-project/commit/cc5c526c80a4cacf7ed5b7fbe50072594ec1aeaf
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lldb/source/Target/Process.cpp
M lldb/test/API/functionalities/memory/holes/TestMemoryHoles.py
Log Message:
-----------
[lldb] Fix and speedup the `memory find` command (#104193)
This patch fixes an issue where the `memory find` command would
effectively stop searching after encountering a memory read error (which
could happen due to unreadable memory), without giving any indication
that it has done so (it would just print it could not find the pattern).
To make matters worse, it would not terminate after encountering this
error, but rather proceed to slowly increment the address pointer, which
meant that searching a large region could take a very long time (and
give the appearance that lldb is actually searching for the thing).
The patch fixes this first problem by detecting read errors and
skipping over (using GetMemoryRegionInfo) the unreadable parts of memory
and resuming the search after them. It also reads the memory in bulk
(`max(sizeof(pattern))`), which speeds up the search significantly (up
to 6x for live processes, 18x for core files).
Commit: 0b2550f8ab77a53f560f6a7a1b401c4803a36d48
https://github.com/llvm/llvm-project/commit/0b2550f8ab77a53f560f6a7a1b401c4803a36d48
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lldb/test/API/api/multiple-debuggers/TestMultipleDebuggers.py
Log Message:
-----------
[lldb][test] Disable TestMultipleDebuggers on Linux
This used to timeout (https://github.com/llvm/llvm-project/issues/101162)
now it's aborting (https://github.com/llvm/llvm-project/pull/105765#issuecomment-2327645665)
Commit: 69657eb7f67600ec1c5c449d13eef3670dfb64da
https://github.com/llvm/llvm-project/commit/69657eb7f67600ec1c5c449d13eef3670dfb64da
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/test/CodeGen/AArch64/PHIElimination-crash.mir
M llvm/test/CodeGen/AArch64/PHIElimination-debugloc.mir
M llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir
M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
M llvm/test/CodeGen/AMDGPU/split-mbb-lis-subrange.mir
M llvm/test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
M llvm/test/CodeGen/Hexagon/two-addr-tied-subregs.mir
M llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
M llvm/test/CodeGen/PowerPC/livevars-crash1.mir
M llvm/test/CodeGen/PowerPC/livevars-crash2.mir
M llvm/test/CodeGen/X86/distancemap.mir
M llvm/test/CodeGen/X86/phielim-undef.mir
M llvm/test/CodeGen/X86/twoaddr-mul2.mir
M llvm/test/tools/llc/new-pm/pipeline.mir
M llvm/test/tools/llc/new-pm/verify.mir
M llvm/tools/llc/NewPMDriver.cpp
M llvm/tools/llc/NewPMDriver.h
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[llc] Provide `opt` like verifier options (#106665)
- Support `verify-each` option.
- Default behavior is verifying output only.
Commit: deeafeab815ddfe7b507e9f79fe8f992265a9f3b
https://github.com/llvm/llvm-project/commit/deeafeab815ddfe7b507e9f79fe8f992265a9f3b
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lldb/include/lldb/Host/Socket.h
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/common/TCPSocket.cpp
Log Message:
-----------
[lldb][NFC] Move few static helpers to the class Socket (#106640)
Fixed a typo in Socket::SetOption().
Commit: 59093cae8681fe5d3d951905887b67a99acf76e6
https://github.com/llvm/llvm-project/commit/59093cae8681fe5d3d951905887b67a99acf76e6
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_luti.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_imm_lane.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sve2-intrinsics-luti.ll
Log Message:
-----------
[AARCH64][SVE] Add intrinsics for SVE LUTI instructions (#97058)
This patch adds intrinsics for LUTI2 and LUTI4 instructions, which use
SVE registers, as specified in the
https://github.com/ARM-software/acle/pull/324
Commit: 3e948eb3e88d89107406ca0812934bea42101e3a
https://github.com/llvm/llvm-project/commit/3e948eb3e88d89107406ca0812934bea42101e3a
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Basic/arm_neon.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/aarch64-neon-luti.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/neon-luti.ll
Log Message:
-----------
[AArch64][NEON] Add intrinsics for LUTI (#96883)
This patch adds intrinsics for NEON LUTI2 and LUTI4 instructions as
specified in the [ACLE
proposal](https://github.com/ARM-software/acle/pull/324)
Commit: 5a658ee933065d0e4ef1a65d9a6ddfba2874ee98
https://github.com/llvm/llvm-project/commit/5a658ee933065d0e4ef1a65d9a6ddfba2874ee98
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lldb/test/API/tools/lldb-server/TestGdbRemoteLaunch.py
M lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
M lldb/test/API/tools/lldb-server/TestNonStop.py
Log Message:
-----------
[lldb][test] Skip some lldb-server tests on Windows
These are known to return errors occasionaly on our Windows on Arm
bot.
Commit: d25e24a0eb909b7604572d28d15cbe648ecccd90
https://github.com/llvm/llvm-project/commit/d25e24a0eb909b7604572d28d15cbe648ecccd90
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/CastingThroughVoidCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/casting-through-void.cpp
Log Message:
-----------
[clang-tidy] Suggest using reinterpret_cast in bugprone-casting-thro… (#106784)
…ugh-void
reinterpret_cast is the equivalent construct, and more clearly expresses
intent.
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: 519b36925cf2e1a59f76bd509471d2e1830169f0
https://github.com/llvm/llvm-project/commit/519b36925cf2e1a59f76bd509471d2e1830169f0
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
Log Message:
-----------
[LLD][COFF][NFC] Store impSym as DefinedImportData in ImportFile. (#107162)
Commit: 126d6f27102fca0d69dc50cf29a37442d18304cf
https://github.com/llvm/llvm-project/commit/126d6f27102fca0d69dc50cf29a37442d18304cf
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
Log Message:
-----------
[AMDGPU] Improve codegen for GFX10+ DPP reductions and scans (#107108)
Use poison for an unused input to the permlanex16 intrinsic, to improve
register allocation and avoid an unnecessary v_mov instruction.
Commit: 2fef449f30e2f484897cb199e3338a1520803c7d
https://github.com/llvm/llvm-project/commit/2fef449f30e2f484897cb199e3338a1520803c7d
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[LLVM][AArch64] Enable verifyTargetSDNode for scalable vectors and fix the fallout. (#104820)
Fix incorrect use of AArch64ISD::UZP1/UUNPK{HI,LO} in:
AArch64TargetLowering::LowerDIV
AArch64TargetLowering::LowerINSERT_SUBVECTOR
The latter highlighted DAG combines that relied on broken behaviour,
which this patch also fixes.
Commit: 29c076b8598c9627cea493fdfc1a30c83385e820
https://github.com/llvm/llvm-project/commit/29c076b8598c9627cea493fdfc1a30c83385e820
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Analysis/Lint.cpp
A llvm/test/Analysis/Lint/scalable.ll
Log Message:
-----------
[Lint] Fix crash with scalable alloca
Commit: 4f3f09e787bab3caccd9496d93e6453c71d7869f
https://github.com/llvm/llvm-project/commit/4f3f09e787bab3caccd9496d93e6453c71d7869f
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/test/Integration/debug-assumed-shape-array.f90
M flang/test/Transforms/debug-assumed-shape-array.fir
Log Message:
-----------
[flang][debug] Add stride information for assumed shape array. (#106703)
Without this information, debugger could present wrong values for arrays
in certain cases as shown in issue #105646.
Fixes #105646.
Commit: d77ccae4a629ba11b5c28f97222a8834c5e5c183
https://github.com/llvm/llvm-project/commit/d77ccae4a629ba11b5c28f97222a8834c5e5c183
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lldb/source/Target/Process.cpp
Log Message:
-----------
[lldb] Fix 32 bit compile error
https://lab.llvm.org/buildbot/#/builders/18/builds/3247/steps/4/logs/stdio
In code added by https://github.com/llvm/llvm-project/issues/87471.
Commit: 4f130fa943af8bf47f4401deff0d825a91dc7584
https://github.com/llvm/llvm-project/commit/4f130fa943af8bf47f4401deff0d825a91dc7584
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M flang/lib/Frontend/CompilerInvocation.cpp
A flang/test/Driver/fno-openmp.f90
M flang/test/Driver/fopenmp.f90
Log Message:
-----------
[flang][Driver] support -fno-openmp (#107087)
Closes #83148
Commit: 5818337765e4c74918a700a14df5f64a658c47ee
https://github.com/llvm/llvm-project/commit/5818337765e4c74918a700a14df5f64a658c47ee
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-binop.ll
Log Message:
-----------
LICM: hoist BO assoc when (C1 op LV) op C2 (#106999)
Extend hoistBOAssociation to handle the "(C1 op LV) op C2" case, when op
is a commutative operand.
Commit: 5a6926ce49b6df807bff6083325ca291b0e731e5
https://github.com/llvm/llvm-project/commit/5a6926ce49b6df807bff6083325ca291b0e731e5
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
Log Message:
-----------
[AMDGPU] Fix test update after #107108
Commit: 360f82f3703fa57de42a2f998b172551f294e11a
https://github.com/llvm/llvm-project/commit/360f82f3703fa57de42a2f998b172551f294e11a
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Analysis/Lint.cpp
M llvm/test/Analysis/Lint/scalable.ll
Log Message:
-----------
[Lint] Fix crash for insert/extract on scalable vector
Don't assume the vector is fixed size. For scalable vectors, do
not report an error, as indices outside the minimum range may be
valid.
Commit: 6d3563422ce6f431b837221932d32db4c9681fc5
https://github.com/llvm/llvm-project/commit/6d3563422ce6f431b837221932d32db4c9681fc5
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/test/CodeGen/aarch64-neon-luti.c
Log Message:
-----------
include REQUIRES guard to aarch64-neon-luti.c (#107217)
Commit: cd46829e547d2d0aa3cb0ef7c9de59c507eaaecc
https://github.com/llvm/llvm-project/commit/cd46829e547d2d0aa3cb0ef7c9de59c507eaaecc
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
A llvm/test/Transforms/LoopVectorize/check-no-vectorize.ll
Log Message:
-----------
[LV] Fix emission of debug message in legality check (#101924)
Successful vectorization message is emitted even
after "Result" is false. "Result" = false indicates failure of one of
the legality check and thus
successful message should not be printed.
Commit: 7afdc6bd57d634354597df185fd7037bec9241ff
https://github.com/llvm/llvm-project/commit/7afdc6bd57d634354597df185fd7037bec9241ff
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abds.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/AArch64/abdu.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/X86/abds-neg.ll
M llvm/test/CodeGen/X86/abds.ll
M llvm/test/CodeGen/X86/abdu-neg.ll
M llvm/test/CodeGen/X86/abdu.ll
Log Message:
-----------
[DAG] Fix typo in i64/i128 abdu/abds tests
I'd incorrectly swapped the operands in some of the "cmp" test patterns when I changed the condition code
Commit: b25b9a7d6c872e42121aa024f362fae0b15dd72c
https://github.com/llvm/llvm-project/commit/b25b9a7d6c872e42121aa024f362fae0b15dd72c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/X86/abdu-neg.ll
M llvm/test/CodeGen/X86/abdu.ll
Log Message:
-----------
[DAG] visitSELECT - add "select usubo(x, y).overflow, (sub y, x), (usubo x, y) -> abdu(x, y)" fold (and neg equivalent)
Handle cases where CGP has merged the CMP+SUB into a USUBO node - improves a few outstanding niggles from #100810
Commit: 8d4235d97e5bd12b8244f9ffc157651a9a288b36
https://github.com/llvm/llvm-project/commit/8d4235d97e5bd12b8244f9ffc157651a9a288b36
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Analysis/Lint.cpp
M llvm/test/Analysis/Lint/scalable.ll
Log Message:
-----------
[Lint] Fix another scalable vector crash
We also need to check that the memory access LocationSize is not
scalable.
Commit: 55a24738302eb9bb5bf458220deb20ddef60ce51
https://github.com/llvm/llvm-project/commit/55a24738302eb9bb5bf458220deb20ddef60ce51
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Transforms/Utils/InlineFunction.cpp
Log Message:
-----------
[CtxProf] Replace include with forward declaration (NFC)
This header is fairly expensive. Forward declare
PGOContextualProfile instead.
Commit: 43b8ae3cea7c0f45dc29479ba8024e0adae9d145
https://github.com/llvm/llvm-project/commit/43b8ae3cea7c0f45dc29479ba8024e0adae9d145
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lower-module-lds-zero-size-arr.ll
Log Message:
-----------
[AMDGPU][LDS] Pre-Commit tests for 'Fix dynamic LDS interaction with "amdgpu-no-lds-kernel-id" (#107091)
Commit: 9ba41031de105d7babf3ae53facd368f2b4e409f
https://github.com/llvm/llvm-project/commit/9ba41031de105d7babf3ae53facd368f2b4e409f
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/use-device-ptr-to-use-device-addr.f90
Log Message:
-----------
[OpenMP]Update use_device_clause lowering (#101703)
This patch updates the use_device_ptr and use_device_addr clauses to use
the mapInfoOps for lowering. This allows all the types that are handle
by the map clauses such as derived types to also be supported by the
use_device_clauses.
This is patch 1/2 in a series of patches.
Co-authored-by: Raghu Maddhipatla raghu.maddhipatla at amd.com
Commit: 2cf36f0293daf0fa28d5c7d5d3617660edf237e7
https://github.com/llvm/llvm-project/commit/2cf36f0293daf0fa28d5c7d5d3617660edf237e7
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
A mlir/test/Target/LLVMIR/openmp-target-use-device-nested.mlir
Log Message:
-----------
[OpenMP]Update use_device_clause lowering (#101707)
This patch updates the use_device_ptr and use_device_addr clauses to use
the mapInfoOps for lowering. This allows all the types that are handle
by the map clauses such as derived types to also be supported by the
use_device_clauses.
This is patch 2/2 in a series of patches.
Commit: 7330c9b033f29bd92b99db6282c0f71de64122ab
https://github.com/llvm/llvm-project/commit/7330c9b033f29bd92b99db6282c0f71de64122ab
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Lower/DirectivesCommon.h
Log Message:
-----------
[flang] Fix -Wunneeded-internal-declaration in DirectivesCommon.h (NFC)
/llvm-project/flang/lib/Lower/DirectivesCommon.h:910:1:
error: 'static' function 'peelOuterConvert' declared in header file should be declared 'static inline' [-Werror,-Wunneeded-internal-declaration]
peelOuterConvert(Fortran::semantics::SomeExpr &expr) {
^
1 error generated.
Commit: d94199c8ffba3f3895da7627d3dbbca62937310c
https://github.com/llvm/llvm-project/commit/d94199c8ffba3f3895da7627d3dbbca62937310c
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
Log Message:
-----------
[clang] Make lifetimebound and GSL analysis more coherent (#105884)
This allows clang to detect more use-after-free bugs (shown in the
#100549).
This relands the remaining change (removing the EnableLifetimeWarnings
flag) in https://github.com/llvm/llvm-project/pull/104906, with a proper
fix for the regression.
Fixes #100549
Commit: af1e59aea2ea7d07ece1f34621dda38c995826a3
https://github.com/llvm/llvm-project/commit/af1e59aea2ea7d07ece1f34621dda38c995826a3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
Log Message:
-----------
[SLP]Fix PR107037: correctly track origonal/modified after vectorizations reduced values
Need to correctly track reduced values with multiple uses in the same
reduction emission attempt. Otherwise, the number of the reuses might be
calculated incorrectly, and may cause compiler crash.
Fixes https://github.com/llvm/llvm-project/issues/107037
Commit: bb1b368e0ad3da98b4c51018bdbcd6a83d8e646d
https://github.com/llvm/llvm-project/commit/bb1b368e0ad3da98b4c51018bdbcd6a83d8e646d
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_faminmax.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/sve2-intrinsics-faminmax.ll
Log Message:
-----------
[AArch64] Implement intrinsics for SVE FAMIN/FAMAX (#99042)
This patch implements the following intrinsics:
* Floating-point absolute maximum (predicated)
svfloat16_t svamax[_f16]_m(svbool_t, svfloat16_t, svfloat16_t);
svfloat16_t svamax[_f16]_x(svbool_t, svfloat16_t, svfloat16_t);
svfloat16_t svamax[_f16]_z(svbool_t, svfloat16_t, svfloat16_t);
svfloat16_t svamax[_n_f16]_m(svbool_t, svfloat16_t, float16_t);
svfloat16_t svamax[_n_f16]_x(svbool_t, svfloat16_t, float16_t);
svfloat16_t svamax[_n_f16]_z(svbool_t, svfloat16_t, float16_t);
* Floating-point absolute minimum (predicated)
svfloat16_t svmin[_f16]_m(svbool_t, svfloat16_t, svfloat16_t);
svfloat16_t svmin[_f16]_x(svbool_t, svfloat16_t, svfloat16_t);
svfloat16_t svmin[_f16]_z(svbool_t, svfloat16_t, svfloat16_t);
svfloat16_t svmin[_n_f16]_m(svbool_t, svfloat16_t, float16_t);
svfloat16_t svmin[_n_f16]_x(svbool_t, svfloat16_t, float16_t);
svfloat16_t svmin[_n_f16]_z(svbool_t, svfloat16_t, float16_t);
All the intrinsics have also variants for `f32` and `f64`, and have the
`__arm_streaming` attribute.
(cf. https://github.com/ARM-software/acle/pull/324)
Commit: c2b92a4250b3f514685676ba8985ea73450f14d3
https://github.com/llvm/llvm-project/commit/c2b92a4250b3f514685676ba8985ea73450f14d3
Author: Bartłomiej Chmiel <bachm44 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
Log Message:
-----------
[SROA] Use SetVector for PromotableAllocas (#105809)
Use SetVector to make operations more efficient
if there is a very large number of allocas.
Commit: d65ff3e9364536f9e0bd5f1c1bace626c256a2ad
https://github.com/llvm/llvm-project/commit/d65ff3e9364536f9e0bd5f1c1bace626c256a2ad
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/empty-struct.ll
Log Message:
-----------
[SLP]Fix PR107198: add a check for empty complex type
Need to check if the complex type is empty before trying to dig in,
trying to find vectorizable type
Fixes https://github.com/llvm/llvm-project/issues/107198
Commit: 26645ae2eea00456d98b497f348426c375409ce4
https://github.com/llvm/llvm-project/commit/26645ae2eea00456d98b497f348426c375409ce4
Author: Menooker <yijie.mei at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
M mlir/test/Transforms/buffer-results-to-out-params-elim.mlir
Log Message:
-----------
[mlir][memref] Fix hoist-static-allocs option of buffer-results-to-out-params when function parameters are returned (#102093)
buffer-results-to-out-params pass will have a nullptr-referencing error
when hoist-static-allocs option is on, when the return value of a
function is a parameter of the function. This PR fixes this issue.
Commit: 6238159e886baca5ebf31fd6b15d79db30ced889
https://github.com/llvm/llvm-project/commit/6238159e886baca5ebf31fd6b15d79db30ced889
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
Log Message:
-----------
[CodeGen][NewPM] Fix linker error due to dummy `MachineVerifierPass` (#107237)
Forgot to remove the dummy registry in `MachinePassRegistry.def`.
Commit: df5840f9f09280a33923f119db5a82e0cda3622d
https://github.com/llvm/llvm-project/commit/df5840f9f09280a33923f119db5a82e0cda3622d
Author: Aarni Koskela <akx at iki.fi>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[AMDGPU][Docs] Update product names for some targets (#106973)
Based on
https://rocm.docs.amd.com/projects/install-on-linux/en/latest/reference/system-requirements.html#supported-gpus.
Commit: 205f7ee737f75e666f70ad51bda5f778c02ab124
https://github.com/llvm/llvm-project/commit/205f7ee737f75e666f70ad51bda5f778c02ab124
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Analysis/Lint.cpp
A llvm/test/Analysis/Lint/noalias-null.ll
Log Message:
-----------
[Lint] Skip null args when checking noalias
Do not emit a warning if there are two null noalias arguments,
as they cannot be dereferenced anyway.
This is a common pattern for `@.omp_outlined`, which has some
optional noalias arguments.
Commit: 3d53212f6104c27df5097301587ece69db9c007e
https://github.com/llvm/llvm-project/commit/3d53212f6104c27df5097301587ece69db9c007e
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lld/COFF/InputFiles.cpp
A lld/test/COFF/arm64ec-import.test
Log Message:
-----------
[LLD][COFF] Initial support for ARM64EC importlibs. (#107164)
Use demangled symbol name for __imp_ symbols and define demangled thunk
symbol as AMD64 thunk.
Commit: f11915153761e0c2691945add795c891e63c0c4a
https://github.com/llvm/llvm-project/commit/f11915153761e0c2691945add795c891e63c0c4a
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
Log Message:
-----------
IVDescriptors: improve readability of a function (NFC) (#106219)
Avoid dereferencing operand to llvm::isa.
Commit: 4552153c37e04def01e99e32c02eab245d92b753
https://github.com/llvm/llvm-project/commit/4552153c37e04def01e99e32c02eab245d92b753
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/MachineCSE.cpp
Log Message:
-----------
[CodeGen][MachineCSE] Remove unused AA results(NFC) (#106604)
Alias Analysis result is never used in this pass
and hence removing it.
Commit: 028174aa2c3a9447aca3333e45b5f89e652b74d1
https://github.com/llvm/llvm-project/commit/028174aa2c3a9447aca3333e45b5f89e652b74d1
Author: Paul T Robinson <paul.robinson at sony.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/test/CodeGenCXX/debug-info-lambda-this.cpp
Log Message:
-----------
[DebugInfo] Make a test more robust (#106463)
This was accidentally matching a metadata record that happend to have
three elements, but wasn't the record of interest. Add CHECKs to make
sure we've found the correct record.
Commit: 6c143a86cddbc6d0431dd643bfc7d4f017042512
https://github.com/llvm/llvm-project/commit/6c143a86cddbc6d0431dd643bfc7d4f017042512
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A llvm/include/llvm/CodeGen/MachineCSE.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir
M llvm/test/CodeGen/AArch64/sve-pfalse-machine-cse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
M llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
M llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir
M llvm/test/CodeGen/Thumb/machine-cse-physreg.mir
M llvm/test/CodeGen/X86/cse-two-preds.mir
M llvm/test/DebugInfo/MIR/X86/machine-cse.mir
Log Message:
-----------
[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)
Commit: 7732d8e51819416b9d28b1815bdf81d0e0642b04
https://github.com/llvm/llvm-project/commit/7732d8e51819416b9d28b1815bdf81d0e0642b04
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT] Deprecate DenseMap::FindAndConstruct (#107224)
I've migrated all uses of FindAndConstruct to operator[] and
try_emplace. This patch inlines FindAndConstruct into operator[] and
deprecates FindAndConstruct.
Commit: 1b0a80249399dadfe0c3f682fff77bf9eb666535
https://github.com/llvm/llvm-project/commit/1b0a80249399dadfe0c3f682fff77bf9eb666535
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
Log Message:
-----------
[GDBRemote] Handle 'heap' memory region info type (#105883)
This should cause the memory region info "is stack" field to be set to
"no".
Commit: 30f1cfb4d0784de869ab3a4a9774b696b9769093
https://github.com/llvm/llvm-project/commit/30f1cfb4d0784de869ab3a4a9774b696b9769093
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/TableGen/Record.h
M llvm/lib/TableGen/DetailedRecordsBackend.cpp
M llvm/lib/TableGen/Record.cpp
Log Message:
-----------
[TableGen] Print memory stats in detailed record emitter (#106990)
Print memory allocation and related statistics when dumping detailed
record information.
Commit: e64ef634bbd940dfaae23d9fb43e6385014ffd10
https://github.com/llvm/llvm-project/commit/e64ef634bbd940dfaae23d9fb43e6385014ffd10
Author: Malek Ben Slimane <85631834+malek203 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/Analysis/ThreadSafety.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
Log Message:
-----------
Thread Safety Analysis: Differentiate between lock sets at real join points and expected/actual sets at function end (#105526)
This fixes false positives related to returning a scoped lockable
object. At the end of a function, we check managed locks instead of
scoped locks.
At real join points, we skip checking managed locks because we assume
that the scope keeps track of its underlying mutexes and will release
them at its destruction. So, checking for the scopes is sufficient.
However, at the end of a function, we aim at comparing the expected and
the actual lock sets. There, we skip checking scoped locks to prevent to
get duplicate warnings for the same lock.
Commit: 8f77d37f256809766fd83a09c6d144b785e9165a
https://github.com/llvm/llvm-project/commit/8f77d37f256809766fd83a09c6d144b785e9165a
Author: Princeton Ferro <pferro at nvidia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAGCombiner] cache negative result from getMergeStoreCandidates() (#106949)
Cache negative search result from getStoreMergeCandidates() so that
mergeConsecutiveStores() does not iterate quadratically over a
potentially long sequence of unmergeable stores.
Commit: 3bc38fb27a12f785d8e78b8d00cbd277464ace92
https://github.com/llvm/llvm-project/commit/3bc38fb27a12f785d8e78b8d00cbd277464ace92
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/phi-select-constant.ll
Log Message:
-----------
[InstCombine] Generalize and consolidate phi translation check (#106051)
The foldOpIntoPhi() transforms requires all operands to be
phi-translatable. This can be the case either because they are phi nodes
in the same block, or because the operand dominates the block.
Currently, most callers of foldOpIntoPhi() satisfy this pre-condition by
requiring a constant operand, which trivially dominates everything. Only
selects had handling for variable operands.
Move this logic into foldOpIntoPhi(), so things are handled correctly if
other callers are generalized. Also make the implementation a bit more
general by querying the dominator tree.
Commit: 75dc9af1a227e5bfd34eeaf822d2db4520545f14
https://github.com/llvm/llvm-project/commit/75dc9af1a227e5bfd34eeaf822d2db4520545f14
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Remove some dead code + reorder calls to avoid extra checks
Commit: f7fa75b20835254c35baeff908b8c3827c13db41
https://github.com/llvm/llvm-project/commit/f7fa75b20835254c35baeff908b8c3827c13db41
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_faminmax.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
A llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
Log Message:
-----------
[AArch64] Implement intrinsics for SME2 FAMIN/FAMAX (#99063)
This patch implements these intrinsics:
``` c
// Variants are also available for:
// [_f32_x2], [_f64_x2],
// [_f16_x4], [_f32_x4], [_f64_x4]
svfloat16x2_t svamax[_f16_x2](svfloat16x2 zd, svfloat16x2_t zm) __arm_streaming;
svfloat16x2_t svamin[_f16_x2](svfloat16x2 zd, svfloat16x2_t zm) __arm_streaming;
```
(cf. https://github.com/ARM-software/acle/pull/324)
Co-authored-by: Caroline Concatto <caroline.concatto at arm.com>
Commit: 660e34fd38c3fb39fba1871bbf5b2eb3a48bf277
https://github.com/llvm/llvm-project/commit/660e34fd38c3fb39fba1871bbf5b2eb3a48bf277
Author: Alexey Merzlyakov <60094858+AlexeyMerzlyakov at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
M lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
M lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
M lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
R lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.gpr_fpr.core
A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.gpr_fpr.out
A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.gpr_only.core
A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.gpr_only.out
R lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
A lldb/test/API/functionalities/postmortem/elf-core/main_fpr.c
Log Message:
-----------
[lldb][RISCV] Support optionally disabled FPR for riscv64 (#104547)
The PR adds the support optionally enabled/disabled FP-registers to LLDB
`RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V
builds having no FP-registers, like RV64IMAC or RV64IMACV.
To aim this, patch adds `opt_regsets` flags mechanism. It re-works
RegisterInfo class to work with flexibly allocated (depending on
`opt_regsets` flag) `m_register_sets` and `m_register_infos` vectors
instead of statically defined structures. The registration of regsets is
being arranged by `m_per_regset_regnum_range` map.
The patch flows are spread to `NativeRegisterContextLinux_riscv64` and
`RegisterContextCorePOSIX_riscv64` classes, that were tested on:
- x86_64 host working with coredumps
- RV64GC and RV64IMAC targets working with coredumps and natively in
run-time with binaries
`EmulateInstructionRISCV` is out of scope of this patch, and its
behavior did not change, using maximum set of registers.
According testcase built for RV64IMAC (no-FPR) was added to
`TestLinuxCore.py`.
Commit: 2d7339ad24b41eb06c417f7067b9fbeb4fdb2e6b
https://github.com/llvm/llvm-project/commit/2d7339ad24b41eb06c417f7067b9fbeb4fdb2e6b
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/test/CodeGen/AMDGPU/lower-module-lds-zero-size-arr.ll
Log Message:
-----------
[AMDGPU][LDS] Fix dynamic LDS interaction with "amdgpu-no-lds-kernel-id" (#107092)
Dynamic lds and Table lds both use the amdgpu_lds_kernel_id intrinsic.
Kernels and functons that make an indirect use of this should not have
the
"amdgpu-no-lds-kernel-id" attribute.
For the later, this was done. For the dynamic lds case, this was
missing. This patch fixes it.
Commit: 865edb0436bc55a3df3596eefb9a83050a5c7a96
https://github.com/llvm/llvm-project/commit/865edb0436bc55a3df3596eefb9a83050a5c7a96
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
Log Message:
-----------
[mlir][ArmSME] Fix typo (NFC)
Commit: ba40737e819b4ca77b25c0950c47c305a15a93de
https://github.com/llvm/llvm-project/commit/ba40737e819b4ca77b25c0950c47c305a15a93de
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M libcxx/include/__type_traits/result_of.h
Log Message:
-----------
[libc++][modules] Include __type_traits/invoke.h from __type_traits/result_of.h (#106796)
The result_of trait requires the __invoke_of implementation detail, but
that is defined under __type_traits, not under __functional. Include the
right header directly to remove a dependency from __type_traits to
__functional.
Commit: d9019d478d40b4e8766efccdb3eb1ff77cdbfaec
https://github.com/llvm/llvm-project/commit/d9019d478d40b4e8766efccdb3eb1ff77cdbfaec
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M libcxx/include/__math/hypot.h
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++] Remove unused pair.h include from hypot.h (#106798)
This was added in #100820 by mistake since the final version of that PR
didn't depend on std::pair anymore.
Commit: 7a785d46d6c31937c620f186464fdc59c265b4bf
https://github.com/llvm/llvm-project/commit/7a785d46d6c31937c620f186464fdc59c265b4bf
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M libcxx/include/__fwd/array.h
M libcxx/include/span
Log Message:
-----------
[libc++][modules] Use inline variable instead of true_type (#106797)
This allows breaking up a dependency from __fwd/array.h onto
__type_traits, which is a circular dependency once __type_traits becomes
a module of its own. This is also a small consistency improvement since
we've been using inline variables for traits like this elsewhere in the
library.
Commit: c1a8283fcc735b1567c49bb6cd485f9e71a12cc4
https://github.com/llvm/llvm-project/commit/c1a8283fcc735b1567c49bb6cd485f9e71a12cc4
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
A libcxx/include/__memory/noexcept_move_assign_container.h
R libcxx/include/__type_traits/noexcept_move_assign_container.h
M libcxx/include/module.modulemap
M libcxx/include/string
M libcxx/include/vector
Log Message:
-----------
[libc++][modules] Move __noexcept_move_assign_container out of __type_traits (#107140)
That header depends on allocator traits, which is fundamentally tied to
`<memory>`, not to `<type_traits>`. This breaks a cycle betweeen
__type_traits and __memory.
Commit: 3d9abfc9f841b13825e3d03cfba272f5eeab9a3b
https://github.com/llvm/llvm-project/commit/3d9abfc9f841b13825e3d03cfba272f5eeab9a3b
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
Consolidate all IR logic for getting the identity value of a reduction [nfc]
This change merges the three different places (at the IR layer) for
finding the identity value of a reduction into a single copy. This
depends on several prior commits which fix ommissions and bugs in
the distinct copies, but this patch itself should be fully
non-functional.
As the new comments and naming try to make clear, the identity value
is a property of the @llvm.vector.reduce.* intrinsic, not of e.g.
the recurrence descriptor. (We still provide an interface for
clients using recurrence descriptors, but the implementation simply
translates to the intrinsic which each corresponds to.)
As a note, the getIntrinsicIdentity API does not support fminnum/fmaxnum
or fminimum/fmaximum which is why we still need manual logic (but at
least only one copy of manual logic) for those cases.
Commit: 3ebd79751f2d5e1c54047409865c051daba0a21b
https://github.com/llvm/llvm-project/commit/3ebd79751f2d5e1c54047409865c051daba0a21b
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
Log Message:
-----------
[MLIR][ROCDL] Remove patterns for ops supported as intrinsics in the AMDGPU backend (#102971)
This patch removes patterns for a few operations which allows mathToLLVM
conversion to convert the operations into LLVM intrinsics instead since
they are supported directly by the AMDGPU backend.
Commit: fe454b2044aba1d808cec486a8ca7a0e202d31bf
https://github.com/llvm/llvm-project/commit/fe454b2044aba1d808cec486a8ca7a0e202d31bf
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port c1a8283fcc73
Commit: c81b43074ab010d01ad794224dd9dd22bbe8a1f7
https://github.com/llvm/llvm-project/commit/c81b43074ab010d01ad794224dd9dd22bbe8a1f7
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/CUDA/cuda-kernel-loop-directive.cuf
Log Message:
-----------
[flang][cuda] Fix lowering of cuf kernel with unstructured nested construct (#107149)
Lowering was crashing when cuf kernels has an unstructured construct.
Blocks created by PFT need to be re-created inside of the operation like
it is done for OpenACC construct.
Commit: 0367305af849da7ee9237fd83c04ed3a01e8d223
https://github.com/llvm/llvm-project/commit/0367305af849da7ee9237fd83c04ed3a01e8d223
Author: mzukovec <113346157+mzukovec at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A lld/test/wasm/Inputs/allow-multiple-definition.s
A lld/test/wasm/allow-multiple-definition.s
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/Options.td
M lld/wasm/SymbolTable.cpp
Log Message:
-----------
[lld][WebAssembly] Add allow-multiple-definition flag (#97699)
Add `allow-multiple-definition` flag to `wasm-ld`. This follows the ELF
linker logic. In case of duplication, the first symbol met is used.
This PR resolves the #97543
Commit: 697bc748f97736b294dd85b8f78530d023557b72
https://github.com/llvm/llvm-project/commit/697bc748f97736b294dd85b8f78530d023557b72
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M flang/include/flang/Frontend/TargetOptions.h
M flang/include/flang/Tools/TargetSetup.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
Allow disabling of types from the command line (#107126)
Adding hidden options to disable types through the
`TargetCharacteristics`. I am seeing issues when I do this
programmatically and would like, for anyone, to have the ability to
reproduce them for development and testing purposes.
I am planning to file a couple of issues following this patch.
Commit: 776495987272294de6aafbe73dab3e9ab445227a
https://github.com/llvm/llvm-project/commit/776495987272294de6aafbe73dab3e9ab445227a
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Config/BUILD.gn
Log Message:
-----------
[gn/mac] bump HOST_LINK_VERSION to 520
With this, clang will pass -platform_version instead of
-mmacosx_version_min to the linker. Recent versions of the linker
complain that the flag is now spelled mmacos_version_min (without
the x), and this supresses that warning.
520 is over 4 years old by now, so just changing this unconditionally
seems fine.
Commit: c537dd9375156c2aa3cd1bfaee88af7c492359d5
https://github.com/llvm/llvm-project/commit/c537dd9375156c2aa3cd1bfaee88af7c492359d5
Author: Reid Kleckner <rnk at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/test/CodeGenCXX/microsoft-abi-template-static-init.cpp
Log Message:
-----------
[MS] Put dllexported inline global initializers in a comdat (#107154)
Follow-up to c19f4f8069722f6804086d4438a0254104242c46 to handle corner
case of exported inline variables.
Should fix #56485
Commit: 7e03753539baaaa7a5cc29da3c0dc4d2f6df3b58
https://github.com/llvm/llvm-project/commit/7e03753539baaaa7a5cc29da3c0dc4d2f6df3b58
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaType.cpp
A clang/test/Sema/attr-btf_type_tag.cpp
M clang/test/SemaCXX/sugar-common-types.cpp
M clang/test/SemaCXX/type-traits.cpp
Log Message:
-----------
Disallow btf_type_tag in C++ mode (#107238)
This was always intended to be disallowed in C++ (see the definition in
Attr.td), but failed to add the correct checking code in SemaType.cpp to
ensure it was rejected.
Fixes #106864
Commit: accf90e16410468a2fa1ad9d1320f33fcc4cdd79
https://github.com/llvm/llvm-project/commit/accf90e16410468a2fa1ad9d1320f33fcc4cdd79
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/pull-conditional-binop-through-shift.ll
Log Message:
-----------
[X86] pull-conditional-binop-through-shift.ll - replace X32 check prefixes with X86
We tend to use X32 only for gnux32 testing
Commit: b2223b4d7efa4ed003a1b3ce7439106ddc63125f
https://github.com/llvm/llvm-project/commit/b2223b4d7efa4ed003a1b3ce7439106ddc63125f
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
R llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.mir
A llvm/test/CodeGen/WebAssembly/exception-legacy.mir
R llvm/test/CodeGen/WebAssembly/exception.mir
Log Message:
-----------
[WebAssembly] Rename legacy EH mir tests (#107189)
We added `-legacy` suffix to the legacy EH `ll` tests in #107166 but
forgot to do the same for `mir` tests.
Commit: 32bc670609fe9c938bca5b3c0e70e6b3934b4641
https://github.com/llvm/llvm-project/commit/32bc670609fe9c938bca5b3c0e70e6b3934b4641
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
Log Message:
-----------
[WebAssembly] Misc. fixes in CFGStackify (NFC) (#107182)
This contains misc. small fixes in CFGStackify. Most of them are comment
fixes and variable name changes. Two code changes are removing the cases
that can never occur. Another is extracting a routine as a lambda
function. I will add explanations inline in the code as Github comments.
Commit: 26ba186bd0a22fac7d08ed566b00c03236b6b7a9
https://github.com/llvm/llvm-project/commit/26ba186bd0a22fac7d08ed566b00c03236b6b7a9
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
M llvm/test/CodeGen/PowerPC/load-and-splat.ll
M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
M llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
M llvm/test/CodeGen/PowerPC/test-vector-insert.ll
M llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll
Log Message:
-----------
[PowerPC] Improve pwr7 codegen for v4i8 load (#104507)
There are no partial vector loads on pwr7 so current v4i8 codegen is an
int load then store to vector sized temp and re-load as vector. Try to
use lfiwax to load 32 bits into an FP reg and take advantage of VSX FP
and vector reg sharing to move the result to the right vector position.
Commit: a724f9a7e5d46c9bf49c7b5e207f792fb5214c10
https://github.com/llvm/llvm-project/commit/a724f9a7e5d46c9bf49c7b5e207f792fb5214c10
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
R llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
A llvm/test/Transforms/SLPVectorizer/reduction-whole-regs-loads.ll
Log Message:
-----------
[SLP][NFC]Make whole reg non-power-2 test for x86 and aarch64 along with risc-v
Commit: 2092f3527ed743a8fb9e0858c839cd4b26907f2a
https://github.com/llvm/llvm-project/commit/2092f3527ed743a8fb9e0858c839cd4b26907f2a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/reduction-whole-regs-loads.ll
Log Message:
-----------
[SLP][NFC]Remove unsupported attribute
Commit: 601645c3b70e2a17d18779a3a51b8bc9ecdc9aa6
https://github.com/llvm/llvm-project/commit/601645c3b70e2a17d18779a3a51b8bc9ecdc9aa6
Author: Reid Kleckner <rnk at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGDeclCXX.cpp
Log Message:
-----------
[clang] Fix FIXME in dynamic initializer emission, NFCI
This potentially affects platforms that support comdats other than ELF,
COFF, or wasm, but that is the intention of the FIXME, and if they don't
want this behavior, they probably shouldn't advertise comdat support.
Commit: 9a2fd97d391caf1060e303f636d7113501788d2f
https://github.com/llvm/llvm-project/commit/9a2fd97d391caf1060e303f636d7113501788d2f
Author: Florian Mayer <fmayer at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/mem-attr.ll
Log Message:
-----------
Reapply^2 "[HWASan] remove incorrectly inferred attributes" (#106622) (#106816)
This reverts commit 66927fb95abef9327b453d7213c5df7d641269be.
Filter functions this applies to, which I initially wanted to do in a
follow up to make reverts easier, but turns out without that it gets
really slow
Fleetbench proto: no significant movement
Fleetbench hashing: no significant movement
Fleetbench libc: no significant movement
2nd stage LLVM build:
https://lab.llvm.org/buildbot/#/builders/55/builds/1765/steps/9/logs/stdio
after this change: 80833.56user 3303.04system
previous build: 78430.21user 3258.04system
Commit: 4228e28293458e6ec49bd5487210719ff33c319a
https://github.com/llvm/llvm-project/commit/4228e28293458e6ec49bd5487210719ff33c319a
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/generic09.f90
Log Message:
-----------
[flang] Fix crash in semantics (#106158)
Semantics crashes when merging a USE-associated derived type with a
local generic procedure interface of the same name. (The other direction
works.)
Commit: 6facf6981488700c1554dcce36d4ac774a91d568
https://github.com/llvm/llvm-project/commit/6facf6981488700c1554dcce36d4ac774a91d568
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/runtime/random.cpp
Log Message:
-----------
[flang][runtime] Correct RANDOM_INIT seed generation (#106250)
The initial seed was generated from a bitwise AND ("&") of two
clock-generated values, instead of an XOR or (best) a truncated integer
multiplication. Maybe I mistyped a shift-7 instead of a shift-6 or
shift-8 when I wrote that line, but it was most likely just stupidity.
Fixes https://github.com/llvm/llvm-project/issues/106221.
Commit: 9e53e77265769f1916d8c4fd8ed8263798e8e815
https://github.com/llvm/llvm-project/commit/9e53e77265769f1916d8c4fd8ed8263798e8e815
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/include/flang/Evaluate/integer.h
M flang/include/flang/Runtime/descriptor.h
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/tools.cpp
M flang/unittests/Runtime/Reduction.cpp
M flang/unittests/Runtime/Transformational.cpp
Log Message:
-----------
[flang] Fix warnings from more recent GCCs (#106567)
While experimenting with some more recent C++ features, I ran into
trouble with warnings from GCC 12.3.0 and 14.2.0. These warnings looked
legitimate, so I've tweaked the code to avoid them.
Commit: 500f6cc25cb93607e9ea13732b791297acf8f97f
https://github.com/llvm/llvm-project/commit/500f6cc25cb93607e9ea13732b791297acf8f97f
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/include/flang/Runtime/cpp-type.h
M flang/include/flang/Runtime/numeric.h
M flang/runtime/numeric-templates.h
M flang/runtime/numeric.cpp
M flang/unittests/Runtime/Numeric.cpp
Log Message:
-----------
[flang][runtime] Support SPACING for REAL(2 & 3) (#106575)
Add runtime APIs for the intrinsic function SPACING for REAL kinds 2 & 3
in two ways: Spacing2 (& 3) for build environments with std::float16_t,
and Spacing2By4 (& 3By4) variants (for any build environment) which
compute SPACING for those types but accept and return their values as
32-bit floats.
SPACING for REAL(2) is needed by HDF5.
Commit: 143f3fc40279cbdafce190c5516c9dd74fc22ae5
https://github.com/llvm/llvm-project/commit/143f3fc40279cbdafce190c5516c9dd74fc22ae5
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Parser/prescan.cpp
A flang/test/Parser/non-breaking-space.f90
Log Message:
-----------
[flang] Accept a non-breaking space character in source (#106611)
Accept non-breaking space characters (Latin-1 '\xa0', UTF-8 '\xc2'
'\xa0') in source code, converting them into regular spaces in the
cooked character stream when not in character literals.
Commit: 840da2e8ba7e0f77938adfc6f6d315137542a1b8
https://github.com/llvm/llvm-project/commit/840da2e8ba7e0f77938adfc6f6d315137542a1b8
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Tracker.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
Log Message:
-----------
[SandboxIR] Implement CmpInst, FCmpInst, and ICmpInst (#106301)
As in the description.
Not sure the macros for "WRAP_XXX" add value or not, but do save some
boiler plate. Maybe there is a better way.
Commit: d1e4a2d300f7c0c6b681ddf719132c81d348aaab
https://github.com/llvm/llvm-project/commit/d1e4a2d300f7c0c6b681ddf719132c81d348aaab
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/include/flang/Semantics/expression.h
M flang/include/flang/Semantics/semantics.h
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/semantics.cpp
A flang/test/Semantics/smp-proc-ref.f90
Log Message:
-----------
[flang] Fix spurious error with separate module procedures (#106768)
When the implementation of one SMP apparently references another in what
might be a specification expression, semantics may need to resolve it as
a forward reference, and to allow for the replacement of a
SubprogramNameDetails place-holding symbol with the final
SubprogramDetails symbol. Otherwise, as in the bug report below,
confusing error messages may result.
(The reference in question isn't really in the specification part of a
subprogram, but due to the syntactic ambiguity between the array element
assignment statement and a statement function definition, it appears to
be so at the time that the reference is processed.)
I needed to make DumpSymbols() available via SemanticsContext to analyze
this bug, and left that new API in place to make things easier next
time.
Fixes https://github.com/llvm/llvm-project/issues/106705.
Commit: 1324789a65665c27eda9e04bc93db81cc859924c
https://github.com/llvm/llvm-project/commit/1324789a65665c27eda9e04bc93db81cc859924c
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Parser/prescan.cpp
M flang/test/Preprocessing/pp134.F90
Log Message:
-----------
[flang][preprocessor] Extend handling of line continuation replacements (#107010)
Codes using traditional C preprocessors will sometimes put a keyword
macro name in a free form continuation line in order to get macro
replacement of part of an identifier, as in
call subr_&
&N&
&(1.)
where N is a keyword macro. f18 already handles this case, but not when
there is white space between the macro name and the following
continuation marker character '&'. Allow white space to appear.
Fixes https://github.com/llvm/llvm-project/issues/106931.
Commit: 61759513c8166a6420ded480802de72859a45499
https://github.com/llvm/llvm-project/commit/61759513c8166a6420ded480802de72859a45499
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/IndirectCallPromotionAnalysis.h
Log Message:
-----------
[Analysis] Update getPromotionCandidatesForInstruction description (NFC) (#107277)
Updates the description for getPromotionCandidatesForInstruction to
reflect the cleanup done in #95624.
Commit: 6e60330af55bfdf5b34aed4c9197cd3afbf00498
https://github.com/llvm/llvm-project/commit/6e60330af55bfdf5b34aed4c9197cd3afbf00498
Author: Lei Wang <wlei at fb.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/include/llvm/Transforms/IPO/SampleProfileMatcher.h
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-stale-profile-toplev-func.prof
A llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-toplev-func.ll
Log Message:
-----------
[SampleFDO] Read call-graph matching recovered top-level function profile (#101053)
With extbinary profile format, initial profile loading only reads
profile based on current function names in the module. However, if a
function is renamed, sample loader skips to load its original
profile(which has a different name), we will miss this case. To address
this, we load the top-level profile candidate explicitly for the
matching. If a match is found later, the function profile will be
further preserved for use by the sample loader.
Commit: 2e0ded3371f8d42f376bdfd4d70687537e36818e
https://github.com/llvm/llvm-project/commit/2e0ded3371f8d42f376bdfd4d70687537e36818e
Author: R-Goc <131907007+R-Goc at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
A llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
Log Message:
-----------
[Windows SEH] Fix crash on empty seh block (#107031)
Fixes https://github.com/llvm/llvm-project/issues/105813 and
https://github.com/llvm/llvm-project/issues/106915.
Adds a check for the end of the iterator, which can be a sentinel.
The issue was introduced in
https://github.com/llvm/llvm-project/commit/0efe111365ae176671e01252d24028047d807a84
from what I can see, so along with the introduction of /EHa support.
Commit: 36c210bb340cfdc68d314dd188e18c0bf017b999
https://github.com/llvm/llvm-project/commit/36c210bb340cfdc68d314dd188e18c0bf017b999
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
Log Message:
-----------
[RISCV] Remove pre-assignment of mask vectors during call lowering. NFC (#107192)
The first mask vector operand is supposed to be assigned to V0. No other
vector types will be assigned to V0. We don't need to pre-assign, we can
just try V0 first for any mask vectors in the normal processing.
Commit: b30880e975279c1c8ef4c2645eb03063e4b19f2b
https://github.com/llvm/llvm-project/commit/b30880e975279c1c8ef4c2645eb03063e4b19f2b
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/SandboxIR/Tracker.cpp
Log Message:
-----------
[SandboxIR] Fix linking error caused by 840da2e8ba7e0f77938adfc6f6d315137542a1b8
Commit: a43137c3f85fd87f90c9a8ffaebd71d432018e79
https://github.com/llvm/llvm-project/commit/a43137c3f85fd87f90c9a8ffaebd71d432018e79
Author: Kyle Huey <khuey at kylehuey.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfFile.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfFile.h
A llvm/test/DebugInfo/Generic/debug-ranges-duplication.ll
Log Message:
-----------
[LLVM][DWARF] Make some effort to avoid duplicates in .debug_ranges. (#106614)
Inlining and zero-cost abstractions tend to produce volumes of debug
info with identical ranges. When built with full debugging information
(the equivalent of -g2) librustc_driver.so has 2.1 million entries in
.debug_ranges. But only 1.1 million of those entries are unique. While
in principle all duplicates could be eliminated with a hashtable,
checking to see if the new range is exactly identical to the previous
range and skipping a new addition if it is is sufficient to eliminate
99.99% of the duplicates. This reduces the size of librustc_driver.so's
.debug_ranges section by 35%, or the overall binary size a little more
than 1%.
Commit: c1667f909949d15c593e4a03a4e992cffa72ad3c
https://github.com/llvm/llvm-project/commit/c1667f909949d15c593e4a03a4e992cffa72ad3c
Author: Benoit Jacob <jacob.benoit.1 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp
M mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir
Log Message:
-----------
Fix `transpose->unpack` folding pattern for the partial-tile case of `unpack` (#107271)
Just directly create the empty tensor of appropriate shape instead of
relying on `UnPackOp::createDestinationTensor` which is trying to infer
the destination shape, which isn't possible in general with the set of
paramters that it is taking.
Signed-off-by: Benoit Jacob <jacob.benoit.1 at gmail.com>
Commit: ebf0599314e17c3ab89f303d452811b1db3e6d1e
https://github.com/llvm/llvm-project/commit/ebf0599314e17c3ab89f303d452811b1db3e6d1e
Author: SJW <48454132+sjw36 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
M mlir/test/Dialect/SCF/loop-pipelining.mlir
M mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
Log Message:
-----------
[MLIR][SCF] Add support for loop pipeline peeling for dynamic loops. (#106436)
Allow speculative execution and predicate results per stage.
Commit: 0fffdeb5f46078ddcc61e112cd38856b1165f050
https://github.com/llvm/llvm-project/commit/0fffdeb5f46078ddcc61e112cd38856b1165f050
Author: Ziqing Luo <ziqing at udel.edu>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsage.h
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
A clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions-inline-namespace.cpp
A clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-test-unreachable.cpp
Log Message:
-----------
[-Wunsafe-buffer-usage] Warning Libc functions (#101583)
[-Wunsafe-buffer-usage] Add warn on unsafe calls to libc functions
Warning about calls to libc functions involving buffer access. Warned
functions are hardcoded by names.
(rdar://117182250)
Commit: f574b9c9297538a8d471658564619be3ad6e87dd
https://github.com/llvm/llvm-project/commit/f574b9c9297538a8d471658564619be3ad6e87dd
Author: Edd Dawson <edd.dawson at sony.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/test/Driver/ps4-sdk-root.c
M clang/test/Driver/ps5-sdk-root.c
Log Message:
-----------
[PS4,PS5][Driver] Check for absent SDK when -nostdlib/-nodefaultlibs (#107112)
The PlayStation drivers emit warnings if it looks like SDK libraries are
missing. Until this point, the check was skipped when either `-nostdlib`
or `-nodefaultlibs` was supplied. I believe the idea is that if you
aren't linking default libraries, you won't be in need of the SDK.
However, in a situation where these switches are supplied, users may
still want to pass `-lSomeSDKLib` to the driver/linker with the
expectation that libSomeSDKLib.a will be sourced from the SDK. That is,
`-nodefaultlibs` and `-nostdlib` affect the libraries passed to the
linker, but not the library search paths.
So this change removes `-nostdlib`/`-nodefaultlibs` from consideration
when deciding whether or not to probe for the SDK's existence.
N.B. complete behaviour for `-nostdlib` and `-nodefaultlibs` is yet to
be added to the PlayStation compiler drivers. Coming soon.
SIE tracker: TOOLCHAIN-16704
Commit: c50fecaaaabcf1598dc25fbde24c8352745b4ac9
https://github.com/llvm/llvm-project/commit/c50fecaaaabcf1598dc25fbde24c8352745b4ac9
Author: Ben Howe <141149032+bmhowe23 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Transforms/Utils/RegionUtils.cpp
M mlir/test/Transforms/canonicalize-block-merge.mlir
Log Message:
-----------
[mlir] Fix region simplification bug when later blocks use prior block argument values (#97960)
This fixes #94520 by ensuring that any if any block arguments are being
used outside of the original block that the block is not considered a
candidate for merging.
More details: the root cause of the issue described in #94520 was that
`^bb2` and `^bb5` were being merged despite `%4` (an argument to `^bb2`)
was being used later in `^bb7`. When the block merge occurred, that
unintentionally changed the value of `%4` for all downstream code. This
change prevents that from happening.
Commit: 34f2c9a9ce73a61b27d75dab7e1eed256491afcc
https://github.com/llvm/llvm-project/commit/34f2c9a9ce73a61b27d75dab7e1eed256491afcc
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A llvm/test/Analysis/CostModel/AArch64/vec3-fp-conversions.ll
Log Message:
-----------
[AArch64] Add tests for FP conversion with 3 element vectors.
Add tests showing a number of cases where costs for floating point
conversions are overestimated for vectors with 3 elements.
Commit: 3fe6a064f15cd854fd497594cc20e8b680cd2133
https://github.com/llvm/llvm-project/commit/3fe6a064f15cd854fd497594cc20e8b680cd2133
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
Log Message:
-----------
[LV] Check if compare is truncated directly in getInstructionCost.
The current check for truncated compares in getInstructionCost misses
cases where either the first or both operands are constants.
Check directly if the compare is marked for truncation. In that case,
the minimum bitwidth is that of the operands.
The patch also adds asserts to ensure that.
This fixes a divergence between legacy and VPlan-based cost model, where
the legacy cost model incorrectly estimated the cost of compares with
truncated operands.
Fixes https://github.com/llvm/llvm-project/issues/107171.
Commit: 42b4092db99633ec53d136d5da7abfcfb236c14e
https://github.com/llvm/llvm-project/commit/42b4092db99633ec53d136d5da7abfcfb236c14e
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
Log Message:
-----------
[RISCV] Precommit vmv.v.v with undef passthru tests
Commit: d21e731c42d6b967e29dbe2edc16c1b86885df0d
https://github.com/llvm/llvm-project/commit/d21e731c42d6b967e29dbe2edc16c1b86885df0d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Fix typos in comment. NFC
Commit: 23f6c3370b8bc0bf773e69a41bf90454c0a10120
https://github.com/llvm/llvm-project/commit/23f6c3370b8bc0bf773e69a41bf90454c0a10120
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M libcxx/include/__math/hypot.h
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++][modules] Remove dependency on __algorithm/max from hypot.h (#107150)
That dependency was added recently when we made improvements to
std::hypot, but that resulted in `__math` depending on `__algorithm`,
which is a very heavyweight module. This patch uses `__math::fmax`
instead.
Commit: 5e19fd172063c8957a35c7fa3596620f79ebba97
https://github.com/llvm/llvm-project/commit/5e19fd172063c8957a35c7fa3596620f79ebba97
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M libcxx/include/__filesystem/directory_entry.h
M libcxx/include/__filesystem/path.h
M libcxx/include/__mdspan/layout_left.h
M libcxx/include/__mdspan/layout_right.h
M libcxx/include/__mdspan/layout_stride.h
M libcxx/include/module.modulemap
M libcxx/test/std/containers/views/mdspan/CustomTestLayouts.h
M libcxx/test/std/containers/views/mdspan/extents/comparison.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/conversion.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/ctad.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/dextents.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/dims.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/index_type.verify.cpp
M libcxx/test/std/containers/views/mdspan/extents/obs_static.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/types.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/comparison.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/ctor.default.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/ctor.extents.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/index_operator.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/required_span_size.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/static_requirements.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_left/stride.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/comparison.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/ctor.default.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/ctor.extents.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/index_operator.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/required_span_size.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/static_requirements.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_right/stride.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/comparison.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/ctor.default.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_array.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_span.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/ctor.strided_mapping.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/index_operator.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/required_span_size.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/static_requirements.pass.cpp
M libcxx/test/std/containers/views/mdspan/layout_stride/stride.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/assign.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/conversion.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.copy.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.default.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_integers.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/ctor.move.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/deduction.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/index_operator.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/move.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/properties.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/swap.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/types.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/test_offset_time_zone.h
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/string_view.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/string_view_local_time.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/string_view_local_time_choose.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/string_view_sys_time.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/string_view_zoned_time_duration2_time_zone_ptr2.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/string_view_zoned_time_duration2_time_zone_ptr2_choose.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/sys_time.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/time_zone_pointer.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/time_zone_pointer_local_time.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/time_zone_pointer_local_time_choose.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.ctor/time_zone_pointer_sys_time.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.members/get_local_time.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.members/get_sys_time.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.members/get_time_zone.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.members/operator_local_time.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.zonedtime/time.zone.zonedtime.members/operator_sys_time.pass.cpp
M libcxx/test/std/utilities/charconv/charconv.from.chars/integral.pass.cpp
M libcxx/test/std/utilities/charconv/charconv.from.chars/integral.roundtrip.pass.cpp
M libcxx/test/std/utilities/charconv/charconv.syn/from_chars_result.operator_bool.pass.cpp
M libcxx/test/std/utilities/charconv/charconv.syn/from_chars_result.pass.cpp
M libcxx/test/std/utilities/charconv/charconv.syn/to_chars_result.operator_bool.pass.cpp
M libcxx/test/std/utilities/charconv/charconv.syn/to_chars_result.pass.cpp
M libcxx/test/std/utilities/charconv/charconv.to.chars/integral.pass.cpp
Log Message:
-----------
[libc++][modules] Consolidate leaf modules into their own top-level modules (#107147)
Some modules are leaf modules in the sense that they are not used by any
other part of the headers. These leaf modules are easy to consolidate
since there is no risk to create a cycle. As a result of regrouping
these modules, several missing includes were found and fixed in this
patch.
Commit: 63da545ccdd41d9eb2392a8d0e848a65eb24f5fa
https://github.com/llvm/llvm-project/commit/63da545ccdd41d9eb2392a8d0e848a65eb24f5fa
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
Revert "Reland "AtomicExpand: Allow incrementally legalizing atomicrmw"" (#107307)
Reverts llvm/llvm-project#106793
`Next == E` is not enough:
https://lab.llvm.org/buildbot/#/builders/169/builds/2834
`Next` is deleted by `processAtomicInstr`
Commit: 52dc4918ca8b874ddd4e4fcad873a66ecc5b6953
https://github.com/llvm/llvm-project/commit/52dc4918ca8b874ddd4e4fcad873a66ecc5b6953
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M libcxx/test/libcxx/clang_modules_include.gen.py
M libcxx/test/libcxx/clang_tidy.gen.py
M libcxx/test/libcxx/double_include.gen.py
M libcxx/test/libcxx/header_inclusions.gen.py
M libcxx/test/libcxx/libcpp_version.gen.py
M libcxx/test/libcxx/no_assert_include.gen.py
M libcxx/test/libcxx/system_reserved_names.gen.py
M libcxx/test/libcxx/transitive_includes.gen.py
M libcxx/utils/adb_run.py
M libcxx/utils/ci/Dockerfile
M libcxx/utils/ci/apple-install-libcxx.sh
M libcxx/utils/ci/build-picolibc.sh
M libcxx/utils/ci/buildkite-pipeline.yml
M libcxx/utils/ci/run-buildbot
M libcxx/utils/ci/vendor/android/Dockerfile.emulator
M libcxx/utils/ci/vendor/android/build-emulator-images.sh
M libcxx/utils/ci/vendor/android/container-setup.sh
M libcxx/utils/ci/vendor/android/emulator-entrypoint.sh
M libcxx/utils/ci/vendor/android/emulator-functions.sh
M libcxx/utils/ci/vendor/android/emulator-wait-for-ready.sh
M libcxx/utils/ci/vendor/android/setup-env-for-emulator.sh
M libcxx/utils/ci/vendor/android/start-emulator.sh
M libcxx/utils/ci/vendor/android/stop-emulator.sh
M libcxx/utils/libcxx/test/android.py
Log Message:
-----------
[libc++][NFC] Use consistent layout for license in Python files
Most Python files were using `# === [...]` instead of `#=== [...]`
so I went with what was the most common in the codebase.
Commit: 16900d3b98e6c8fbdad4411a054e3566bbbf9235
https://github.com/llvm/llvm-project/commit/16900d3b98e6c8fbdad4411a054e3566bbbf9235
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-binop.ll
Log Message:
-----------
LICM: hoist BO assoc when BinOp is in RHS (#107072)
Extend hoistBOAssociation smoothly to handle the case when the inner
BinaryOperator is in the RHS of the outer BinaryOperator. This completes
the generalization of hoistBOAssociation, and the only limitation after
this patch is the fact that only Add and Mul are hoisted.
Commit: 1ff8657b26870e9db4527b621fab0d21b6cbdc3c
https://github.com/llvm/llvm-project/commit/1ff8657b26870e9db4527b621fab0d21b6cbdc3c
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/primary64.h
Log Message:
-----------
[scudo] Use variable instead of recomputing. (#106647)
In the get fragmentation functions, there is already a variable that
computes the
in use bytes, so use that instead of recomputing it.
Commit: dd754cd262222bcb489038ac791e4278d90697f0
https://github.com/llvm/llvm-project/commit/dd754cd262222bcb489038ac791e4278d90697f0
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M compiler-rt/lib/nsan/nsan.cpp
Log Message:
-----------
[compiler-rt][nsan] Update UnwindImpl (#107313)
Implement __sanitizer::BufferedStackTrace::UnwindImpl following msan.
Commit: dcf0160bd61d150e7b94067fcd991b466a361b08
https://github.com/llvm/llvm-project/commit/dcf0160bd61d150e7b94067fcd991b466a361b08
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/GetIntrinsicInfoTableEntriesBM.cpp
M llvm/lib/IR/Function.cpp
M llvm/utils/TableGen/IntrinsicEmitter.cpp
Log Message:
-----------
[TableGen] Optimize intrinsic info type signature encoding (#106809)
Change the "fixed encoding" table used for encoding intrinsic
type signature to use 16-bit encoding as opposed to 32-bit.
This results in both space and time improvements. For space,
the total static storage size (in bytes) of this info reduces by 50%:
- Current = 14193*4 (Fixed table) + 16058 + 3 (Long Table) = 72833
- New size = 14193*2 (Fixed table) + 19879 + 3 (Long Table) = 48268.
- Reduction = 50.9%
For time, with the added benchmark, we see a 7.3% speedup in
`GetIntrinsicInfoTableEntries` benchmark. Actual output of the
benchmark in included in the GitHub MR.
Commit: 660cc98647677815a3f5d97d00220071d8cf7a4f
https://github.com/llvm/llvm-project/commit/660cc98647677815a3f5d97d00220071d8cf7a4f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
M llvm/utils/TableGen/SearchableTableEmitter.cpp
Log Message:
-----------
[TableGen] Add `CodeGenIntrinsicsMap` for on-demand intrinsic creation (#107100)
- Add class `CodeGenIntrinsicMap` for on-demand creation of
`CodeGenIntrinsic`.
- Add class `CodeGenIntrinsicContext` to capture global information
required to build `CodeGenIntrinsic` objects.
- Adopt GlobalISel PatternParser and SearchableTableEmitter to use it.
Commit: 98c6bbfe1f3a348633e5e4c192a0134891fe3849
https://github.com/llvm/llvm-project/commit/98c6bbfe1f3a348633e5e4c192a0134891fe3849
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/test/TableGen/intrinsic-attrs.td
M llvm/test/TableGen/intrinsic-long-name.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/test/TableGen/searchabletables-intrinsic.td
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/IntrinsicEmitter.cpp
Log Message:
-----------
[TableGen] Refactor Intrinsics record (#106986)
Eliminate unused `isTarget` field in Intrinsic record.
Eliminate `isOverloaded`, `Types` and `TypeSig` fields from the record,
as they are already available through the `TypeInfo` field. Change
intrinsic emitter code to look for this info using fields of the
`TypeInfo` record attached to the `Intrinsic` record.
Fix several intrinsic related unit tests to source the `Intrinsic` class
def from Intrinsics.td as opposed to defining a skeleton in the test.
This eliminates some duplication of information in the Intrinsic class,
as well as reduces the memory allocated for record fields, resulting in
~2% reduction (though that's not the main goal).
Commit: df50751d24da4f5fdf8f46119c09a7e941f7174b
https://github.com/llvm/llvm-project/commit/df50751d24da4f5fdf8f46119c09a7e941f7174b
Author: vporpo <vporpodas at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantAggregateZero (#107172)
This patch implements sandboxir::ConstantAggregateZero mirroring
llvm::ConstantAggregateZero.
Commit: 9171881d64e4834de7ad7c9807607ce6bc5167a9
https://github.com/llvm/llvm-project/commit/9171881d64e4834de7ad7c9807607ce6bc5167a9
Author: Scott Linder <Scott.Linder at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[AMDGPU][Docs] DWARF aspace-aware base types (post-review fixes)
Commit: 7c4eb60c9509c3a750961eac2dbcaad369d911f2
https://github.com/llvm/llvm-project/commit/7c4eb60c9509c3a750961eac2dbcaad369d911f2
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
Log Message:
-----------
[Clang] Fix CLANG_TOOLCHAIN_PROGRAM_TIMEOUT logic
PR #102521, which landed as 1ea0865dd6fa, implemented
`CLANG_TOOLCHAIN_PROGRAM_TIMEOUT`, but the logic is obviously wrong.
If the user-specified value is negative, it should become zero to mean
infinite. Otherwise, it should be left as is. Thus, use `std::max`
not `std::min`. This obvious fixup doesn't seem worth another pull
request.
Commit: 950bb68516eb564c29815997450bdb6516ffdcec
https://github.com/llvm/llvm-project/commit/950bb68516eb564c29815997450bdb6516ffdcec
Author: vporpo <vporpodas at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantPointerNull (#107320)
This patch implements sandboxir::ConstantPointerNull mirroring
llvm::ConstantPointerNull.
Commit: 9efe377307694be0c92f7cb3b02fd1d090fdbeb8
https://github.com/llvm/llvm-project/commit/9efe377307694be0c92f7cb3b02fd1d090fdbeb8
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/AST/CXXRecordDeclDefinitionBits.def
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/SemaHLSL/Types/Traits/IsIntangibleType.hlsl
A clang/test/SemaHLSL/Types/Traits/IsIntangibleTypeErrors.hlsl
Log Message:
-----------
[HLSL] Implement '__builtin_hlsl_is_intangible' type trait (#104544)
Implements `__builtin_hlsl_is_intangible` type trait.
HLSL intangible types are special implementation-defined types such as
resource handles or samplers. Any class that is an array of intangible
type or contains base class or members of intangible types is also an
intangible type.
Fixes #[102954](https://github.com/llvm/llvm-project/issues/102954)
Commit: aecbc924102ee57ea639cd76ed32b37eb2d257fc
https://github.com/llvm/llvm-project/commit/aecbc924102ee57ea639cd76ed32b37eb2d257fc
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception-legacy.mir
M llvm/test/CodeGen/WebAssembly/function-info.mir
M llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
Log Message:
-----------
[WebAssembly] Rename CATCH/CATCH_ALL to *_LEGACY (#107187)
This renames MIR instruction `CATCH` and `CATCH_ALL` to `CATCH_LEGACY`
and `CATCH_ALL_LEGACY` respectively.
Follow-up PRs for the new EH (exnref) implementation will use `CATCH`,
`CATCH_REF`, `CATCH_ALL`, and `CATCH_ALL_REF` as pseudo-instructions
that return extracted values or `exnref` or both, because we don't
currently support block return values in LLVM. So to give the old (real)
`CATCH`es and the new (pseudo) `CATCH`es different names, this attaches
`_LEGACY` prefix to the old names.
This also rearranges `WebAssemblyInstrControl.td` so that the old legacy
instructions are listed all together at the end.
Commit: 23457964392d00fc872fa6021763859024fb38da
https://github.com/llvm/llvm-project/commit/23457964392d00fc872fa6021763859024fb38da
Author: ziqingluo-90 <ziqing_luo at apple.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsage.h
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
R clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions-inline-namespace.cpp
R clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-test-unreachable.cpp
Log Message:
-----------
Revert "[-Wunsafe-buffer-usage] Warning Libc functions (#101583)"
This reverts commit 0fffdeb5f46078ddcc61e112cd38856b1165f050.
Will re-land this commit soon with a way to opt-out
Commit: 1254259e325428c5912843aa94f6fc663a40ea1b
https://github.com/llvm/llvm-project/commit/1254259e325428c5912843aa94f6fc663a40ea1b
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c
Log Message:
-----------
[hwasan] Disable test with hwasan-aliasing
It's likely flaky because we tag the stack, which
is unsupported in this mode.
Commit: ef1ef03d4c1014d41713feb0c7edc4d0e36982f4
https://github.com/llvm/llvm-project/commit/ef1ef03d4c1014d41713feb0c7edc4d0e36982f4
Author: yonghong-song <yhs at fb.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/BPF/BPFInstrInfo.td
Log Message:
-----------
[BPF] Fix dst/val mismatch in class ATOMIC_NOFETCH (#107288)
All ATOMIC_NOFETCH insns have "$dst = $val" constraints. So let us
enforce "$dst = $val" having the same register type in ATOMIC_NOFETCH as
well.
Currently, things work since ATOMIC_NOFETCH does not have source code
pattern matching. I am experimenting to introduce memory ordering to
BPFInstrInfo.td file and pattern matching will be needed. Eventually,
for atomic_fetch_*() insns locked insns could be generated if memory
ordering is memory_order_relaxed.
[1] https://lore.kernel.org/bpf/7b941f53-2a05-48ec-9032-8f106face3a3@linux.dev/
Commit: c82a5496c80747981efb8d25ad8bc4d8c6785b2e
https://github.com/llvm/llvm-project/commit/c82a5496c80747981efb8d25ad8bc4d8c6785b2e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
Log Message:
-----------
[RISCV] Support fixed vector VP_LOAD/STORE for bf16 and f16 without Zvfh. (#107297)
This allows odd sized vector load/store to be legalized to a
VP_LOAD/STORE using EVL.
I changed the bf16 tests in fixed-vectors-load.ll and
fixed-vectors-store.ll to use an illegal type to be consistent with the
intent of these files. A legal type is already tested in
fixed-vectors-load-store.ll
Commit: b2048de55ea934b70902864767b0cc8dfada8be0
https://github.com/llvm/llvm-project/commit/b2048de55ea934b70902864767b0cc8dfada8be0
Author: Max Winkler <max.enrico.winkler at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/clang_f_opts.c
Log Message:
-----------
[Clang] [Driver] Support `-fjmc` for `*-windows-msvc` target in non cl driver modes (#107177)
Allow `-fjmc` to be used if the target triple is targeting msvc,
`*-windows-msvc`, irrelevant of the driver mode used.
In general the driver mode shouldn't control the target triple.
Also in our custom build system I am trying to just treat clang as
clang. This is because while the `cl` driver mode emulates msvc
interface quite well there are still a lot of operations that are just
clang specific.
The optimization modes do not map directly from msvc to clang.
Warnings do not map from msvc to clang.
Instead of wrapping options with `/clang:` when targeting `clang-cl.exe`
it is just easier to target the clang driver always irrelevant of the
target triple.
Commit: eb2929d323c0c44f2037cf8a345ca6984ec228eb
https://github.com/llvm/llvm-project/commit/eb2929d323c0c44f2037cf8a345ca6984ec228eb
Author: Xiang Li <python3kgae at outlook.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
A llvm/test/CodeGen/DirectX/ContainerData/RuntimeInfoCS.ll
Log Message:
-----------
[DirectX] use DXILMetadataAnalysis to build PSVRuntimeInfo (#107101)
Replace the hardcoded values for compute shader in
DXContainer::addPipelineStateValidationInfo.
Still missing wave size.
Add preserved for previous passes so the information is not lost.
Fix https://github.com/llvm/wg-hlsl/issues/51
Commit: c28b1a19aadff97b369889aee084073a181cfda8
https://github.com/llvm/llvm-project/commit/c28b1a19aadff97b369889aee084073a181cfda8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
Log Message:
-----------
[LegalizeTypes][RISCV] Use SPLAT_VECTOR_PARTS to legalize splat BUILD_VECTOR (#107290)
If the element type needs to be expanded, we can use SPLAT_VECTOR_PARTS
if the target supports it.
There's already a DAGCombine to turn BUILD_VECTOR into SPLAT_VECTOR if
the target makes SPLAT_VECTOR legal, but it doesn't fire for vectors
that need to be split.
Commit: c2fc33204caca8c52b27425255bbc78c9e4d99e4
https://github.com/llvm/llvm-project/commit/c2fc33204caca8c52b27425255bbc78c9e4d99e4
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Semantics/check-io.cpp
M flang/module/__fortran_builtins.f90
A flang/test/Lower/CUDA/cuda-devptr.cuf
Log Message:
-----------
[flang][cuda] Add c_devptr and bypass output semantic check (#107318)
Add a builtin type for c_devptr since it will need some special handling
for some function like c_f_pointer.
`c_ptr` is defined as a builtin type and was raising a semantic error if
you try to use it in a I/O statement. This patch add a check for c_ptr
and c_devptr to bypass the semantic check and allow the variables of
these types to be used in I/O.
Commit: aad699776496a80af5e062b446fe26a4313ff3e3
https://github.com/llvm/llvm-project/commit/aad699776496a80af5e062b446fe26a4313ff3e3
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
Log Message:
-----------
[RISCV] Fold PseudoVMV_V_V with undef passthru, handling policy (#106943)
If a vmv.v.v has an undef passthru then we can just replace it with its
input operand, since the tail is completely undefined.
This is a reattempt of #106840, but also checks to see if the input was
a pseudo where we can relax its tail policy to undef.
This also means we don't need to check for undef passthrus in
foldVMV_V_V anymore because they will be handled by
foldUndefPassthruVMV_V_V.
Commit: ad89e617c703239518187912540b8ea811dc2eda
https://github.com/llvm/llvm-project/commit/ad89e617c703239518187912540b8ea811dc2eda
Author: Matt Hofmann <mrh259 at cornell.edu>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M mlir/python/mlir/dialects/scf.py
M mlir/test/python/dialects/scf.py
Log Message:
-----------
[MLIR][Python] Fix detached operation coming from `IfOp` constructor (#107286)
Without this fix, `scf.if` operations would be created without a parent.
Since `scf.if` operations often have no results, this caused silent bugs
where the generated code was straight-up missing the operation.
Commit: 41c11ea2af743051013dfcc0fced5a450e2dc9b8
https://github.com/llvm/llvm-project/commit/41c11ea2af743051013dfcc0fced5a450e2dc9b8
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[HLSL] Remove variables that are used only in assert (#107299)
Changes the assert to test the same condition without using the
variables.
This change is done in response to a comment
[here](https://github.com/llvm/llvm-project/pull/106657#issuecomment-2327493439).
Commit: abbcfff706b33a8965afa9f2c520f60ad46f3b9e
https://github.com/llvm/llvm-project/commit/abbcfff706b33a8965afa9f2c520f60ad46f3b9e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M flang/lib/Semantics/check-io.cpp
M flang/module/__fortran_builtins.f90
R flang/test/Lower/CUDA/cuda-devptr.cuf
Log Message:
-----------
Revert "[flang][cuda] Add c_devptr and bypass output semantic check" (#107349)
Reverts llvm/llvm-project#107318
It breaks a test
https://lab.llvm.org/buildbot/#/builders/143/builds/1933
Commit: 1465e23985904d55a014f3377c287ded45c0fa0c
https://github.com/llvm/llvm-project/commit/1465e23985904d55a014f3377c287ded45c0fa0c
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
Log Message:
-----------
[RISCV][llvm] Handle `ptr` element type in `lowerDeinterleaveIntrinsicToLoad` and `lowerInterleaveIntrinsicToStore` (#107079)
Resolve https://github.com/llvm/llvm-project/issues/106970
currently it returns 0 fixed size for `ptr` element type. The `ptr`
element size should depend on `XLen` which is 64 in riscv64 and 32 in
riscv32 respectively.
Commit: da8fb7f4dddf48b2395f80dc09efffe38efa3d2f
https://github.com/llvm/llvm-project/commit/da8fb7f4dddf48b2395f80dc09efffe38efa3d2f
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaRISCV.cpp
Log Message:
-----------
[clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. NFC (#106485)
Commit: 845d8d909c37c61298d49c0e91949c669ca15215
https://github.com/llvm/llvm-project/commit/845d8d909c37c61298d49c0e91949c669ca15215
Author: Elvis Wang <110374989+ElvisWang123 at users.noreply.github.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/cast.ll
Log Message:
-----------
[RISCV][TTI] Add cost of typebased cast VPIntrinsics with functionalOPC. (#97797)
This patch make the instruction cost of type-based cast VP intrinsics
will be same as their non-VP counterpart.
This is the following patch of
[#93435](https://github.com/llvm/llvm-project/pull/93435)
Commit: 76be3a0024fe0027bcba9a597fee32a8b2d962ae
https://github.com/llvm/llvm-project/commit/76be3a0024fe0027bcba9a597fee32a8b2d962ae
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
A llvm/test/CodeGen/DirectX/sin_vector_error.ll
Log Message:
-----------
[DirectX] Fix crash in DXILOpBuilder for vector types (#107334)
This function needs to return the "undefined" sigil for unknown types so
that the actual error handling triggers instead of a crash.
Commit: 787fc81437dfc924e4a7d6106248e335e32aeeeb
https://github.com/llvm/llvm-project/commit/787fc81437dfc924e4a7d6106248e335e32aeeeb
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsDirectX.td
Log Message:
-----------
[DirectX] Clean up trailing whitespace. NFC (#107335)
Commit: d18ca271f1add262b4ee0318a980f78a402f5e9c
https://github.com/llvm/llvm-project/commit/d18ca271f1add262b4ee0318a980f78a402f5e9c
Author: Harini0924 <harinidonthula at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A llvm/utils/lit/tests/Inputs/shtest-glob/example_file1.input
A llvm/utils/lit/tests/Inputs/shtest-glob/example_file2.input
A llvm/utils/lit/tests/Inputs/shtest-glob/glob-echo.txt
A llvm/utils/lit/tests/Inputs/shtest-glob/glob-mkdir.txt
A llvm/utils/lit/tests/Inputs/shtest-glob/lit.cfg
A llvm/utils/lit/tests/shtest-glob.py
Log Message:
-----------
Reapply "[llvm-lit] Add precommit test to verify current behavior of glob expansion in lit's internal shell" (#106763) (#107169)
This reverts commit 5af4ba2684b9b59de3bf8135f62e05ab68cfc489.
The previous patch was missing the closing parenthesis `)` in the
`CHECK` statement in the `llvm/utils/lit/tests/shtest-glob.py` file:
`# CHECK: FAIL: shtest-glob :: glob-mkdir.txt ({{[^)]*}}`
This issue broke some build bots. This patch corrects the `CHECK`
statement by adding the closing parenthesis:
`# CHECK: FAIL: shtest-glob :: glob-mkdir.txt ({{[^)]*}})`
Commit: 16cda01d22c0ac1713f667d501bdca91594a4e13
https://github.com/llvm/llvm-project/commit/16cda01d22c0ac1713f667d501bdca91594a4e13
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
Log Message:
-----------
[AMDGPU] V_SET_INACTIVE optimizations (#98864)
Optimize V_SET_INACTIVE by allow it to run in WWM.
Hence WWM sections are not broken up for inactive lane setting.
WWM V_SET_INACTIVE can typically be lower to V_CNDMASK.
Some cases require use of exec manipulation V_MOV as previous code.
GFX9 sees slight instruction count increase in edge cases due to
smaller constant bus.
Additionally avoid introducing exec manipulation and V_MOVs where
a source of V_SET_INACTIVE is the destination.
This is a common pattern as WWM register pre-allocation often
assigns the same register.
Commit: 96a5aabbd6adada4525d5e0107e96e6f57dbdfbf
https://github.com/llvm/llvm-project/commit/96a5aabbd6adada4525d5e0107e96e6f57dbdfbf
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer.h
Log Message:
-----------
[NFC][sanitizer] Thread safety annotation for Symbolizer
Commit: aafaa6943463b56db2928081dc72b116e246c249
https://github.com/llvm/llvm-project/commit/aafaa6943463b56db2928081dc72b116e246c249
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
M llvm/lib/Target/M68k/M68kCallingConv.td
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/lib/Target/PowerPC/PPCCallingConv.td
M llvm/lib/Target/SystemZ/SystemZCallingConv.td
M llvm/lib/Target/X86/X86CallingConv.td
Log Message:
-----------
[Target] Use templated MachineFunction::getSubtarget in *CallingConv.td. NFC (#107311)
This hides away the static_cast needed to get the target specific Subtarget
object.
Commit: 0c1500ef05e0a5b25cae79d2bd361dbc6e14e726
https://github.com/llvm/llvm-project/commit/0c1500ef05e0a5b25cae79d2bd361dbc6e14e726
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
Log Message:
-----------
[RISCV] Fix another RV32 Zdinx load/store addressing corner case.
RISCVExpandPseudoInsts makes sure the offset is divisible by 8
so we need to enforce that during isel.
Commit: 77f04882251b1e44239d6d7545cd62301e903a4a
https://github.com/llvm/llvm-project/commit/77f04882251b1e44239d6d7545cd62301e903a4a
Author: David Green <david.green at arm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/zext-shuffle.ll
Log Message:
-----------
[AArch64] Combine zext of deinterleaving shuffle. (#107201)
This is part 1 of a few patches that are intended to take deinterleaving
shuffles with masks like `[0,4,8,12]`, where the shuffle is
zero-extended to a larger size, and optimize away the deinterleave. In
this case it converts them to `and(uzp1, mask)`, where the `uzp1` act
upon the elements in the larger type size to get the lanes into the
correct possitions, and the `and` performs the zext. It performs the
combine fairly late, on the legalized type so that uitofp that are
converted to uitofp(zext(..)) will also be handled.
Commit: a7697c86559e9d57c9c0e2b5f2daaa5cec4e5119
https://github.com/llvm/llvm-project/commit/a7697c86559e9d57c9c0e2b5f2daaa5cec4e5119
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/test/CodeGen/ARM/arm-vld1.ll
M llvm/test/CodeGen/ARM/arm-vst1.ll
M llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll
M llvm/test/Transforms/InstCombine/ARM/neon-intrinsics.ll
Log Message:
-----------
[ARM] Do not assume alignment in vld1xN and vst1xN intrinsics (#106984)
These intrinsics currently assume natural alignment. Instead, respect
the alignment attribute on the intrinsic. Teach InstCombine to improve
that alignment.
If desired I could also adjust the clang frontend to add alignment
annotations equivalent to the previous behavior, but I don't see any
indication that such an assumption is correct in the ARM intrinsics
docs.
Fixes https://github.com/llvm/llvm-project/issues/59081.
Commit: 3d729571fdc86a40218e5743d4386d7d8edc36ae
https://github.com/llvm/llvm-project/commit/3d729571fdc86a40218e5743d4386d7d8edc36ae
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
Log Message:
-----------
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
Previously for vector peepholes that fold based on VL, we checked if the
VLMAX is the same as a proxy to check that the EEWs were the same. This
only worked at LMUL >= 1 because the EMULs of the Src output and user's
input had to be the same because the register classes needed to match.
At fractional LMULs we would have incorrectly folded something like
this:
%x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, 4, 4 /* e16 */, 0
%y:vr = PseudoVMV_V_V_MF8 $noreg, %x, 4, 3 /* e8 */, 0
This models the EEW of the destination operands of vector instructions
with a TSFlag, which is enough to fix the incorrect folding.
There's some overlap with the TargetOverlapConstraintType and
IsRVVWideningReduction. If we model the source operands as well we may
be able to subsume them.
Commit: f006246299c96486a8e37005a94e07c0bf334ee0
https://github.com/llvm/llvm-project/commit/f006246299c96486a8e37005a94e07c0bf334ee0
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/Target.td
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
M llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
Log Message:
-----------
[CodeGen] Add generic INIT_UNDEF pseudo (#106744)
The InitUndef pass currently uses target-specific pseudo instructions,
with one pseudo per register class.
Instead, add a generic pseudo instruction, which can be used by all
targets and register classes.
Commit: f1ac334b13c22222ed5c71bad04ed8345b2be135
https://github.com/llvm/llvm-project/commit/f1ac334b13c22222ed5c71bad04ed8345b2be135
Author: Mital Ashok <mital at mitalashok.co.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/SemaCXX/cxx20-default-compare.cpp
Log Message:
-----------
[Clang][SemaCXX] Preserve qualifiers in derived-to-base cast in defaulted comparison operators (#102619)
Fixes #102588
Co-authored-by: cor3ntin <corentinjabot at gmail.com>
Commit: cf1ad28169be5d026ec95f351b56b0c090b3e682
https://github.com/llvm/llvm-project/commit/cf1ad28169be5d026ec95f351b56b0c090b3e682
Author: Daniel Grumberg <dgrumberg at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/ExtractAPI/DeclarationFragments.cpp
A clang/test/ExtractAPI/attributed-typedef.m
Log Message:
-----------
[clang][ExtractAPI] Handle AttributedType fragments transparently (#107262)
rdar://131958623
Commit: 41373098421f2aa551a0879537864c87d797a102
https://github.com/llvm/llvm-project/commit/41373098421f2aa551a0879537864c87d797a102
Author: Mital Ashok <mital at mitalashok.co.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/lib/Lex/Lexer.cpp
M clang/test/Sema/pre-c2x-compat.c
Log Message:
-----------
[Clang] Warn with -Wpre-c23-compat instead of -Wpre-c++17-compat for u8 character literals in C23 (#97210)
Co-authored-by: cor3ntin <corentinjabot at gmail.com>
Commit: 3e4788377bb29ed389b46521fcba0d06aa985bcf
https://github.com/llvm/llvm-project/commit/3e4788377bb29ed389b46521fcba0d06aa985bcf
Author: Giulio Eulisse <10544+ktf at users.noreply.github.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/include/clang/Basic/SourceManager.h
M llvm/include/llvm/ADT/PagedVector.h
Log Message:
-----------
Recover performance loss after PagedVector introduction (#67972)
Commit: b206bf0952796cb93f1aca9e47d5764e474e1998
https://github.com/llvm/llvm-project/commit/b206bf0952796cb93f1aca9e47d5764e474e1998
Author: Konrad Kleine <kkleine at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/cmake/caches/Release.cmake
Log Message:
-----------
Fix CLANG_BOOTSTRAP_TARGETS in Release.cmake (#106407)
# Problem
Before this patch you could not build the `stage2-LLVM` for example
because you first had to manually add it to `CLANG_BOOTSTRAP_TARGETS` in
the `Release.cmake` and also add it to
`LLVM_RELEASE_FINAL_STAGE_TARGETS` in the cmake configure run. Now you
can just use `-DLLVM_RELEASE_FINAL_STAGE_TARGETS="LLVM;clang"` on the
cmake CLI and be able to build the targets `stage2-LLVM` and
`stage2-clang` without further changes to the cache file.
# Solution
Take all `LLVM_RELEASE_FINAL_STAGE_TARGETS` elements and append them
prefixed with `stage2-` to `CLANG_BOOTSTRAP_TARGETS`. Afterwards all
duplicates are removed.
Commit: 3413f957243e4a152726e572986eb730699b8486
https://github.com/llvm/llvm-project/commit/3413f957243e4a152726e572986eb730699b8486
Author: David Green <david.green at arm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/zext-shuffle.ll
Log Message:
-----------
[AArch64] Add a few extra two-step zext shuffle tests. NFC
Commit: a95b212e9957b8f5b7d452b4713a7b6f9ee19e71
https://github.com/llvm/llvm-project/commit/a95b212e9957b8f5b7d452b4713a7b6f9ee19e71
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Log Message:
-----------
[DWARF] Don't search scope chain to find DISubprogram for prologues (#107261)
Seemingly this goes back to fd07a2a in 2015 -- I anticipate that back
then the metadata layout was radically different. But nowadays at least, we
can just directly look up the subprogram.
Commit: 03d5b7ca3d83eee3514318ef8934ba26bc3d7fa9
https://github.com/llvm/llvm-project/commit/03d5b7ca3d83eee3514318ef8934ba26bc3d7fa9
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[MemorySanitizer] Don't create types pointers (NFC)
Everything in this pass uses a single addrspace 0 pointer type.
Don't try to create it using the typed pointer ctor.
This allows removing the type argument from
getShadowPtrForVAArgument().
Commit: 071606ab282bb622a87759569b7044ec19a9c641
https://github.com/llvm/llvm-project/commit/071606ab282bb622a87759569b7044ec19a9c641
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
Log Message:
-----------
[RISCV] Remove RV32 FIXMEs completed in #107290. NFC
Commit: 5ee73953f03fe0cf53190c8dc9a257c752ab4171
https://github.com/llvm/llvm-project/commit/5ee73953f03fe0cf53190c8dc9a257c752ab4171
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s
Log Message:
-----------
[AMDGPU] Add image_atomic_fmin/fmax as aliases for GFX12 (#107242)
This just follows SP3.
Commit: d0278cf395e09bfb8dbef9cb92e6103be91e1eb3
https://github.com/llvm/llvm-project/commit/d0278cf395e09bfb8dbef9cb92e6103be91e1eb3
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
Log Message:
-----------
[RISCV] Remove some more completed FIXMEs from tests. NFC
Commit: 3299bc863fd74613fdfad2a2fde3f75de79bd645
https://github.com/llvm/llvm-project/commit/3299bc863fd74613fdfad2a2fde3f75de79bd645
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/DebugHandlerBase.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
Log Message:
-----------
[DWARF] Identify prologue_end by instruction rather than DILocation (#107264)
Currently, we identify the end of the prologue as being "the instruction
that first has *this* DebugLoc". It works well enough, but I feel
identifying a position in a function is best communicated by a
MachineInstr. Plus, I've got some patches coming that depend upon this.
Commit: 95684afbcd59f34be580f75ee32f766874b5d0f5
https://github.com/llvm/llvm-project/commit/95684afbcd59f34be580f75ee32f766874b5d0f5
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/Mangler.h
M llvm/lib/IR/Mangler.cpp
Log Message:
-----------
[IR][ARM64EC][NFC] Clean up and document ARM64EC mangling helpers. (#107230)
Commit: 87b4b648585f69a2ea148e86543aa31474e59acd
https://github.com/llvm/llvm-project/commit/87b4b648585f69a2ea148e86543aa31474e59acd
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/Sema/CheckExprLifetime.cpp
Log Message:
-----------
Fix a typo in CheckExprLifetime.cpp, NFC
Commit: 3e070906eff720dc44aee86e533e12aafc8bb14b
https://github.com/llvm/llvm-project/commit/3e070906eff720dc44aee86e533e12aafc8bb14b
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/Sema/CheckExprLifetime.cpp
Log Message:
-----------
Fix llvm-else-after-return clang-tidy warning in CheckExprLifetime.cpp, NFC
Commit: 07bef02831836748f46ddd285520f351fe18cfe9
https://github.com/llvm/llvm-project/commit/07bef02831836748f46ddd285520f351fe18cfe9
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
Log Message:
-----------
[OpenMPOpt] Initialize OpenMPIRBuilderConfig::IsGPU flag (#104456)
This patch ensures the `IsGPU` flag is set by the OpenMPOpt pass, so
that it can be relied upon by `OpenMPIRBuilder` methods when called by
that pass as well.
Since currently there are very limited callers for the
`OpenMPIRBuilder::isGPU()` method, no assertions are being triggered by
the lack of initialization of this flag. However, when more
offloading-related features are implemented, it will eventually start
happening.
Commit: 142433684a6e3a2936f814268396dea4190905dc
https://github.com/llvm/llvm-project/commit/142433684a6e3a2936f814268396dea4190905dc
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
A offload/test/offloading/fortran/target-map-dynamic.f90
Log Message:
-----------
[OpenMP][Flang] Fix dynamic-extent array mapping (#107247)
This patch fixes the mapping and lowering of arrays with dynamic extents
and adds a new test for the same. The fix discards the incomplete the
dynamic extent information and replacing it with just the base type.
When lowering to llvm later, the bounds information is used instead.
Commit: b44d9e5d3605d7ddd64992e3c77b6669f0f7701b
https://github.com/llvm/llvm-project/commit/b44d9e5d3605d7ddd64992e3c77b6669f0f7701b
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
VPlanTransforms: fix style after cursory reading (NFC) (#105827)
Commit: fa385274baae77a0ea7e78c4c6feca6b0ab4f1dc
https://github.com/llvm/llvm-project/commit/fa385274baae77a0ea7e78c4c6feca6b0ab4f1dc
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
A libcxx/test/libcxx/containers/associative/unord.map/abi.compile.pass.cpp
A libcxx/test/libcxx/containers/associative/unord.set/abi.compile.pass.cpp
M libcxx/utils/libcxx/test/features.py
Log Message:
-----------
[libc++] Add ABI tests for unordered_{map,set} (#107200)
These are used to ensure #76756 is correct.
Commit: 11040560ba30381ed47c3089a2562a41b00dbb4b
https://github.com/llvm/llvm-project/commit/11040560ba30381ed47c3089a2562a41b00dbb4b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/abds-neg.ll
M llvm/test/CodeGen/X86/abds.ll
Log Message:
-----------
[X86] preferABDSToABSWithNSW - use ABDS for i32/i64 if we have CMOV
Now that we have better ABDS lowering, prefer cmov(sub(x,y),sub(y,x)) to cmov(abs(sub(x,y)),sub(x,y)) to improve ILP
Commit: 84cf3a573e89b18ce79ff32a7646c0a99729029c
https://github.com/llvm/llvm-project/commit/84cf3a573e89b18ce79ff32a7646c0a99729029c
Author: Mital Ashok <mital at mitalashok.co.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/literals.cpp
M clang/test/CXX/drs/cwg27xx.cpp
M clang/test/CXX/expr/expr.const/p2-0x.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[Clang] CWG2749: relational operators involving pointers to void (#93046)
https://cplusplus.github.io/CWG/issues/2749.html
This DR's effects are backported to C++98.
Does not affect C where integral constant expressions cannot involve
pointers.
---------
Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Co-authored-by: cor3ntin <corentinjabot at gmail.com>
Commit: d6832a611a7c4ec36f08b1cfe9af850dad32da2e
https://github.com/llvm/llvm-project/commit/d6832a611a7c4ec36f08b1cfe9af850dad32da2e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/ranges_minmax.h
M libcxx/include/__atomic/atomic.h
M libcxx/include/__charconv/to_chars_integral.h
A libcxx/include/__cstddef/byte.h
A libcxx/include/__cstddef/max_align_t.h
A libcxx/include/__cstddef/nullptr_t.h
A libcxx/include/__cstddef/ptrdiff_t.h
A libcxx/include/__cstddef/size_t.h
M libcxx/include/__exception/nested_exception.h
M libcxx/include/__fwd/array.h
M libcxx/include/__fwd/complex.h
M libcxx/include/__fwd/pair.h
M libcxx/include/__fwd/span.h
M libcxx/include/__fwd/subrange.h
M libcxx/include/__fwd/tuple.h
M libcxx/include/__iterator/concepts.h
M libcxx/include/__iterator/iterator_traits.h
M libcxx/include/__iterator/wrap_iter.h
M libcxx/include/__mdspan/layout_stride.h
M libcxx/include/__memory/pointer_traits.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__memory/uses_allocator.h
M libcxx/include/__random/mersenne_twister_engine.h
M libcxx/include/__random/seed_seq.h
M libcxx/include/__random/subtract_with_carry_engine.h
M libcxx/include/__ranges/subrange.h
M libcxx/include/__string/constexpr_c_functions.h
M libcxx/include/__tuple/tuple_size.h
M libcxx/include/__type_traits/aligned_storage.h
M libcxx/include/__type_traits/aligned_union.h
M libcxx/include/__type_traits/alignment_of.h
M libcxx/include/__type_traits/extent.h
M libcxx/include/__type_traits/is_allocator.h
M libcxx/include/__type_traits/is_array.h
M libcxx/include/__type_traits/is_bounded_array.h
M libcxx/include/__type_traits/is_nothrow_destructible.h
M libcxx/include/__type_traits/is_null_pointer.h
M libcxx/include/__type_traits/is_swappable.h
M libcxx/include/__type_traits/rank.h
M libcxx/include/__type_traits/remove_all_extents.h
M libcxx/include/__type_traits/remove_extent.h
M libcxx/include/__type_traits/type_list.h
M libcxx/include/__utility/in_place.h
M libcxx/include/__utility/pair.h
M libcxx/include/__utility/swap.h
M libcxx/include/any
M libcxx/include/cstddef
M libcxx/include/cstdio
M libcxx/include/cstdlib
M libcxx/include/cstring
M libcxx/include/ctime
M libcxx/include/cuchar
M libcxx/include/cwchar
M libcxx/include/experimental/__simd/reference.h
M libcxx/include/experimental/__simd/scalar.h
M libcxx/include/experimental/__simd/simd.h
M libcxx/include/experimental/__simd/simd_mask.h
M libcxx/include/experimental/__simd/vec_ext.h
M libcxx/include/module.modulemap
M libcxx/include/typeinfo
M libcxx/include/unordered_map
M libcxx/include/unordered_set
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countl_one.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countl_zero.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countr_one.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countr_zero.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/popcount.pass.cpp
M libcxx/test/std/numerics/bit/bitops.rot/rotl.pass.cpp
M libcxx/test/std/numerics/bit/bitops.rot/rotr.pass.cpp
M libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.cpp
M libcxx/utils/libcxx/test/modules.py
Log Message:
-----------
[libc++][modules] Modularize <cstddef> (#107254)
Many headers include `<cstddef>` just for size_t, and pulling in
additional content (e.g. the traits used for std::byte) is unnecessary.
To solve this problem, this patch splits up `<cstddef>` into
subcomponents so that headers can include only the parts that they
actually require.
This has the added benefit of making the modules build a lot stricter
with respect to IWYU, and also providing a canonical location where we
define `std::size_t` and friends (which were previously defined in
multiple headers like `<cstddef>` and `<ctime>`).
After this patch, there's still many places in the codebase where we
include `<cstddef>` when `<__cstddef/size_t.h>` would be sufficient.
This patch focuses on removing `<cstddef>` includes from __type_traits
to make these headers non-circular with `<cstddef>`. Additional
refactorings can be tackled separately.
Commit: 485d191f0ca5e31a60fe2489ac99270ed5c7a594
https://github.com/llvm/llvm-project/commit/485d191f0ca5e31a60fe2489ac99270ed5c7a594
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port d6832a611a7c
Commit: 2a07509c8d3c8b5b2c88e4f73dde0071bf506870
https://github.com/llvm/llvm-project/commit/2a07509c8d3c8b5b2c88e4f73dde0071bf506870
Author: Mital Ashok <mital at mitalashok.co.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/ByteCode/State.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/SemaCXX/builtin-is-within-lifetime.cpp
A clang/test/SemaCXX/consteval-builtin.cpp
Log Message:
-----------
[Clang] Add __builtin_is_within_lifetime to implement P2641R4's std::is_within_lifetime (#91895)
[P2641R4](https://wg21.link/P2641R4)
This new builtin function is declared `consteval`. Support for
`-fexperimental-new-constant-interpreter` will be added in a later
patch.
---------
Co-authored-by: cor3ntin <corentinjabot at gmail.com>
Commit: e4fdbcc28f19b59fef065f2a6f939f91f286b9a8
https://github.com/llvm/llvm-project/commit/e4fdbcc28f19b59fef065f2a6f939f91f286b9a8
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/forward_list
M libcxx/include/list
M libcxx/include/string
Log Message:
-----------
[libc++] Add miscellaneous missing includes
Commit: 2c3da172d1869a2e261af38c45582027a9ff6af7
https://github.com/llvm/llvm-project/commit/2c3da172d1869a2e261af38c45582027a9ff6af7
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
Log Message:
-----------
LIR: strip unused LAA header dependency (NFC) (#107382)
LoopIdiomRecognize does not use LoopAccessAnalysis. Make this clear.
Commit: 3d01f0a33b9a14545217938fbd2475226ade2719
https://github.com/llvm/llvm-project/commit/3d01f0a33b9a14545217938fbd2475226ade2719
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
M mlir/test/Dialect/GPU/canonicalize.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
Log Message:
-----------
[mlir][gpu] Add 'cluster_stride' attribute to gpu.subgroup_reduce (#107142)
Follow-up to 7aa22f013e24d20291aad745368ff907baa9dfa4, adding an
additional attribute needed in some applications.
Commit: 7d1a68178ef4332c9bf19a5c959a3ec4cef0285d
https://github.com/llvm/llvm-project/commit/7d1a68178ef4332c9bf19a5c959a3ec4cef0285d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Log Message:
-----------
[SystemZ] Use APInt::getAllOnes()
This was using -1 without setting the signed flag.
Split off from https://github.com/llvm/llvm-project/pull/80309.
Commit: 67e19e5bb11d8ed2f1b5a0b8145331c8bf4522e9
https://github.com/llvm/llvm-project/commit/67e19e5bb11d8ed2f1b5a0b8145331c8bf4522e9
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
Log Message:
-----------
[flang] Set isSigned=true for negative constant (NFC)
We're providing this as a negative signed value, so set the flag.
Currently doesn't make a difference, but will assert in the future.
Split out of https://github.com/llvm/llvm-project/pull/80309.
Commit: 9e9971b100e121b83f1de9e9206cddb52cda4815
https://github.com/llvm/llvm-project/commit/9e9971b100e121b83f1de9e9206cddb52cda4815
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[PatternMatchTest] Use APInt::getAllOnes() (NFC)
Split out from https://github.com/llvm/llvm-project/pull/80309 to
avoid assertion failures in the future.
Commit: eae1d6152fd77511f943fd7f300a971c53453e70
https://github.com/llvm/llvm-project/commit/eae1d6152fd77511f943fd7f300a971c53453e70
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
Log Message:
-----------
[X86] Add test coverage for #107289
Commit: 1a1264726db275d4b207c5bc640e2779dd484478
https://github.com/llvm/llvm-project/commit/1a1264726db275d4b207c5bc640e2779dd484478
Author: Robin Caloudis <robin.caloudis at gmx.de>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M libcxx/include/__math/traits.h
M libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
M libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-gcc.pass.cpp
A libcxx/test/std/numerics/c.math/signbit.pass.cpp
Log Message:
-----------
[libc++][math] Add `constexpr` for `std::signbit()` (#105946)
## Why
Since 18th of August, the floating point comparison builtin
``__builtin_signbit`` is available in Clang as constant expression
(https://github.com/llvm/llvm-project/pull/94118).
## What
* Implement `constexpr` for `std::signbit()` as defined by
[P0533R9](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2021/p0533r9.pdf)
(new C++23 feature)
* Restrict execution of tests to tip-of-trunk Clang as builtin is not
yet available (note that builtin is available in GCC)
Commit: 7f0c5b0502b462d2afad32d3681b37cfc15ba844
https://github.com/llvm/llvm-project/commit/7f0c5b0502b462d2afad32d3681b37cfc15ba844
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/test/CodeGen/AArch64/sme-vg-to-stack.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll
M llvm/test/CodeGen/AArch64/sve-callee-save-restore-pairs.ll
Log Message:
-----------
[AArch64]Fix invalid use of ld1/st1 in stack alloc (#105518)
This patch fixes incorrect usage of scalar+immediate variant of ld1/st1
instructions during stack allocation caused by
[c4bac7f](https://github.com/llvm/llvm-project/commit/c4bac7f7dcd931a5e561604e95656a24c3d1c9d9).
This commit used ld1/st1 even when stack offset was outside of immediate
range for this instruction, producing invalid assembly. This commit was also using incorrect offsets when using ld1/st1.
Commit: 80cd2141eb7f6e7be738a01348bc2ccd08b41cd6
https://github.com/llvm/llvm-project/commit/80cd2141eb7f6e7be738a01348bc2ccd08b41cd6
Author: Mogball <jeff at modular.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][llvm] Add `externally_initialized` support to GlobalOp
This maps the `externally_initialized` flag in `llvm::GlobalVariable` to
`GlobalOp` and adds exported support.
Commit: 0ba78182b975d8ccd8ca42b33fbf038a85a44747
https://github.com/llvm/llvm-project/commit/0ba78182b975d8ccd8ca42b33fbf038a85a44747
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerSelect - generalize "select icmp(x,0), lhs, rhs" folding patterns [NFC] (#107374)
This patch proposes we add a LowerSELECTWithCmpZero helper, which allows us to fold the compare-with-zero from different condition nodes with minimal duplication.
So far I've only handled the simple no-cmov case for or/xor nodes, but the intention is to convert more folds in future PRs.
NFC preliminary patch for #107272
Commit: 233ed51cf53d590d3f52d5becff95317dbf73657
https://github.com/llvm/llvm-project/commit/233ed51cf53d590d3f52d5becff95317dbf73657
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/Chunks.h
Log Message:
-----------
[LLD][COFF][NFC] Use is64Bit in Baserel::getDefaultType. (#107378)
In preparation for ARM64EC support. Also make it static.
Commit: 9707b98e572adf34ef3e71bcf159dae08e654fd8
https://github.com/llvm/llvm-project/commit/9707b98e572adf34ef3e71bcf159dae08e654fd8
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/IR/ConstantRange.cpp
Log Message:
-----------
[ConstantRange] Perform increment on APInt (NFC)
This handles the edge case where BitWidth is 1 and doing the
increment gets a value that's not valid in that width, while we
just want wrap-around.
Split out of https://github.com/llvm/llvm-project/pull/80309.
Commit: 9e85efb0dec8e78ca69925a05c0bbba211dee507
https://github.com/llvm/llvm-project/commit/9e85efb0dec8e78ca69925a05c0bbba211dee507
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/unittests/IR/ConstantRangeTest.cpp
Log Message:
-----------
[ConstantRangeTest] Set APInt signed flags where needed (NFC)
Split out from https://github.com/llvm/llvm-project/pull/80309 to
avoid assertion failures in the future.
Commit: 5024dff6eee5a95a741b063c953422c5b6d02fdc
https://github.com/llvm/llvm-project/commit/5024dff6eee5a95a741b063c953422c5b6d02fdc
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libc++][ci] Add a test configuration with an incomplete sysroot (#107089)
When bringing up a new cross compiler from scratch, we build
libunwind/libcxx in a setup where the toolchain is incomplete and unable
to perform the normal linker checks; this requires a few special cases
in the CMake files.
We simulate that scenario by removing the libc++ headers, libunwind and
libc++ libraries from the installed toolchain.
We need to set CMAKE_CXX_COMPILER_WORKS since CMake fails to probe the
compiler. We need to set CMAKE_CXX_COMPILER_TARGET, since LLVM's
heuristics fail when CMake hasn't been able to probe the environment
properly. (This is normal; one has to set those options when setting up
such a toolchain from scratch.)
This adds CI coverage for these build scenarios, which otherwise seldom
are tested by some build flow (but are essential when setting up a cross
compiler from scratch).
Commit: 16dc65bdc0f0a23bc2696afce2abecd9f2faa097
https://github.com/llvm/llvm-project/commit/16dc65bdc0f0a23bc2696afce2abecd9f2faa097
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/test/CodeGen/MLRegAlloc/dev-mode-extra-features-logging.ll
Log Message:
-----------
[mlgo] Fix test post - #106744
Trivial fix, some instruction opcodes changed.
Commit: bded3b3ea9f78c5b3edc3d4a6076665af0ea746b
https://github.com/llvm/llvm-project/commit/bded3b3ea9f78c5b3edc3d4a6076665af0ea746b
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/div.ll
Log Message:
-----------
[llvm][AArch64] Improve the cost model for i128 div's (#107306)
Commit: 63e8a1b16f344eaef17c4015497326479e69d1e7
https://github.com/llvm/llvm-project/commit/63e8a1b16f344eaef17c4015497326479e69d1e7
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
Log Message:
-----------
[SLP] Enable reordering for non-power-of-two vectors (#106638)
This change tries to enable vector reordering during vectorization for
non-power-of-two vectors. Specifically, my goal is to be able to
vectorize reductions whose operands appear in other than identity order.
(i.e. a[1] + a[0] + a[2]). Our standard pass pipeline, Reassociation
effectively canonicalizes towards this form. So for reduction
vectorization to be wildly applicable, we need this feature.
This change enables the use of a non-empty ReorderIndices structure -
which is effectively required for out of order loads or gathers - while
leaving the ReuseShuffleIndices mechanism unused and disabled. If I've
understood the code structure, the former is used when describing
implicit shuffles required by the vectorization strategy (i.e. loading
elements 0,1,3,2 in the order 0,1,2,3 and then shuffling later), while
the later is used when trying to optimize explode/buildvectors (called
gathers in this code).
I audited all the code enabled by this change, but can't claim to
deeply understand most of it. I added a couple of bailouts in places
which appeared to be difficult to audit and optional optimizations. I've
tried to do so in the least risky way I can, but am not completely
confident in this change. Careful review appreciated.
Commit: 3b19e480c056a35a60e3c65de476b6097329ceac
https://github.com/llvm/llvm-project/commit/3b19e480c056a35a60e3c65de476b6097329ceac
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M flang/include/flang/Tools/TargetSetup.h
M flang/module/ieee_arithmetic.f90
M flang/test/CMakeLists.txt
M flang/test/Evaluate/fold-out_of_range.f90
M flang/test/Evaluate/folding07.f90
M flang/test/Lower/Intrinsics/ieee_class_queries.f90
M flang/test/Lower/Intrinsics/ieee_unordered.f90
M flang/test/Lower/common-block.f90
M flang/test/Semantics/kinds03.f90
M flang/test/Semantics/modfile26.f90
M flang/test/Semantics/realkinds-aarch64-01.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/f18/CMakeLists.txt
Log Message:
-----------
[flang] Warn when F128 is unsupported (#102147) (#106957)
This generates `warning: REAL(KIND=16) is not an enabled type for this
target` if that type is used in a build not correctly configured to
support this type. Uses of `selected_real_kind(30)` return -1.
Relanding #102147 because the test errors turned out to be specific to a
downstream configuration.
Commit: e80f48986c7ba6cc41378b8d8e12d804cf26895d
https://github.com/llvm/llvm-project/commit/e80f48986c7ba6cc41378b8d8e12d804cf26895d
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/udiv-of-x-xsmaxone-fold.ll
Log Message:
-----------
[SCEV] BECount to zero if `((-C + (C smax %x)) /u %x), C > 0` holds
The SCEV expression `((-C + (C smax %x)) /u %x)` can be folded
to zero for any positive constant C.
Proof: https://alive2.llvm.org/ce/z/_dLm8C.
Commit: 7eca38ce76d5d1915f4ab7e665964062c0b37697
https://github.com/llvm/llvm-project/commit/7eca38ce76d5d1915f4ab7e665964062c0b37697
Author: Hari Limaye <hari.limaye at arm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGBuilder.h
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/2005-01-02-ConstantInits.c
M clang/test/CodeGen/PowerPC/ppc-emmintrin.c
M clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
M clang/test/CodeGen/attr-counted-by.c
M clang/test/CodeGen/catch-nullptr-and-nonzero-offset-when-nullptr-is-defined.c
M clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
M clang/test/CodeGen/catch-pointer-overflow-volatile.c
M clang/test/CodeGen/catch-pointer-overflow.c
M clang/test/CodeGen/ext-int.c
M clang/test/CodeGen/hexagon-brev-ld-ptr-incdec.c
M clang/test/CodeGen/integer-overflow.c
M clang/test/CodeGen/ms-intrinsics.c
M clang/test/CodeGen/ubsan-pointer-overflow.m
M clang/test/CodeGen/vla.c
M clang/test/CodeGenCXX/attr-likelihood-iteration-stmt.cpp
M clang/test/CodeGenCXX/for-range.cpp
M clang/test/CodeGenCXX/pr45964-decomp-transform.cpp
M clang/test/CodeGenCXX/vla.cpp
M clang/test/CodeGenHLSL/buffer-array-operator.hlsl
M clang/test/CodeGenSYCL/address-space-deduction.cpp
M clang/test/Headers/__clang_hip_math.hip
M clang/test/OpenMP/bug60602.cpp
M clang/test/OpenMP/declare_mapper_codegen.cpp
M clang/test/OpenMP/distribute_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/distribute_simd_codegen.cpp
M clang/test/OpenMP/for_linear_codegen.cpp
M clang/test/OpenMP/for_reduction_codegen.cpp
M clang/test/OpenMP/for_reduction_codegen_UDR.cpp
M clang/test/OpenMP/for_reduction_task_codegen.cpp
M clang/test/OpenMP/for_scan_codegen.cpp
M clang/test/OpenMP/for_simd_scan_codegen.cpp
M clang/test/OpenMP/irbuilder_for_iterator.cpp
M clang/test/OpenMP/irbuilder_for_rangefor.cpp
M clang/test/OpenMP/irbuilder_for_unsigned.c
M clang/test/OpenMP/irbuilder_for_unsigned_auto.c
M clang/test/OpenMP/irbuilder_for_unsigned_down.c
M clang/test/OpenMP/irbuilder_for_unsigned_dynamic.c
M clang/test/OpenMP/irbuilder_for_unsigned_dynamic_chunked.c
M clang/test/OpenMP/irbuilder_for_unsigned_runtime.c
M clang/test/OpenMP/irbuilder_for_unsigned_static_chunked.c
M clang/test/OpenMP/map_struct_ordering.cpp
M clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
M clang/test/OpenMP/master_taskloop_reduction_codegen.cpp
M clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
M clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp
M clang/test/OpenMP/ordered_codegen.cpp
M clang/test/OpenMP/parallel_for_codegen.cpp
M clang/test/OpenMP/parallel_for_linear_codegen.cpp
M clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/parallel_for_scan_codegen.cpp
M clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
M clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
M clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp
M clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp
M clang/test/OpenMP/parallel_reduction_codegen.cpp
M clang/test/OpenMP/parallel_reduction_task_codegen.cpp
M clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
M clang/test/OpenMP/reduction_implicit_map.cpp
M clang/test/OpenMP/sections_reduction_task_codegen.cpp
M clang/test/OpenMP/target_data_use_device_addr_codegen.cpp
M clang/test/OpenMP/target_data_use_device_ptr_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_codegen.cpp
M clang/test/OpenMP/target_in_reduction_codegen.cpp
M clang/test/OpenMP/target_is_device_ptr_codegen.cpp
M clang/test/OpenMP/target_map_both_pointer_pointee_codegen.cpp
M clang/test/OpenMP/target_map_codegen_01.cpp
M clang/test/OpenMP/target_map_codegen_21.cpp
M clang/test/OpenMP/target_map_codegen_27.cpp
M clang/test/OpenMP/target_map_codegen_28.cpp
M clang/test/OpenMP/target_map_codegen_29.cpp
M clang/test/OpenMP/target_map_deref_array_codegen.cpp
M clang/test/OpenMP/target_map_member_expr_array_section_codegen.cpp
M clang/test/OpenMP/target_map_member_expr_codegen.cpp
M clang/test/OpenMP/target_map_nest_defalut_mapper_codegen.cpp
M clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
M clang/test/OpenMP/target_task_affinity_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/target_update_codegen.cpp
M clang/test/OpenMP/task_codegen.c
M clang/test/OpenMP/task_codegen.cpp
M clang/test/OpenMP/task_in_reduction_codegen.cpp
M clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp
M clang/test/OpenMP/taskloop_in_reduction_codegen.cpp
M clang/test/OpenMP/taskloop_reduction_codegen.cpp
M clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp
M clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp
Log Message:
-----------
Reland "[clang] Add nuw attribute to GEPs (#105496)" (#107257)
Add nuw attribute to inbounds GEPs where the expression used to form the
GEP is an addition of unsigned indices.
Relands #105496, which was reverted because it exposed a miscompilation
arising from #98608. This is now fixed by #106512.
Commit: 122874c955e06defb619b1afd4e26db482dbbf19
https://github.com/llvm/llvm-project/commit/122874c955e06defb619b1afd4e26db482dbbf19
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/buildvec-insertvec.ll
M llvm/test/CodeGen/X86/known-signbits-vector.ll
M llvm/test/CodeGen/X86/load-scalar-as-vector.ll
M llvm/test/CodeGen/X86/pr44915.ll
M llvm/test/CodeGen/X86/vec_insert-5.ll
M llvm/test/CodeGen/X86/vec_shift5.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
Log Message:
-----------
[X86] Fold scalar_to_vector(shift(x,imm)) -> vshift(scalar_to_vector(x),imm)
Noticed while working on #107289
Commit: 0c8d6df362fe5b4bce54776e2199623d0382293b
https://github.com/llvm/llvm-project/commit/0c8d6df362fe5b4bce54776e2199623d0382293b
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/builtin-unary-fp.c
Log Message:
-----------
Fix handling of FP-classify where the last arg fails to convert
The last argument of an FP-classify function was checked for vailidity
as an expression, but we never ensured that the usual unary
conversions/etc properly resulted in a valid value. Thus, when we got
the value, it was null, so we had a null dereference.
This patch instead fails out/marks the function call as invalid if the
argument is incorrect. I DID consider just allowing it to continue, but
the result was an extraneous error about how the last argument wasn't a
float (in this case, it was an overload set).
Fixes: #107411
Commit: aea3b0f6838bd8268fc3653e1b662d771c87ab15
https://github.com/llvm/llvm-project/commit/aea3b0f6838bd8268fc3653e1b662d771c87ab15
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
Log Message:
-----------
[ARM] Avoid repeated hash lookups (NFC) (#107356)
Commit: abfb340b779f2b20009fe42ebc522417adf79c44
https://github.com/llvm/llvm-project/commit/abfb340b779f2b20009fe42ebc522417adf79c44
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/Analysis/ThreadSafety.cpp
Log Message:
-----------
[Analysis] Avoid repeated hash lookups (NFC) (#107357)
Commit: 0593b95ff4c459ccf71f9472c148967d40f6d865
https://github.com/llvm/llvm-project/commit/0593b95ff4c459ccf71f9472c148967d40f6d865
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
[CGOpenMPRuntime] Avoid repeated hash lookups (NFC) (#107358)
Commit: be427dfb9ea6689947253d737708dc3645e179dc
https://github.com/llvm/llvm-project/commit/be427dfb9ea6689947253d737708dc3645e179dc
Author: Mital Ashok <mital at mitalashok.co.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/test/CXX/drs/cwg27xx.cpp
M clang/test/Lexer/cxx-features.cpp
M clang/test/Parser/cxx11-user-defined-literals.cpp
M clang/test/Sema/static-assert.c
A clang/test/SemaCXX/static-assert-ext.cpp
Log Message:
-----------
[Clang][Parser] Accept P2741R3 (static_assert with user-generated message) in C++11 as an extension (#102044)
Added a new `-Wpre-c++26-compat` warning for when this feature is used
in C++26 and a `-Wc++26-extensions` warning for when this is used in
C++11 through C++23.
---------
Co-authored-by: cor3ntin <corentinjabot at gmail.com>
Commit: 13013bdc6a5e4def05204fb69d7a31ef17ccd1c7
https://github.com/llvm/llvm-project/commit/13013bdc6a5e4def05204fb69d7a31ef17ccd1c7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-imm.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-imm.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
Log Message:
-----------
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
There is no Fmv with Zfinx.
Commit: 56b2be4a7608770bae5db9d467f50c232c3cf19a
https://github.com/llvm/llvm-project/commit/56b2be4a7608770bae5db9d467f50c232c3cf19a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
Log Message:
-----------
[X86] Fold scalar_to_vector(funnel(x,y,imm)) -> funnel(scalar_to_vector(x),scalar_to_vector(y),imm)
Limit this to cases where x, y are known to be extracted from a vector.
Addresses poor x86 codegen on #107289
Commit: 2f6e4ed389a6589f340d7efab2b0c7ee22c3d086
https://github.com/llvm/llvm-project/commit/2f6e4ed389a6589f340d7efab2b0c7ee22c3d086
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/IR/Type.cpp
A llvm/test/Assembler/target-type-param-errors.ll
Log Message:
-----------
[IR] Check parameters of target extension types on construction (#107268)
Since IR Types are immutable it makes sense to check them on
construction instead of in the IR Verifier pass.
This patch checks that some TargetExtTypes are well-formed in the sense
that they have the expected number of type parameters and integer
parameters. When called from LLParser it gives a diagnostic message.
When called from anywhere else it just asserts that they are
well-formed.
Commit: fc3e6a81868a0c84e405622a64756e57f020ca37
https://github.com/llvm/llvm-project/commit/fc3e6a81868a0c84e405622a64756e57f020ca37
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenCommonISel.h
M llvm/lib/CodeGen/CodeGenCommonISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/isinf.ll
M llvm/test/CodeGen/PowerPC/fp-classify.ll
Log Message:
-----------
DAG: Handle lowering unordered compare with inf (#100378)
Try to take advantage of the nan check behavior of fcmp.
x86_64 looks better, x86_32 looks worse.
Commit: c2018fa40fd081a10af4f3294362db9634d9a282
https://github.com/llvm/llvm-project/commit/c2018fa40fd081a10af4f3294362db9634d9a282
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/Support/FormatCommon.h
M llvm/include/llvm/Support/FormatVariadic.h
M llvm/lib/Support/FormatVariadic.cpp
M llvm/unittests/Support/FormatVariadicTest.cpp
Log Message:
-----------
[NFC][Support] Refactor FormatVariadic code. (#106610)
- Rename `Align` field in ReplacementItem/FmtAlign to `Width` to
accurately reflect its use.
- Change both `Width` and `Index` in ReplacementItem to 32-bit int
instead of size_t (as 64-bits seems excessive in this context).
- Eliminate the use of `Empty` ReplacementType, and use the
existing std::optional<> instead to indicate that.
- Eliminate some boilerplate type code in formatv().
- Eliminate the loop in `splitLiteralAndReplacement`. The existing
code will never loop back.
- Directly use constructor instead of std::make_pair.
Commit: be1958fd487dd58532a45b40be4a7152b80ec31a
https://github.com/llvm/llvm-project/commit/be1958fd487dd58532a45b40be4a7152b80ec31a
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/sve-bf16-converts.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Implement nxvbf16 fpextend to nxvf32/nxvf64. (#107253)
NOTE: There are no dedicated SVE instructions but bf16->f32 is just a
left shift because they share the same exponent range and from there
other convert instructions can be used.
Commit: 62e6c1ead7aedfbf973fb667537ff5cee4988da1
https://github.com/llvm/llvm-project/commit/62e6c1ead7aedfbf973fb667537ff5cee4988da1
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lld/MachO/Driver.cpp
M lld/MachO/OutputSegment.cpp
M lld/test/MachO/segprot.s
Log Message:
-----------
[lld/mac] Allow -segprot having stricter initprot than maxprot on mac (#107269)
...including for catalyst.
The usecase for this is to put certain security-critical variables into
a special segment/section that's mapped as read-only most of the time,
and that temporary gets remapped as writeable when these variables are
written to be the program. This protects against them being written to
by heap spraying attacks. This special section should be mapped as
read-only at program start, so using
`-segprot MY_PROTECTED_MEMORY_THINGER rw r`
to mark that segment as rw maxprot and r initprot is exactly what we
want.
lld has so far rejected mismatching initprot and maxprot.
ld64 doesn't reject this, but silently writes initprot into both fields
(!) It looks like this might not be fully intentional, see
https://crbug.com/41495919#comment5 and
http://crbug.com/41495919#comment8.
In any case, when postprocessing ld64's output to have different values
for initprot and maxprot, the dynamic loader seems to do the right thing
(see also the previous two links).
The same technique also works on Windows, using both link.exe and
lld-link.exe using `/SECTION:myprotsect,R`.
So, since this is useful, allow it when targeting macOS, and make it do
what you'd expect.
Since loader support for this on iOS is less clear, keep disallowing it
there for now.
See the PR for the program I used to check that this seems to work. (I
only checked on arm64 macOS 14.5 so far; will run this on many more
systems on bots once this is merged and rolled in.)
Commit: ce3648094d44e8c098396a353b215acecb363cda
https://github.com/llvm/llvm-project/commit/ce3648094d44e8c098396a353b215acecb363cda
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
Log Message:
-----------
[RISCV] Update V0Defs after moving Src in peepholes (#107359)
If we move a pseudo in tryReduceVL or foldVMV_V_V via ensureDominates,
its V0 definition may have changed so we need to update V0Defs.
This shouldn't have any functional change today since any pseudo which
uses V0 won't be able to move past a new definition.
However this will matter if we add a peephole to convert unmasked
pseudos to masked pseudos and add a use of V0.
Commit: 8e28f0471b20ed1148951bc7ffe5c503c43692ae
https://github.com/llvm/llvm-project/commit/8e28f0471b20ed1148951bc7ffe5c503c43692ae
Author: Michael Jones <michaelrj at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M libc/config/darwin/arm/entrypoints.txt
Log Message:
-----------
[libc] Correct the entrypoints list for ARM/darwin (#107331)
These entrypoints were added to every target without testing. They don't
work on ARM macs.
Commit: 2ed510dc9789ca0b9172f0593527bee9d53496c4
https://github.com/llvm/llvm-project/commit/2ed510dc9789ca0b9172f0593527bee9d53496c4
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.cpp
M lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.h
M lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py
Log Message:
-----------
[LLDB][Minidump] Extend the minidump x86_64 registers to include fs_base and gs_base (#106767)
A follow up to #106473 Minidump wasn't collecting fs or gs_base. This
patch extends the x86_64 register context and gated reading it behind an
lldb specific flag. Additionally these registers are explicitly checked
in the tests.
Commit: 953af0e7f1bcb42136be1a0ea9cdd5aa1fb74852
https://github.com/llvm/llvm-project/commit/953af0e7f1bcb42136be1a0ea9cdd5aa1fb74852
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M libcxx/include/__mdspan/extents.h
M libcxx/src/filesystem/error.h
M libcxx/src/filesystem/file_descriptor.h
M libcxx/src/filesystem/format_string.h
M libcxx/src/filesystem/operations.cpp
M libcxx/src/filesystem/posix_compat.h
M libcxx/src/filesystem/time_utils.h
M libcxx/src/include/atomic_support.h
M libcxx/src/memory_resource.cpp
M libcxx/src/system_error.cpp
M libcxx/test/benchmarks/ContainerBenchmarks.h
M libcxx/test/benchmarks/VariantBenchmarks.h
M libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.last_write_time/last_write_time.pass.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/is_swappable.pass.cpp
M libcxx/test/std/utilities/tuple/tuple.tuple/tuple.apply/apply.pass.cpp
M libcxx/test/support/archetypes.h
M libcxx/test/support/container_test_types.h
M libcxx/test/support/filesystem_test_helper.h
M libcxx/test/support/make_test_thread.h
M libcxx/test/support/parse_integer.h
M libcxx/test/support/uses_alloc_types.h
M libcxxabi/src/cxa_guard_impl.h
M libcxxabi/src/cxa_personality.cpp
Log Message:
-----------
[libc++][NFC] Increase consistency for namespace closing comments
Commit: eee2f02e4e28e54e5a38a1dbbd62ea6780909e16
https://github.com/llvm/llvm-project/commit/eee2f02e4e28e54e5a38a1dbbd62ea6780909e16
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M libcxx/include/__type_traits/datasizeof.h
Log Message:
-----------
[libc++][modules] Get rid of <cstddef> dependency in __datasizeof (#107394)
All the compilers we support also provide __builtin_offsetof, so avoid
using this macro and use the builtin directly instead. This allows
removing a dependency on `<cstddef>`, which is heavier than we need.
Commit: 5edede2db09d38cbf9397edb9bfd43b92265f660
https://github.com/llvm/llvm-project/commit/5edede2db09d38cbf9397edb9bfd43b92265f660
Author: Tim Gymnich <tgymnich at icloud.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
A llvm/test/CodeGen/DirectX/sign.ll
Log Message:
-----------
[DXIL] Add sign intrinsic part 2 (#101988)
makes progress on #70078
### Changes
- Added `int_dx_sign` intrinsic in `IntrinsicsDirectX.td`
- Added expansion for `int_dx_sign in `DXILIntrinsicExpansion.cpp`
- Added DXIL backend test case
### Related PRs
- https://github.com/llvm/llvm-project/pull/101987
- https://github.com/llvm/llvm-project/pull/101989
Commit: 0818c2801ecc5cb07b680bb77e24df90f35c74b9
https://github.com/llvm/llvm-project/commit/0818c2801ecc5cb07b680bb77e24df90f35c74b9
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
Log Message:
-----------
[WebAssembly] Simplify a switch-case in CFGStackify (NFC) (#107360)
This merges some `case`s using `[[fallthrough]]`, and make `DELEGATE` as
a separate `case`. (Previously the reason we didn't do that was not to
duplicate the code in `RewriteOperands`. But now that we've extracted it
into a lambda function in #107182 we can do it.
Commit: 18ad98e7947502da0c8f6dcbbf485bb34fe8d204
https://github.com/llvm/llvm-project/commit/18ad98e7947502da0c8f6dcbbf485bb34fe8d204
Author: Alex Langford <alangford at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.cpp
Log Message:
-----------
[lldb] Fix a format string in ClangASTSource (#107325)
Without this, LLDB asserts when enabling the expression logs.
Commit: 91a3c6f3d66b866bcda8a0f7d4815bc8f2dbd86c
https://github.com/llvm/llvm-project/commit/91a3c6f3d66b866bcda8a0f7d4815bc8f2dbd86c
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/spillfill-sve.mir
Log Message:
-----------
[AArch64] Remove redundant COPY from loadRegFromStackSlot (#107396)
This removes a redundant 'COPY' instruction that #81716 probably forgot
to remove.
This redundant COPY led to an issue because because code in
LiveRangeSplitting expects that the instruction emitted by
`loadRegFromStackSlot` is an instruction that accesses memory, which
isn't the case for the COPY instruction.
Commit: 54194e1506bdd6dc37988678a8047ad4d48168fa
https://github.com/llvm/llvm-project/commit/54194e1506bdd6dc37988678a8047ad4d48168fa
Author: Michal Terepeta <michalt at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
Log Message:
-----------
[RISCV][SiFive7] Change `Latency` of VCIX to the default (#106497)
Currently we multiply the default (`SiFive7GetCyclesDefault`) by 10, but
this turns out to be both surprising to our users and leads to worse
codegen in most cases. I think it's more natural to just keep the
default.
In the end the right solution is probably to have a separate scheduling
model for a particular VCIX coprocessor.
Commit: cf2ecc7c1c24dee6e3b70a836474a5ac553829b3
https://github.com/llvm/llvm-project/commit/cf2ecc7c1c24dee6e3b70a836474a5ac553829b3
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
Log Message:
-----------
[LV] Remove over-aggressive assert from 3fe6a064f15c.
There are some cases where only the first operand is marked for
truncation. In that case, the compare won't be truncated which would
incorrectly trigger the assertion.
It also shows that the check pre 3fe6a064f15c also considered compares
truncated that cannot be truncated.
Commit: 311ac6381649fa0f7cc495db8fa697d6a9b43988
https://github.com/llvm/llvm-project/commit/311ac6381649fa0f7cc495db8fa697d6a9b43988
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/tools/c-arcmt-test/c-arcmt-test.c
M clang/tools/c-index-test/c-index-test.c
M llvm/include/llvm/Support/AutoConvert.h
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/InitLLVM.cpp
M llvm/lib/Support/MemoryBuffer.cpp
M llvm/lib/Support/Unix/Path.inc
M llvm/lib/Support/Unix/Program.inc
M llvm/lib/Support/raw_ostream.cpp
M llvm/utils/count/count.c
Log Message:
-----------
[NFC][SystemZ][z/OS] Rename autoconversion-related functions to be less generic (#107399)
This patch renames the functions in AutoConvert.h/cpp to have a less
generic name because they are z/OS specific.
Commit: 5e25291b3c50873dbd0e2b3939b113bcff691460
https://github.com/llvm/llvm-project/commit/5e25291b3c50873dbd0e2b3939b113bcff691460
Author: vporpo <vporpodas at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/SandboxIRBench.cpp
Log Message:
-----------
[SandboxIR][Bench] Initial patch for performance tracking (#107296)
This patch adds a new benchmark suite for SandboxIR. It measures the
performance of some of the most commonly used API functions and compares
it against LLVM IR.
Commit: 3815f478bb4f1c724d36044a4e0bbd3352313322
https://github.com/llvm/llvm-project/commit/3815f478bb4f1c724d36044a4e0bbd3352313322
Author: Matthias Springer <me at m-sp.org>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir
M mlir/test/Transforms/test-legalize-type-conversion.mlir
M mlir/test/Transforms/test-legalizer.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Make materializations optional (#107109)
This commit makes source/target/argument materializations (via the
`TypeConverter` API) optional.
By default (`ConversionConfig::buildMaterializations = true`), the
dialect conversion infrastructure tries to legalize all unresolved
materializations right after the main transformation process has
succeeded. If at least one unresolved materialization fails to resolve,
the dialect conversion fails. (With an error message such as `failed to
legalize unresolved materialization ...`.) Automatic materializations
through the `TypeConverter` API can now be deactivated. In that case,
every unresolved materialization will show up as a
`builtin.unrealized_conversion_cast` op in the output IR.
There used to be a complex and error-prone analysis in the dialect
conversion that predicted the future uses of unresolved
materializations. Based on that logic, some casts (that were deemed to
unnecessary) were folded. This analysis was needed because folding
happened at a point of time when some IR changes (e.g., op replacements)
had not materialized yet.
This commit removes that analysis. Any folding of cast ops now happens
after all other IR changes have been materialized and the uses can
directly be queried from the IR. This simplifies the analysis
significantly. And certain helper data structures such as
`inverseMapping` are no longer needed for the analysis. The folding
itself is done by `reconcileUnrealizedCasts` (which also exists as a
standalone pass).
After casts have been folded, the remaining casts are materialized
through the `TypeConverter`, as usual. This last step can be deactivated
in the `ConversionConfig`.
`ConversionConfig::buildMaterializations = false` can be used to debug
error messages such as `failed to legalize unresolved materialization
...`. (It is also useful in case automatic materializations are not
needed.) The materializations that failed to resolve can then be seen as
`builtin.unrealized_conversion_cast` ops in the resulting IR. (This is
better than running with `-debug`, because `-debug` shows IR where some
IR changes have not been materialized yet.)
Note: This is a reupload of #104668, but with correct handling of cyclic
unrealized_conversion_casts that may be generated by the dialect
conversion.
Commit: ebc7f5578033248ce7de52a7f374332a2fc201aa
https://github.com/llvm/llvm-project/commit/ebc7f5578033248ce7de52a7f374332a2fc201aa
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
M llvm/test/MC/SystemZ/regs-bad.s
M llvm/test/MC/SystemZ/regs-good.s
Log Message:
-----------
[llvm][SystemZ] Fix parsing of `.cfi_undefined` with percent-less registers. (#107032)
This is just e3d658b applied to SystemZ.
An example of this being used in the wild:
https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/s390/s390-64/start.S;h=59eeb7e998227bdf32029cd074f0876c450404ea;hb=HEAD#l63
Commit: bedac64d36dce88ea25bd444c60eaac7d420550e
https://github.com/llvm/llvm-project/commit/bedac64d36dce88ea25bd444c60eaac7d420550e
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/MC/MCExpr.h
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZELFObjectWriter.cpp
M llvm/test/MC/SystemZ/fixups.s
Log Message:
-----------
[llvm][SystemZ] Recognize `@GOTENT` modifier in assembler. (#107038)
Closes #105918.
I'm unsure if there are other places that need to be updated for this.
Commit: 797f01198e8b41982916ba02d703bd6a96b5347e
https://github.com/llvm/llvm-project/commit/797f01198e8b41982916ba02d703bd6a96b5347e
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/runtime/assign.cpp
M flang/test/Lower/OpenMP/DelayedPrivatization/equivalence.f90
M flang/test/Lower/OpenMP/copyin-order.f90
M flang/test/Lower/OpenMP/copyin.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/copyprivate2.f90
M flang/test/Lower/OpenMP/default-clause-byref.f90
M flang/test/Lower/OpenMP/delayed-privatization-allocatable-array.f90
M flang/test/Lower/OpenMP/delayed-privatization-allocatable-firstprivate.f90
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/delayed-privatization-firstprivate.f90
M flang/test/Lower/OpenMP/implicit-dsa.f90
M flang/test/Lower/OpenMP/lastprivate-allocatable.f90
M flang/test/Lower/OpenMP/lastprivate-commonblock.f90
M flang/test/Lower/OpenMP/lastprivate-iv.f90
M flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90
M flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90
M flang/test/Lower/OpenMP/parallel-wsloop-lastpriv.f90
M flang/test/Lower/OpenMP/parallel-wsloop.f90
M flang/test/Lower/OpenMP/sections.f90
M flang/test/Lower/OpenMP/single.f90
M flang/test/Lower/OpenMP/statement-function.f90
M flang/test/Lower/OpenMP/task.f90
M flang/test/Lower/OpenMP/task2.f90
Log Message:
-----------
[flang][OpenMP] Make lastprivate work with reallocated variables (#106559)
Fixes https://github.com/llvm/llvm-project/issues/100951
Commit: 4d819daab91f54b90365927ba4b40e5a2eff26a9
https://github.com/llvm/llvm-project/commit/4d819daab91f54b90365927ba4b40e5a2eff26a9
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
Log Message:
-----------
[compiler-rt] Simplify definition of uptr
We can rely on the compiler-provided macro __UINTPTR_TYPE__ for all
non-MSVC compilers. I verified via https://godbolt.org/z/MW9KMjv5f that
this works for MSVC as well as GCC 4.5 Clang 3.0, so that should cover
all supported compilers.
This means we no longer need to explicitly handle new architectures
and as an added bonus also adds support for architectures where
`unsigned long long` cannot be used to hold pointers (e.g. CHERI).
Reviewed By: mstorsjo, vitalybuka
Pull Request: https://github.com/llvm/llvm-project/pull/106155
Commit: b2dbcf4dc1078fd62ef2295ff9696173a9991116
https://github.com/llvm/llvm-project/commit/b2dbcf4dc1078fd62ef2295ff9696173a9991116
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
Log Message:
-----------
[Presburger] Avoid repeated hash lookups (NFC) (#107426)
Commit: 7cf18ff22b626efb0dad6eb9daebea821faff438
https://github.com/llvm/llvm-project/commit/7cf18ff22b626efb0dad6eb9daebea821faff438
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
Log Message:
-----------
[LLVMIR] Avoid repeated hash lookups (NFC) (#107428)
Commit: 92e75c095bb380039f32218534f78c4580bf76e4
https://github.com/llvm/llvm-project/commit/92e75c095bb380039f32218534f78c4580bf76e4
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M flang/include/flang/Common/Fortran-features.h
M flang/lib/Semantics/check-io.cpp
M flang/module/__fortran_builtins.f90
A flang/test/Lower/CUDA/cuda-devptr.cuf
Log Message:
-----------
Reland [flang][cuda] Add c_devptr and bypass output semantic check (#107353)
Add a builtin type for c_devptr since it will need some special handling
for some function like c_f_pointer.
`c_ptr` is defined as a builtin type and was raising a semantic error if
you try to use it in a I/O statement. This patch add a check for c_ptr
and c_devptr to bypass the semantic check and allow the variables of
these types to be used in I/O.
This version of the patch keeps the semantic error when -pedantic is
enabled to align with gfortran.
Commit: d219c63b16851ba264b6495e3f63016d1c8b2aac
https://github.com/llvm/llvm-project/commit/d219c63b16851ba264b6495e3f63016d1c8b2aac
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/Expr.cpp
M clang/test/SemaCXX/source_location.cpp
Log Message:
-----------
[Clang] Fix crash with `source_location` in lambda declarators. (#107411)
Parsing lambdas require pushing a declaration context for the lambda, so
that parameters can be attached to it, before its trailing type is
parsed. DAt that point, partially-parsed lambda don't have a name that
can be computed for then.
This would cause source_location::current() to crash when use in the
decltype of a lambda().
We work around this by producing a source_location for an enclosing
scope in that scenario.
Fixes #67134
Commit: 18926666f509104c3f478444b282291ce19fab6a
https://github.com/llvm/llvm-project/commit/18926666f509104c3f478444b282291ce19fab6a
Author: SJW <48454132+sjw36 at users.noreply.github.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
Log Message:
-----------
[MLIR][SCF] Loop pipelining fails on failed predication (no assert) (#107442)
The SCFLoopPipelining allows predication on peeled or loop ops. When the
predicationFn returns a nullptr this signifies the op type is
unsupported and the pipeliner fails except in `emitPrologue` where it
asserts.
This patch fixes handling in the prologue to gracefully fail.
Commit: 3f1d0e1b1dfef0af0ca5f3315317246d0026fb70
https://github.com/llvm/llvm-project/commit/3f1d0e1b1dfef0af0ca5f3315317246d0026fb70
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M flang/lib/Semantics/expression.cpp
Log Message:
-----------
[flang] Silence warning in module file (#107421)
Most warnings should be silenced when processing the content of a module
file, since the warning should have also appeared when the module file
was generated. The case of an intrinsic type kind not being supported
for a target wasn't being suppressed; fix.
Fixes https://github.com/llvm/llvm-project/issues/107337.
Commit: 5e1e6a689c82aaf2b7af72e074c95889a11d3a78
https://github.com/llvm/llvm-project/commit/5e1e6a689c82aaf2b7af72e074c95889a11d3a78
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M mlir/lib/TableGen/Pattern.cpp
Log Message:
-----------
[TableGen] Avoid repeated hash lookups (NFC) (#107429)
Commit: a0dd90eb7dc318c9b3fccb9ba02e1e22fb073094
https://github.com/llvm/llvm-project/commit/a0dd90eb7dc318c9b3fccb9ba02e1e22fb073094
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/Status.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectMemoryTag.cpp
M lldb/source/Commands/CommandObjectStats.cpp
M lldb/source/Commands/CommandObjectTrace.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Core/ThreadedCommunication.cpp
M lldb/source/Core/ValueObjectVTable.cpp
M lldb/source/Core/ValueObjectVariable.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Host/common/FileCache.cpp
M lldb/source/Host/common/NativeProcessProtocol.cpp
M lldb/source/Host/common/TCPSocket.cpp
M lldb/source/Host/macosx/objcxx/Host.mm
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Interpreter/CommandObject.cpp
M lldb/source/Interpreter/OptionValueRegex.cpp
M lldb/source/Plugins/Language/CPlusPlus/BlockPointer.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/Minidump/ObjectFileMinidump.cpp
M lldb/source/Plugins/Platform/MacOSX/objcxx/PlatformiOSSimulatorCoreSimulatorSupport.mm
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerPlatform.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/StructuredData/DarwinLog/StructuredDataDarwinLog.cpp
M lldb/source/Target/ModuleCache.cpp
M lldb/source/Target/Platform.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Utility/Scalar.cpp
M lldb/source/Utility/Status.cpp
M lldb/source/Utility/StructuredData.cpp
M lldb/unittests/TestingSupport/Host/NativeProcessTestUtils.h
M lldb/unittests/Utility/StatusTest.cpp
Log Message:
-----------
[lldb] Make conversions from llvm::Error explicit with Status::FromEr… (#107163)
…ror() [NFC]
Commit: 9df592fb806b77d5fb0c7a9d5c9057d1626587e3
https://github.com/llvm/llvm-project/commit/9df592fb806b77d5fb0c7a9d5c9057d1626587e3
Author: David Green <david.green at arm.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/zext-shuffle.ll
Log Message:
-----------
[AArch64] Fold away zext of extract of uzp. (#107367)
Similar to #107201, this comes up from the lowering of zext of
deinterleaving shuffles. Patterns such as ext(extract_subvector(uzp(a,
b))) can be converted to a simple and to perform the extract/zext from a
uzp1. Uzp2 can be handled with an extra shift, and due to the existing
legalization we could have and / shift between which can be combined in.
Mostly this reduces instruction count or increases the amount of
parallelism in the sequence.
Commit: 362da640dd18e2ef960e0d2198fe8378104c4119
https://github.com/llvm/llvm-project/commit/362da640dd18e2ef960e0d2198fe8378104c4119
Author: vporpo <vporpodas at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/benchmarks/SandboxIRBench.cpp
Log Message:
-----------
[SandboxIR][Bench] Test RAUW (#107440)
Commit: f32e5bdcefcff80f4296f8f4abedc37dcda36d53
https://github.com/llvm/llvm-project/commit/f32e5bdcefcff80f4296f8f4abedc37dcda36d53
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp
M compiler-rt/lib/ctx_profile/CtxInstrProfiling.h
M llvm/include/llvm/Analysis/MLModelRunner.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
M llvm/lib/Analysis/FunctionPropertiesAnalysis.cpp
M llvm/lib/Analysis/MLInlineAdvisor.cpp
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
M llvm/unittests/ProfileData/PGOCtxProfReaderWriterTest.cpp
Log Message:
-----------
[NFC] Rename the `Nr` abbreviation to `Num` (#107151)
It's more clear. (This isn't exhaustive).
Commit: 9de972e3e1ecea506a3884bd2fc47570ce83e4df
https://github.com/llvm/llvm-project/commit/9de972e3e1ecea506a3884bd2fc47570ce83e4df
Author: Ming-Yi Lai <ming-yi.lai at mediatek.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGCall.h
Log Message:
-----------
[clang] Fix FnInfoOpts::operator&= and FnInfoOpts::operator|= not updating assigned operands (#107050)
This affects CodeGenTypes::arrangeCall. No test because the only current in-tree use of that function isn't affected.
Commit: 5515b086f35c2c1402234b9b94338f10fc9d16f7
https://github.com/llvm/llvm-project/commit/5515b086f35c2c1402234b9b94338f10fc9d16f7
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Utility/Status.h
M lldb/source/Expression/FunctionCaller.cpp
M lldb/source/Expression/LLVMUserExpression.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Utility/Status.cpp
Log Message:
-----------
Factor Process::ExecutionResultAsCString() into a global function (NFC)
Commit: 53d5ffea6be7216589599b6415c021f8bd13cd37
https://github.com/llvm/llvm-project/commit/53d5ffea6be7216589599b6415c021f8bd13cd37
Author: Fabian Parzefall <parzefall at meta.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/test/CodeGenCXX/vtable-available-externally.cpp
Log Message:
-----------
[clang] Check inline defs when emitting speculative vtable (#100785)
Clang should only emit an available_externally vtable when there are no
unused virtual inline functions. Currently, if such such a function is
declared without inline inside the class, but is defined inline outside
the class, Clang might emit the vtable as available_externally. This
happens because Clang only considers the declarations of vtable entries,
but not the definitions. This patch addresses this by inspecting the
definitions in addition to the declarations.
Commit: b798f4bd50bbf0f5eb46804afad10629797c73aa
https://github.com/llvm/llvm-project/commit/b798f4bd50bbf0f5eb46804afad10629797c73aa
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/bindings/python/python-swigsafecast.swig
M lldb/include/lldb/API/SBError.h
M lldb/include/lldb/API/SBValueList.h
M lldb/include/lldb/Core/ValueObjectConstResult.h
M lldb/include/lldb/Utility/Status.h
M lldb/source/API/SBBreakpoint.cpp
M lldb/source/API/SBBreakpointLocation.cpp
M lldb/source/API/SBBreakpointName.cpp
M lldb/source/API/SBDebugger.cpp
M lldb/source/API/SBError.cpp
M lldb/source/API/SBFile.cpp
M lldb/source/API/SBFormat.cpp
M lldb/source/API/SBFrame.cpp
M lldb/source/API/SBPlatform.cpp
M lldb/source/API/SBProcess.cpp
M lldb/source/API/SBSaveCoreOptions.cpp
M lldb/source/API/SBStructuredData.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/API/SBThread.cpp
M lldb/source/API/SBValue.cpp
M lldb/source/API/SBValueList.cpp
M lldb/source/API/SBWatchpoint.cpp
M lldb/source/Commands/CommandObjectCommands.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/ModuleList.cpp
M lldb/source/Core/ValueObject.cpp
M lldb/source/Core/ValueObjectCast.cpp
M lldb/source/Core/ValueObjectConstResult.cpp
M lldb/source/Core/ValueObjectDynamicValue.cpp
M lldb/source/Core/ValueObjectSyntheticFilter.cpp
M lldb/source/Expression/Materializer.cpp
M lldb/source/Expression/UserExpression.cpp
M lldb/source/Host/common/LockFileBase.cpp
M lldb/source/Host/common/NativeProcessProtocol.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/Platform/Android/AdbClient.cpp
M lldb/source/Plugins/Platform/Android/PlatformAndroidRemoteGDBServer.cpp
M lldb/source/Plugins/Platform/MacOSX/objcxx/PlatformiOSSimulatorCoreSimulatorSupport.h
M lldb/source/Plugins/Platform/MacOSX/objcxx/PlatformiOSSimulatorCoreSimulatorSupport.mm
M lldb/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp
M lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Target/ModuleCache.cpp
M lldb/source/Target/Platform.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Utility/Status.cpp
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
M lldb/unittests/Target/RemoteAwarePlatformTest.cpp
Log Message:
-----------
[lldb] Make deep copies of Status explicit (NFC) (#107170)
Commit: 7b760894f247f4fa1b27c01c767c8599c169f996
https://github.com/llvm/llvm-project/commit/7b760894f247f4fa1b27c01c767c8599c169f996
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
Log Message:
-----------
[lldb] Convert NativeProcessLinux to new Status API (NFC)
Commit: 54b10555c32e9677ce15c408296f92b35cd3d29c
https://github.com/llvm/llvm-project/commit/54b10555c32e9677ce15c408296f92b35cd3d29c
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M openmp/docs/SupportAndFAQ.rst
Log Message:
-----------
[OpenMP] LIBOMPTARGET_DEVICE_ARCHITECTURES requires semicolons (#107454)
If I use commas to delimit architectures in
`LIBOMPTARGET_DEVICE_ARCHITECTURES`, cmake for the runtimes complains:
```
Unknown GPU architecture 'sm_70,sm_80,sm_90'
```
Semicolons are required instead.
Commit: 3b426a8951caa543b65f20ff265353fd79f436e5
https://github.com/llvm/llvm-project/commit/3b426a8951caa543b65f20ff265353fd79f436e5
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
Log Message:
-----------
[lldb] Convert NativeProcessLinux to new Status API (NFC)
Commit: 3726f9c57537aff05bd6ecf309133ce05bebaf43
https://github.com/llvm/llvm-project/commit/3726f9c57537aff05bd6ecf309133ce05bebaf43
Author: Johannes Doerfert <johannes at jdoerfert.de>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
M llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll
M llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll
M llvm/test/Transforms/Attributor/assumes_info.ll
M llvm/test/Transforms/Attributor/cb_liveness_disabled.ll
M llvm/test/Transforms/Attributor/cb_liveness_enabled.ll
M llvm/test/Transforms/Attributor/phi_bug_pointer_info.ll
M llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
M llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
Log Message:
-----------
[Attributor][NFC] Pre-commits for #107439 (#107457)
Commit: 4ce8808dd96dd6f1380c4e27c04ff0a0a0fed12b
https://github.com/llvm/llvm-project/commit/4ce8808dd96dd6f1380c4e27c04ff0a0a0fed12b
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
Log Message:
-----------
[AMDGPU] Common up default value of -amdgpu-nsa-threshold. NFC.
The default value of 3 was specified in two places. Use the actual value
of the cl::init to avoid repeating it.
Commit: e6dece9f6947a50c36f714d3fc0d86c6ad9acc9b
https://github.com/llvm/llvm-project/commit/e6dece9f6947a50c36f714d3fc0d86c6ad9acc9b
Author: Johannes Doerfert <johannes at jdoerfert.de>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
Log Message:
-----------
[Attributor][FIX] Mark "may" accesses through call sites as such (#107439)
Before, we kept the call site access kind (may/must) when we translated
the access. However, the pointer we access it through (by passing it to
the callee) might not be the underlying object. We have similar logic
when we add store and load accesses.
Commit: 08533a3ee8f3a09a59cf6ac3be59198b26b7f739
https://github.com/llvm/llvm-project/commit/08533a3ee8f3a09a59cf6ac3be59198b26b7f739
Author: Johannes Doerfert <johannes at jdoerfert.de>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/include/Allocator.h
M offload/DeviceRTL/include/Configuration.h
A offload/DeviceRTL/include/DeviceTypes.h
A offload/DeviceRTL/include/DeviceUtils.h
M offload/DeviceRTL/include/Interface.h
M offload/DeviceRTL/include/LibC.h
M offload/DeviceRTL/include/Mapping.h
M offload/DeviceRTL/include/State.h
M offload/DeviceRTL/include/Synchronization.h
R offload/DeviceRTL/include/Types.h
R offload/DeviceRTL/include/Utils.h
M offload/DeviceRTL/src/Allocator.cpp
M offload/DeviceRTL/src/Configuration.cpp
M offload/DeviceRTL/src/Debug.cpp
A offload/DeviceRTL/src/DeviceUtils.cpp
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/DeviceRTL/src/Misc.cpp
M offload/DeviceRTL/src/Parallelism.cpp
M offload/DeviceRTL/src/Reduction.cpp
M offload/DeviceRTL/src/State.cpp
M offload/DeviceRTL/src/Synchronization.cpp
M offload/DeviceRTL/src/Tasking.cpp
R offload/DeviceRTL/src/Utils.cpp
M offload/DeviceRTL/src/Workshare.cpp
A offload/include/Shared/RefCnt.h
A offload/include/Shared/Types.h
M offload/include/Shared/Utils.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/GlobalHandler.cpp
M offload/plugins-nextgen/common/src/JIT.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/src/DeviceImage.cpp
M offload/src/omptarget.cpp
Log Message:
-----------
[Offload][NFC] Reorganize `utils::` and make Device/Host/Shared clearer (#100280)
We had three `utils::` namespaces, all with different "meaning" (host,
device, hsa_utils). We should, when we can, keep "include/Shared"
accessible from host and device, thus RefCountTy has been moved to a
separate header. `hsa_utils` was introduced to make `utils::` less
overloaded. And common functionality was de-duplicated, e.g.,
`utils::advance` and `utils::advanceVoidPtr` -> `utils:advancePtr`. Type
punning now checks for the size of the result to make sure it matches
the source type.
No functional change was intended.
Commit: 84bf0da34dd020090e05816fcbda305d1f422c27
https://github.com/llvm/llvm-project/commit/84bf0da34dd020090e05816fcbda305d1f422c27
Author: Johannes Doerfert <johannes at jdoerfert.de>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll
M llvm/test/Transforms/Attributor/align.ll
M llvm/test/Transforms/Attributor/memory_locations.ll
M llvm/test/Transforms/Attributor/range.ll
M llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll
M llvm/test/Transforms/Attributor/returned.ll
M llvm/test/Transforms/OpenMP/replace_globalization.ll
Log Message:
-----------
[Attributor][FIX] Ensure to always translate call site arguments (#107323)
When we propagate call site arguments we always need to translate them,
this is important as we ended up picking the function argument for a
recurisve call not the call site argument. `@recBad` and `@recGood` in
`returned.ll` show the problem as they used to transform them the same
way. The restructuring cleans the code up and helps derive more
"returned" arguments and better information in the presence of recursive
calls. The "dropped" attributes are simply dropped because we do not
query them anymore, not because we cannot derive them.
Commit: 52dca6ffae08fcd86cff32ab469870016a6aceb5
https://github.com/llvm/llvm-project/commit/52dca6ffae08fcd86cff32ab469870016a6aceb5
Author: vporpo <vporpodas at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
A llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
A llvm/test/Transforms/SandboxVectorizer/boilerplate.ll
Log Message:
-----------
[SandboxVec] Boilerplate (#107431)
This patch implements the new pass and registers it with the pass
manager. For context, this is a vectorizer that operates on Sandbox IR,
which is a transactional IR on top of LLVM IR.
Commit: 4634a480e0e5aa3116b397369fe3877a8dfe4dc0
https://github.com/llvm/llvm-project/commit/4634a480e0e5aa3116b397369fe3877a8dfe4dc0
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/common.cpp
M compiler-rt/lib/scudo/standalone/common.h
M compiler-rt/lib/scudo/standalone/linux.cpp
M compiler-rt/lib/scudo/standalone/platform.h
M compiler-rt/lib/scudo/standalone/release.h
Log Message:
-----------
[scudo] Add a method to use a hard-coded page size (#106646)
Currently, only Android supports using a hard-code page size. Make this
a bit more generic so any platform that wants to can use this.
In addition, add a getPageSizeLogCached() function since this value is
used in release.h and can avoid keeping this value around in objects.
Finally, change some of the release.h page size multiplies to shifts
using the new page size log value.
Commit: 247d3ea843cb20d8d75ec781cd603c8ececf8934
https://github.com/llvm/llvm-project/commit/247d3ea843cb20d8d75ec781cd603c8ececf8934
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
Log Message:
-----------
[SLP] Expand non-power-of-two bailout in TryToFindDuplicates
This fixes a crash noticed when doing a downstream merge. The
test case has been reduced, and is included in this commit.
The existing bailout for non-power-of-two vectors in TryToFindDuplicates
did not consider the case where the list being vectorized had no
root node. This allowed reshuffled scalars to slip through to code
which does not yet expect to handle it.
This was an existing bug (likely introduced by my ed03070e), but
made easier to hit by 63e8a1b1
Commit: 24684bb4a9791145a36a97477eb1fd525a122d8e
https://github.com/llvm/llvm-project/commit/24684bb4a9791145a36a97477eb1fd525a122d8e
Author: Evgenii Stepanov <eugeni.stepanov at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/fsanitize.c
M clang/test/Driver/fuchsia.c
Log Message:
-----------
[sanitizer] Delay sanitizer args parsing (#107280)
Delay sanitizer arg parsing until after -Xclang flags are forwarded to
the clang command line. This allows the check in hasTargetFeatureMTE to
pick up manually specified target feature, and enables the following:
-march=armv8-a -Xclang -target-feature -Xclang +mte
-fsanitize=memtag-stack
Commit: 3836d4acccbe87216133d08d75df509e95c291f0
https://github.com/llvm/llvm-project/commit/3836d4acccbe87216133d08d75df509e95c291f0
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Host/windows/ConnectionGenericFileWindows.cpp
Log Message:
-----------
[lldb] Convert ConnectionGenericFileWindows.cpp to new Status API (NFC)
Commit: f00c946c2da0caf6da4a49e87ac905a8b1d2e8b6
https://github.com/llvm/llvm-project/commit/f00c946c2da0caf6da4a49e87ac905a8b1d2e8b6
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Host/windows/MainLoopWindows.cpp
Log Message:
-----------
[lldb] Convert MainLoopWindows.cpp to new Status API (NFC)
Commit: 64498c54831bed9cf069e0923b9b73678c6451d8
https://github.com/llvm/llvm-project/commit/64498c54831bed9cf069e0923b9b73678c6451d8
Author: Mingming Liu <mingmingl at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/include/lld/Common/CommonLinkerContext.h
Log Message:
-----------
[LTO][ELF][lld] Use unique string saver in ELF bitcode symbol parsing (#106670)
lld ELF
[BitcodeFile](https://github.com/llvm/llvm-project/blob/a527248a3c2d638b0c92a06992f3f1c1f80842ad/lld/ELF/InputFiles.h#L328)
uses [string
saver](https://github.com/llvm/llvm-project/blob/a527248a3c2d638b0c92a06992f3f1c1f80842ad/lld/include/lld/Common/CommonLinkerContext.h#L57)
to keep copies of bitcode symbols. Symbol duplication is very common
when compiling application binaries.
This change proposes to introduce a UniqueStringSaver in lld context and
use it for bitcode symbol parsing. The implementation covers ELF only.
Similar opportunities should exist on other (COFF, MachO, wasm) formats.
For an internal production binary where lto indexing takes ~10GiB
originally, this changes optimizes away ~800MiB (~7.8%), measured by
https://github.com/google/pprof. Flame graph breaks down memory by usage
call stacks and agrees with this measurement.
Commit: 50be455ab88b17872cd620698156b4058dc92f58
https://github.com/llvm/llvm-project/commit/50be455ab88b17872cd620698156b4058dc92f58
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/test/TableGen/intrinsic-struct.td
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
Log Message:
-----------
[TableGen] Add check for number of intrinsic return values (#107326)
Fail if we see an intrinsic that returns more than the supported number
of return values.
Intrinsics can return only upto a certain nyumber of values, as defined
by the `IIT_RetNumbers` list in `Intrinsics.td`. Currently, if we define
an intrinsic that exceeds the limit, llvm-tblgen crashes. Instead, read
this limit and fail if it's exceeded with a proper error message.
Commit: 3380dae2f0d6b8035744da573c4508b98c80045c
https://github.com/llvm/llvm-project/commit/3380dae2f0d6b8035744da573c4508b98c80045c
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lld/MachO/BPSectionOrderer.cpp
Log Message:
-----------
[lld][InstrProf] Refactor BPSectionOrderer.cpp (#107347)
Refactor some code in `BPSectionOrderer.cpp` in preparation for
https://github.com/llvm/llvm-project/pull/107348.
* Rename `constructNodesForCompression()` -> `getUnsForCompression()`
and return a `SmallVector` directly rather than populating a vector
alias
* Pass `duplicateSectionIdxs` as a pointer to make it possible to skip
finding (nearly) duplicate sections
* Combine `duplicate{Function,Data}SectionIdxs` into one variable
* Compute all `BPFunctionNode` vectors at the end (like
`nodesForStartup`)
There should be no functional change.
Commit: 7ea9f0d85fc3dc80b45e6ba7087c41c6f2481f07
https://github.com/llvm/llvm-project/commit/7ea9f0d85fc3dc80b45e6ba7087c41c6f2481f07
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
Log Message:
-----------
[SandboxVec][NFC] Remove unused header files
Commit: 73514f6831cfcea49f33fb9e31db0141b05532f2
https://github.com/llvm/llvm-project/commit/73514f6831cfcea49f33fb9e31db0141b05532f2
Author: wldfngrs <wldfngrs at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/sighandler_t.h
M libc/src/signal/linux/signal.cpp
M libc/src/signal/signal.h
M libc/test/src/signal/CMakeLists.txt
M libc/test/src/signal/signal_test.cpp
Log Message:
-----------
[libc] Add proxy header for __sighandler_t type (#107354)
Added proxy headers for __sighandler_t type, modified the corresponding
CMakeLists.txt files and test files
Commit: e44a67543c0b6a3a2307362f5bbcf54cd6de6a8e
https://github.com/llvm/llvm-project/commit/e44a67543c0b6a3a2307362f5bbcf54cd6de6a8e
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
Log Message:
-----------
AMDGPU: Add a few unsupported checks for llvm.fptrunc.round intrinsic (#107330)
A check here can be removed when we implement support for the
corresponding types/mode.
Commit: 1e98aa4730b1b3b93205af74be26e04d5f876d10
https://github.com/llvm/llvm-project/commit/1e98aa4730b1b3b93205af74be26e04d5f876d10
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Host/windows/ConnectionGenericFileWindows.cpp
Log Message:
-----------
[lldb] Convert ConnectionGenericFileWindows.cpp to new Status API (NFC)
Commit: bd840a40042c2c67f56079493d0bcdbfc70325ba
https://github.com/llvm/llvm-project/commit/bd840a40042c2c67f56079493d0bcdbfc70325ba
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SMInstructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
Log Message:
-----------
[AMDGPU] Add target intrinsic for s_prefetch_data (#107133)
Commit: c1c42518c1356e78a10bf252a4a5a643b2bb9efd
https://github.com/llvm/llvm-project/commit/c1c42518c1356e78a10bf252a4a5a643b2bb9efd
Author: vporpo <vporpodas at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
A llvm/test/Transforms/SandboxVectorizer/X86/no_implicit_float.ll
Log Message:
-----------
[SandboxVec] Early return checks (#107465)
This patch implements a couple of early return checks.
Commit: 169d453429ca9015046b42719ff5d13cda5d2c6f
https://github.com/llvm/llvm-project/commit/169d453429ca9015046b42719ff5d13cda5d2c6f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/include/llvm/ADT/SmallVector.h
M llvm/lib/Support/SmallVector.cpp
Log Message:
-----------
[ADT] Declare replaceAllocation in SmallVector.cpp (NFC) (#107469)
This patch changes replaceAllocation to a static function while moving
the declaration to SmallVector.cpp. Note that:
- replaceAllocation is used only within SmallVector.cpp.
- replaceAllocation doesn't access any class members.
Commit: 6d3725924fe6adf0d490697327938de9c3516cbe
https://github.com/llvm/llvm-project/commit/6d3725924fe6adf0d490697327938de9c3516cbe
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/unconventional-assign-operator.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/avoid-nested-conditional-operator.rst
Log Message:
-----------
[clang-tidy][NFC] remove autosar link in documents (#107412)
As discussion in
https://discourse.llvm.org/t/clang-tidy-rfc-add-autosar-c-14-clang-tidy-module/59223/12.
We should not link clang-tidy check with AUTOSAR rules.
Commit: c8834527b729c8c89f453d215e667047fd948aa1
https://github.com/llvm/llvm-project/commit/c8834527b729c8c89f453d215e667047fd948aa1
Author: Tai Ly <tai.ly at arm.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/Utils/ConversionUtils.h
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Tosa/Utils/ConversionUtils.cpp
Log Message:
-----------
[TOSA] Move CreateOpAndInfer into ConversionUtils.h (#106122)
This moves CreateOpAndInfer from TF legalize_util.h into
ConversionUtils.h
also removed duplicate createOpAndInfer function from
TosaDecomposeTransposeConv.cpp
Renamed to CreateOpAndInferShape so we can upstream this independently
of tensorflow (otherwise a redefinition error would break TF compile if
not upstreamed together with removal of CreateOpAndInfer in TF)
---------
Signed-off-by: Tai Ly <tai.ly at arm.com>
Commit: 67fb8d15c993f5695cf944b16022a9ee49b9252d
https://github.com/llvm/llvm-project/commit/67fb8d15c993f5695cf944b16022a9ee49b9252d
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
Log Message:
-----------
[lldb] Convert ProcessDebugger.cpp to new Status API (NFC)
Commit: e0a93d3505bf6b4c87e819db7a871e0ce4d4100c
https://github.com/llvm/llvm-project/commit/e0a93d3505bf6b4c87e819db7a871e0ce4d4100c
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
Log Message:
-----------
[lldb] Convert ProcessWindows.cpp to new Status API (NFC)
Commit: 1be9a80768a03ea9bd2bfbb03762b2bc3c350007
https://github.com/llvm/llvm-project/commit/1be9a80768a03ea9bd2bfbb03762b2bc3c350007
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/test/Dialect/Affine/scalrep.mlir
Log Message:
-----------
[mlir][affine] Fix the crash due to the simultaneous replacement store (#90829)
`AffineScalarReplacement` should forward the memref store op to load op
only if the store op reaches the load. But it now checks the
reachability only if these ops are in the same block, which causes the
crash reported in https://github.com/llvm/llvm-project/issues/76309.
We need to check the reachability even if they are both in the same
block, which rescues the case where consecutive store operations are
written before the load op.
Commit: d1756165a9066f907b88d51dd8e3ffee15a8cc1e
https://github.com/llvm/llvm-project/commit/d1756165a9066f907b88d51dd8e3ffee15a8cc1e
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/ICF.cpp
M lld/MachO/InputSection.cpp
M lld/MachO/InputSection.h
M lld/MachO/MapFile.cpp
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
M lld/MachO/SyntheticSections.cpp
M lld/MachO/Target.h
A lld/test/MachO/icf-safe-thunks.ll
Log Message:
-----------
[lld-macho][arm64] Enhance safe ICF with thunk-based deduplication (#106573)
Currently, our `safe` ICF mode only merges non-address-significant code,
leaving duplicate address-significant functions in the output. This
patch introduces `safe_thunks` ICF mode, which keeps a single master
copy of each function and replaces address-significant duplicates with
thunks that branch to the master copy.
Currently `--icf=safe_thunks` is only supported for `arm64`
architectures.
**Perf stats for a large binary:**
| ICF Option | Total Size | __text Size | __unwind_info | % total |
|-------------------|------------|-------------|---------------------|---------------------------|
| `--icf=none` | 91.738 MB | 55.220 MB | 1.424 MB | 0% |
| `--icf=safe` | 85.042 MB | 49.572 MB | 1.168 MB | 7.30% |
| `--icf=safe_thunks` | 84.650 MB | 49.219 MB | 1.143 MB | 7.72% |
| `--icf=all` | 82.060 MB | 48.726 MB | 1.111 MB | 10.55% |
So overall we can expect a `~0.45%` binary size reduction for a typical
large binary compared to the `--icf=safe` option.
**Runtime:**
Linking the above binary took ~10 seconds. Comparing the link
performance of --icf=safe_thunks vs --icf=safe, a ~2% slowdown was
observed.
Commit: b525ead65c224cd2e73298c7a735f8136a926c35
https://github.com/llvm/llvm-project/commit/b525ead65c224cd2e73298c7a735f8136a926c35
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[SandboxIR] Add bazel support (#107486)
Commit: d7dd2c468fecae871ba67e891a3519c758c94b63
https://github.com/llvm/llvm-project/commit/d7dd2c468fecae871ba67e891a3519c758c94b63
Author: ziqingluo-90 <ziqing_luo at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsage.h
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
A clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions-inline-namespace.cpp
A clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-test-unreachable.cpp
Log Message:
-----------
Re-land "[-Wunsafe-buffer-usage] Warning Libc functions (#101583)"
Revert commit 23457964392d00fc872fa6021763859024fb38da, and re-land
with a new flag "-Wunsafe-buffer-usage-in-libc-call" for the new
warning.
(rdar://117182250)
Commit: a84baef74892dc294eb65bb2a1ea2339be13e8b2
https://github.com/llvm/llvm-project/commit/a84baef74892dc294eb65bb2a1ea2339be13e8b2
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[gn build] Port 52dca6ffae08
Commit: 2949720c2e55d2695682d6412d5afe45b167cb1e
https://github.com/llvm/llvm-project/commit/2949720c2e55d2695682d6412d5afe45b167cb1e
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
Log Message:
-----------
[RISCV] Move vmerge same mask peephole to RISCVVectorPeephole (#106108)
We currently fold a vmerge.vvm into its true operand if the true operand
is a masked pseudo with the same mask.
We can move this over to RISCVVectorPeephole by instead splitting it up
into a smaller peephole which converts it to a vmv.v.v first. The
existing foldVMV_V_V peephole will then take care of folding it if
needed.
This is very similar to the existing all-ones mask peephole and we could
potentially do it inside of it. I opted to put it in a separate peephole
to make it easier to reason about, given that the duplication is small,
but I could be persuaded either way.
Commit: 11084c5c49f8bb7825f81adc5b7140b3506fe253
https://github.com/llvm/llvm-project/commit/11084c5c49f8bb7825f81adc5b7140b3506fe253
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.cpp
Log Message:
-----------
[lldb] Convert DebuggerThread.cpp to new Status API (NFC)
Commit: 16df489fdae23e77eb5180e4d4dc99b07421bf77
https://github.com/llvm/llvm-project/commit/16df489fdae23e77eb5180e4d4dc99b07421bf77
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/ClangSyntaxEmitter.cpp
M llvm/include/llvm/TableGen/DirectiveEmitter.h
M llvm/include/llvm/TableGen/Record.h
M llvm/lib/TableGen/Record.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/Common/SubtargetFeatureInfo.cpp
M llvm/utils/TableGen/Common/SubtargetFeatureInfo.h
M llvm/utils/TableGen/ExegesisEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/TableGen/SubtargetEmitter.cpp
M llvm/utils/TableGen/TableGen.cpp
M mlir/include/mlir/TableGen/GenInfo.h
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/OmpOpGen.cpp
M mlir/tools/mlir-tblgen/OpDocGen.cpp
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/tools/tblgen-to-irdl/OpDefinitionsGen.cpp
Log Message:
-----------
[TableGen] Add const variants of accessors for backend (#106658)
Split RecordKeeper `getAllDerivedDefinitions` family of functions into
two variants:
(a) non-const ones that return vectors of `Record *` and
(b) const ones, that return vector/ArrayRef of `const Record *`.
This will help gradual migration of TableGen backends to use
`const RecordKeeper` and by implication change code to work
with const pointers and better const correctness.
Existing backends are not yet compatible with the const family of
functions, so change them to use a non-constant `RecordKeeper`
reference, till they are migrated.
Commit: 616a8ce6203d8c7569266bfaf163e74df1f440ad
https://github.com/llvm/llvm-project/commit/616a8ce6203d8c7569266bfaf163e74df1f440ad
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly annotate braces in macro definition (#107352)
Also add a test case for #107096.
Fixes #106418.
Commit: c02fd17c1e20615c9e6174a3f8ad4ef0ec5ebbec
https://github.com/llvm/llvm-project/commit/c02fd17c1e20615c9e6174a3f8ad4ef0ec5ebbec
Author: donald chen <chenxunyu1993 at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
Log Message:
-----------
[mlir] [scf] fix crash when conversion from scf to control flow (#107221)
This patch fixed a crash when scf.parallel's region donesn't terminate
with reduce op. This can happend in dialect conversion.
Commit: 33ceb2dd7596a05277fd246865862df6b03cf976
https://github.com/llvm/llvm-project/commit/33ceb2dd7596a05277fd246865862df6b03cf976
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
Log Message:
-----------
[clang-tidy] Avoid repeated hash lookups (NFC) (#107490)
Commit: 144314eaa5ca7f44817cf0ac162dbd17a5d88391
https://github.com/llvm/llvm-project/commit/144314eaa5ca7f44817cf0ac162dbd17a5d88391
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] Avoid repeated hash lookups (NFC) (#107491)
Commit: 5acd9d11373ca67f0d4baf17a78ebb56193a7df0
https://github.com/llvm/llvm-project/commit/5acd9d11373ca67f0d4baf17a78ebb56193a7df0
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
Log Message:
-----------
[clang][scan] Report module dependencies in topological order (#107474)
Commit: ede40da1f8c1e91601b985cd32ad785aa8806880
https://github.com/llvm/llvm-project/commit/ede40da1f8c1e91601b985cd32ad785aa8806880
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/invalid.mlir
Log Message:
-----------
[mlir][tensor] Add check for indices of `tensor.gather` (#106894)
This patch add a check for indices of `tensor.gather` and
`tensor.scatter`. For that the length of gather_dims/scatter_dims should
match the size of last dimension of the indices. Fix #94901.
Commit: 8e35c86977ce5529a9387657321ac9fefcdae5b5
https://github.com/llvm/llvm-project/commit/8e35c86977ce5529a9387657321ac9fefcdae5b5
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/HLSL/RWBuffer-AST.hlsl
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
M clang/test/ParserHLSL/hlsl_is_rov_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_handle_attrs.hlsl
M clang/test/SemaHLSL/resource_binding_attr_error.hlsl
M clang/test/SemaHLSL/resource_binding_attr_error_resource.hlsl
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
Log Message:
-----------
[HLSL] Apply resource attributes to the resource type rather than the handle member (#107160)
Converts existing resource attributes `[[hlsl::resource_class(..)]]` and
`[[is_rov]]` from declaration attributes to type attributes.
During type attribute processing all HLSL resource type attributes are
validated and collected by `SemaHLSL`
(`SemaHLSL::handleResourceTypeAttr`). At the end of the declaration they
are be combined into a single `HLSLAttributedResourceType` instance
(`SemaHLSL::ProcessResourceTypeAttributes`) that wraps the original type
and stores all of the necessary information about the resource.
`SemaHLSL` will also need to short-term-store the `TypeLoc` information
for the newly created type that will be grabbed by `TypeSpecLocFiller`
soon after it is created.
Updates all places that expected resource attributes on declarations
like resource binding diagnostic, builtin types in
HLSLExternalSemaSource, or codegen.
Also includes implementation of
`TreeTransform<Derived>::TransformHLSLAttributedResourceType` that
enables the use of attributed resource types inside templates.
Fixes #104861
Part 2/2
Commit: 77f1b481b884621c12cde5f2ce6f080f11dbbbcc
https://github.com/llvm/llvm-project/commit/77f1b481b884621c12cde5f2ce6f080f11dbbbcc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/CodeGenCommonISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/X86/is_fpclass.ll
Log Message:
-----------
DAG: Lower single infinity is.fpclass tests to fcmp (#100380)
InstCombine also should have taken care of this, but this
should be helpful when the fcmp based lowering strategy tries
to combine multiple tests.
Commit: 093b8bfe6b64c916647ae64af8066df22bb6ea65
https://github.com/llvm/llvm-project/commit/093b8bfe6b64c916647ae64af8066df22bb6ea65
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
A llvm/lib/Target/RISCV/RISCVCallingConv.cpp
A llvm/lib/Target/RISCV/RISCVCallingConv.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
Log Message:
-----------
[RISCV] Separate the calling convention handlers into their own file. NFC (#107484)
These are used by both SelectionDAG and GlobalISel and are separate from
RISCVTargetLowering.
Having a separate file is how other targets are structured. Though other
targets generate most of their calling convention code through tablegen.
I moved the `CC_RISV` functions from the `llvm::RISCV` namespace to
`llvm::`. That's what the tablegen code on other targets does and the
functions already have RISCV in their name. `RISCVCCAssignFn` is moved
from `RISCVTargetLowering` to the `llvm` namespace.
Commit: dcfa147c9d9569ea44cb0f0b6981f69a62b87f71
https://github.com/llvm/llvm-project/commit/dcfa147c9d9569ea44cb0f0b6981f69a62b87f71
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn build] Port 093b8bfe6b64
Commit: 24267a7e14b35f41ab55e15ba12bb80c82881941
https://github.com/llvm/llvm-project/commit/24267a7e14b35f41ab55e15ba12bb80c82881941
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
Log Message:
-----------
AMDGPU: Add f64 to f32 support for llvm.fptrunc.round (#107481)
Commit: ddf40e0132cdfb9443e8dce9ca18d4f5595fb73c
https://github.com/llvm/llvm-project/commit/ddf40e0132cdfb9443e8dce9ca18d4f5595fb73c
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParser.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/test/Shell/SymbolFile/DWARF/x86/type-definition-search.cpp
Log Message:
-----------
[lldb] Correctly reconstruct simplified names for type units (#107240)
We need to resolve the type signature to get a hold of the template
argument dies.
The associated test case passes even without this patch, but it only
does it by accident (because the subsequent code considers the types to
be in an anonymous namespace and this not subject to uniqueing). This
will change once my other patch starts resolving names correctly.
Commit: 9c72a308d839a27ffcbb0c67104baceb1871c50e
https://github.com/llvm/llvm-project/commit/9c72a308d839a27ffcbb0c67104baceb1871c50e
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[clang][ASTImporter] New fix for default template parameter values. (#101836)
Commit e4440b8 added a change that introduced new crash in an
incorrectly handled case. This is fixed here. Default argument
definition or inheritance is preserved in the "To" AST compared to
the "From". If the default argument is defined already in the "To"
AST it can be duplicated at the import.
Commit: 6fb39e496411a64af8fa5484385ef3ff42d2a5f4
https://github.com/llvm/llvm-project/commit/6fb39e496411a64af8fa5484385ef3ff42d2a5f4
Author: Patryk Wychowaniec <pwychowaniec at pm.me>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/test/MC/AVR/hex-immediates.s
M llvm/test/MC/AVR/inst-adc.s
M llvm/test/MC/AVR/inst-add.s
M llvm/test/MC/AVR/inst-adiw.s
M llvm/test/MC/AVR/inst-and.s
M llvm/test/MC/AVR/inst-andi.s
M llvm/test/MC/AVR/inst-asr.s
M llvm/test/MC/AVR/inst-bld.s
M llvm/test/MC/AVR/inst-brbc.s
M llvm/test/MC/AVR/inst-brbs.s
M llvm/test/MC/AVR/inst-brcc.s
M llvm/test/MC/AVR/inst-brcs.s
M llvm/test/MC/AVR/inst-break.s
M llvm/test/MC/AVR/inst-breq.s
M llvm/test/MC/AVR/inst-brge.s
M llvm/test/MC/AVR/inst-brhc.s
M llvm/test/MC/AVR/inst-brhs.s
M llvm/test/MC/AVR/inst-brid.s
M llvm/test/MC/AVR/inst-brie.s
M llvm/test/MC/AVR/inst-brlo.s
M llvm/test/MC/AVR/inst-brlt.s
M llvm/test/MC/AVR/inst-brmi.s
M llvm/test/MC/AVR/inst-brne.s
M llvm/test/MC/AVR/inst-brpl.s
M llvm/test/MC/AVR/inst-brsh.s
M llvm/test/MC/AVR/inst-brtc.s
M llvm/test/MC/AVR/inst-brts.s
M llvm/test/MC/AVR/inst-brvc.s
M llvm/test/MC/AVR/inst-brvs.s
M llvm/test/MC/AVR/inst-bst.s
M llvm/test/MC/AVR/inst-call.s
M llvm/test/MC/AVR/inst-cbi.s
M llvm/test/MC/AVR/inst-cbr.s
M llvm/test/MC/AVR/inst-clr.s
M llvm/test/MC/AVR/inst-com.s
M llvm/test/MC/AVR/inst-cp.s
M llvm/test/MC/AVR/inst-cpc.s
M llvm/test/MC/AVR/inst-cpi.s
M llvm/test/MC/AVR/inst-cpse.s
M llvm/test/MC/AVR/inst-dec.s
M llvm/test/MC/AVR/inst-des.s
M llvm/test/MC/AVR/inst-eicall.s
M llvm/test/MC/AVR/inst-eijmp.s
M llvm/test/MC/AVR/inst-elpm.s
M llvm/test/MC/AVR/inst-eor.s
M llvm/test/MC/AVR/inst-family-set-clr-flag.s
M llvm/test/MC/AVR/inst-fmul.s
M llvm/test/MC/AVR/inst-fmuls.s
M llvm/test/MC/AVR/inst-fmulsu.s
M llvm/test/MC/AVR/inst-icall.s
M llvm/test/MC/AVR/inst-ijmp.s
M llvm/test/MC/AVR/inst-in.s
M llvm/test/MC/AVR/inst-inc.s
M llvm/test/MC/AVR/inst-jmp.s
M llvm/test/MC/AVR/inst-lac.s
M llvm/test/MC/AVR/inst-las.s
M llvm/test/MC/AVR/inst-lat.s
M llvm/test/MC/AVR/inst-ld.s
M llvm/test/MC/AVR/inst-ldd.s
M llvm/test/MC/AVR/inst-ldi.s
M llvm/test/MC/AVR/inst-lds.s
M llvm/test/MC/AVR/inst-lpm.s
M llvm/test/MC/AVR/inst-lsl.s
M llvm/test/MC/AVR/inst-lsr.s
M llvm/test/MC/AVR/inst-mov.s
M llvm/test/MC/AVR/inst-movw.s
M llvm/test/MC/AVR/inst-mul.s
M llvm/test/MC/AVR/inst-muls.s
M llvm/test/MC/AVR/inst-mulsu.s
M llvm/test/MC/AVR/inst-neg.s
M llvm/test/MC/AVR/inst-nop.s
M llvm/test/MC/AVR/inst-or.s
M llvm/test/MC/AVR/inst-ori.s
M llvm/test/MC/AVR/inst-out.s
M llvm/test/MC/AVR/inst-pop.s
M llvm/test/MC/AVR/inst-push.s
M llvm/test/MC/AVR/inst-rcall.s
M llvm/test/MC/AVR/inst-ret.s
M llvm/test/MC/AVR/inst-reti.s
M llvm/test/MC/AVR/inst-rjmp.s
M llvm/test/MC/AVR/inst-rol.s
M llvm/test/MC/AVR/inst-ror.s
M llvm/test/MC/AVR/inst-sbc.s
M llvm/test/MC/AVR/inst-sbci.s
M llvm/test/MC/AVR/inst-sbi.s
M llvm/test/MC/AVR/inst-sbic.s
M llvm/test/MC/AVR/inst-sbis.s
M llvm/test/MC/AVR/inst-sbiw.s
M llvm/test/MC/AVR/inst-sbr.s
M llvm/test/MC/AVR/inst-sbrc.s
M llvm/test/MC/AVR/inst-sbrs.s
M llvm/test/MC/AVR/inst-ser.s
M llvm/test/MC/AVR/inst-sleep.s
M llvm/test/MC/AVR/inst-spm.s
M llvm/test/MC/AVR/inst-st.s
M llvm/test/MC/AVR/inst-std.s
M llvm/test/MC/AVR/inst-sts.s
M llvm/test/MC/AVR/inst-sub.s
M llvm/test/MC/AVR/inst-subi.s
M llvm/test/MC/AVR/inst-swap.s
M llvm/test/MC/AVR/inst-tst.s
M llvm/test/MC/AVR/inst-wdr.s
M llvm/test/MC/AVR/inst-xch.s
M llvm/test/MC/AVR/modifiers.s
M llvm/test/MC/AVR/registers.s
M llvm/test/MC/AVR/relocations-abs.s
M llvm/test/MC/AVR/relocations.s
M llvm/test/MC/AVR/separator.s
M llvm/test/MC/AVR/syntax-reg-int-literal.s
M llvm/test/MC/AVR/syntax-reg-pair.s
Log Message:
-----------
[AVR][NFC] Reformat MC tests (#107068)
Commit: 30a9cace807d4b5c98f2d0e2bd5bdea49061c8b8
https://github.com/llvm/llvm-project/commit/30a9cace807d4b5c98f2d0e2bd5bdea49061c8b8
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
Log Message:
-----------
[clang][ASTImporter] Fix -Wpessimizing-move in ASTImporter.cpp (NFC)
/llvm-project/clang/lib/AST/ASTImporter.cpp:371:20: error: moving a local object in a return statement prevents copy elision [-Werror,-Wpessimizing-move]
return std::move(Err);
^
/llvm-project/clang/lib/AST/ASTImporter.cpp:371:20: note: remove std::move call here
return std::move(Err);
^~~~~~~~~~ ~
/llvm-project/clang/lib/AST/ASTImporter.cpp:380:22: error: moving a local object in a return statement prevents copy elision [-Werror,-Wpessimizing-move]
return std::move(Err);
^
/llvm-project/clang/lib/AST/ASTImporter.cpp:380:22: note: remove std::move call here
return std::move(Err);
^~~~~~~~~~ ~
2 errors generated.
Commit: 62fec3d23d2325869e6eba0263b0b9f834c2067f
https://github.com/llvm/llvm-project/commit/62fec3d23d2325869e6eba0263b0b9f834c2067f
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
Log Message:
-----------
[NFCI] [ClangScanDeps] [P1689] Use PreprocessorOnly Action for P1689
It is fine enough to use PreprocessorOnly action for P1689 format. We
don't need to read any PCH or module files.
Commit: 4b2c950de5611a94defb00cbd66226eb02350938
https://github.com/llvm/llvm-project/commit/4b2c950de5611a94defb00cbd66226eb02350938
Author: wanglei <wanglei at loongson.cn>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
A llvm/test/CodeGen/LoongArch/ctpop-with-lsx.ll
Log Message:
-----------
[test][LoongArch] Pre-commit test for optimize CTPOP. NFC
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/106940
Commit: df93327c1ad9db7ab6c71a97bc093ce7133659d8
https://github.com/llvm/llvm-project/commit/df93327c1ad9db7ab6c71a97bc093ce7133659d8
Author: wanglei <wanglei at loongson.cn>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/ctpop-with-lsx.ll
Log Message:
-----------
[LoongArch] Legalize ISD::CTPOP for GRLenVT type with LSX
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/106941
Commit: 2ee7183e38b91525ebd803144a588a9548ca9a46
https://github.com/llvm/llvm-project/commit/2ee7183e38b91525ebd803144a588a9548ca9a46
Author: wanglei <wanglei at loongson.cn>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
A llvm/test/Transforms/LoopIdiom/LoongArch/lit.local.cfg
A llvm/test/Transforms/LoopIdiom/LoongArch/popcnt.ll
Log Message:
-----------
[LoongArch] Add TTI support for cpop with LSX
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/106961
Commit: 5602bd5a42897e9323dc0275655186397778c67b
https://github.com/llvm/llvm-project/commit/5602bd5a42897e9323dc0275655186397778c67b
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/mac_sdk.gni
M llvm/utils/gn/build/toolchain/target_flags.gni
Log Message:
-----------
[gn build] Bump macOS target to 12 and make it configurable (#107492)
Bumping the deployment target from macOS 10.10 to 12 enables chained
fixups and DWARF 4 debug information for the LLVM binaries and
libraries.
Like in Chromium, a GN arg (`mac_deployment_target`) is added to allow
overriding the default.
Commit: 861caf9b319ea44d48f1e077f07be3b5f102c6d5
https://github.com/llvm/llvm-project/commit/861caf9b319ea44d48f1e077f07be3b5f102c6d5
Author: hanbeom <kese111 at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
Log Message:
-----------
[SCCP] Remove LoadInst if it loaded from Constant GlobalVariable (#107245)
This patch removes the `LoadInst` when it loaded from Constant
GlobalVariable. This allows `canRemoveInstruction` function to be
removed.
Commit: 310b0a1cf39aaf25a8fb5c88afc3a47a5776cec2
https://github.com/llvm/llvm-project/commit/310b0a1cf39aaf25a8fb5c88afc3a47a5776cec2
Author: Matt Bolitho <matt.bolitho.software at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/test/tools/llvm-ml/run.asm
M llvm/tools/llvm-ml/Opts.td
Log Message:
-----------
[llvm-ml] Adds /quiet flag to llvm-ml (#107308)
In PR #106794, it was noted that `llvm-ml` does not support the `/quiet`
flag. The original reason it was added by Microsoft to `ml`/`ml64` was
to remove extraneous CMake build output (see [CMake GitLab
issue](https://gitlab.kitware.com/cmake/cmake/-/issues/23537)) much like
in the linked PR .
If the goal is for `llvm-ml` to be a drop-in replacement for
`ml`/`ml64`, then I think it makes sense to support the `/quiet` flag,
much like how `/nologo` is supported.
Commit: 77b388cfc60706ee1600bf0d50ecfc0ed035db3f
https://github.com/llvm/llvm-project/commit/77b388cfc60706ee1600bf0d50ecfc0ed035db3f
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lldb/docs/resources/test.rst
Log Message:
-----------
[lldb][Docs] Fix broken link to qemu testing page
Commit: c2e53b2d50e63d9802483334d6fd39ea7ef889ef
https://github.com/llvm/llvm-project/commit/c2e53b2d50e63d9802483334d6fd39ea7ef889ef
Author: Matthias Springer <me at m-sp.org>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/docs/DialectConversion.md
M mlir/include/mlir/Transforms/DialectConversion.h
Log Message:
-----------
[mlir][Transforms][NFC] Dialect conversion: Fix typo and improve docs (#107539)
Commit: 458c91d810a133850ebbf9313defd38fe5e61b50
https://github.com/llvm/llvm-project/commit/458c91d810a133850ebbf9313defd38fe5e61b50
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
R llvm/test/CodeGen/AArch64/partial-reduce-dot-product.ll
A llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64][NEON] Lower fixed-width add partial reductions to dot product (#107078)
This PR adds lowering for fixed-width <4 x i32> and <2 x i32> partial
reductions to a dot product when Neon and the dot product feature are
available.
The work is by Max Beck-Jones (@DevM-uk).
Commit: 725fab987d7b2133293eb4b82e8a0e9c6ba76053
https://github.com/llvm/llvm-project/commit/725fab987d7b2133293eb4b82e8a0e9c6ba76053
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
Log Message:
-----------
[lldb][NFC] Separated GDBRemoteCommunication::GetDebugserverPath() (#107388)
This is the prerequisite for #104238.
Commit: 691e3c64d08c32955c8f5f740d4ce0db00ee2307
https://github.com/llvm/llvm-project/commit/691e3c64d08c32955c8f5f740d4ce0db00ee2307
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lld/MachO/Symbols.h
Log Message:
-----------
[lld-macho] Fix `Defined` size increase with `-mms-bitfields` (#107545)
Under the Microsoft ABI, only those bit fields can be merged whose
underlying types have the same size.
d175616 (`[lld-macho][arm64] Enhance safe ICF with thunk-based
deduplication`) added an enum field (`identicalCodeFoldingKind`) next to
booleans in the `Defined` class, which increased the size under the MS
ABI. On MinGW targets, this triggered the `static_assert` which checks
the size of `Defined` (for MSVC targets, the check is disabled due to
another problem). Let's store it as a `uint8_t` to allow merging to take
place.
Fixes #107511
Commit: 66a03295de26c61a2178bb3a697d355592cb0eb5
https://github.com/llvm/llvm-project/commit/66a03295de26c61a2178bb3a697d355592cb0eb5
Author: Vitaly Goldshteyn <VitalyGoldstein at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M libc/src/string/memory_utils/op_x86.h
M libc/src/string/memory_utils/x86_64/inline_bcmp.h
Log Message:
-----------
[libc] Implement branchless head-tail comparison for bcmp (#107540)
Binary size changes:
| Bytes (cache lines) | before | after |
|---------------------|----------|---------|
| sse4 | 419 (7) | 288 (5) |
| avx | 430 (7) | 308 (5) |
| avx512f | 589 (10) | 390 (7) |
Benchmarks for different CPUs using
https://github.com/google/fleetbench.
- indus-cascadelake
```
name old speed new speed delta
BM_LIBC_Bcmp_Fleet_L1 1.96GB/s ± 1% 2.19GB/s ± 0% +11.49% (p=0.000 n=29+24)
BM_LIBC_Bcmp_Fleet_L2 1.90GB/s ± 1% 2.14GB/s ± 1% +12.68% (p=0.000 n=29+24)
BM_LIBC_Bcmp_Fleet_LLC 513MB/s ± 4% 531MB/s ± 4% +3.53% (p=0.000 n=24+24)
BM_LIBC_Bcmp_Fleet_Cold 452MB/s ± 3% 456MB/s ± 4% ~ (p=0.103 n=30+30)
BM_LIBC_Bcmp_0_L1 [Bcmp_0] 2.98GB/s ± 1% 3.15GB/s ± 1% +5.59% (p=0.000 n=29+30)
BM_LIBC_Bcmp_0_L2 [Bcmp_0] 2.86GB/s ± 1% 3.07GB/s ± 1% +7.21% (p=0.000 n=29+30)
BM_LIBC_Bcmp_0_LLC [Bcmp_0] 738MB/s ± 7% 751MB/s ± 3% +1.68% (p=0.000 n=24+25)
BM_LIBC_Bcmp_0_Cold [Bcmp_0] 643MB/s ± 3% 642MB/s ± 4% ~ (p=0.522 n=29+30)
BM_LIBC_Bcmp_1_L1 [Bcmp_1] 3.08GB/s ± 0% 3.25GB/s ± 0% +5.35% (p=0.000 n=28+30)
BM_LIBC_Bcmp_1_L2 [Bcmp_1] 2.97GB/s ± 1% 3.17GB/s ± 1% +6.65% (p=0.000 n=29+30)
BM_LIBC_Bcmp_1_LLC [Bcmp_1] 901MB/s ±59% 871MB/s ±36% ~ (p=0.676 n=29+27)
BM_LIBC_Bcmp_1_Cold [Bcmp_1] 686MB/s ± 4% 686MB/s ± 3% ~ (p=0.934 n=29+30)
BM_LIBC_Bcmp_2_L1 [Bcmp_2] 1.63GB/s ± 0% 1.80GB/s ± 1% +10.19% (p=0.000 n=29+30)
BM_LIBC_Bcmp_2_L2 [Bcmp_2] 1.57GB/s ± 1% 1.75GB/s ± 1% +11.46% (p=0.000 n=29+30)
BM_LIBC_Bcmp_2_LLC [Bcmp_2] 451MB/s ±61% 427MB/s ±28% ~ (p=0.469 n=29+25)
BM_LIBC_Bcmp_2_Cold [Bcmp_2] 353MB/s ± 4% 354MB/s ± 5% ~ (p=0.467 n=30+30)
BM_LIBC_Bcmp_3_L1 [Bcmp_3] 1.91GB/s ± 1% 2.10GB/s ± 1% +9.90% (p=0.000 n=29+29)
BM_LIBC_Bcmp_3_L2 [Bcmp_3] 1.84GB/s ± 1% 2.03GB/s ± 1% +10.63% (p=0.000 n=29+30)
BM_LIBC_Bcmp_3_LLC [Bcmp_3] 491MB/s ±24% 538MB/s ±24% +9.66% (p=0.000 n=24+27)
BM_LIBC_Bcmp_3_Cold [Bcmp_3] 417MB/s ± 4% 421MB/s ± 3% ~ (p=0.063 n=30+29)
BM_LIBC_Bcmp_4_L1 [Bcmp_4] 761MB/s ± 1% 867MB/s ± 1% +14.02% (p=0.000 n=28+30)
BM_LIBC_Bcmp_4_L2 [Bcmp_4] 748MB/s ± 1% 860MB/s ± 1% +15.04% (p=0.000 n=30+30)
BM_LIBC_Bcmp_4_LLC [Bcmp_4] 227MB/s ±29% 260MB/s ±64% +14.70% (p=0.000 n=26+27)
BM_LIBC_Bcmp_4_Cold [Bcmp_4] 187MB/s ± 3% 191MB/s ± 5% +2.26% (p=0.000 n=30+30)
BM_LIBC_Bcmp_5_L1 [Bcmp_5] 1.48GB/s ± 1% 1.71GB/s ± 1% +15.26% (p=0.000 n=29+30)
BM_LIBC_Bcmp_5_L2 [Bcmp_5] 1.42GB/s ± 1% 1.67GB/s ± 1% +17.68% (p=0.000 n=29+29)
BM_LIBC_Bcmp_5_LLC [Bcmp_5] 412MB/s ±34% 519MB/s ±80% +25.87% (p=0.000 n=27+30)
BM_LIBC_Bcmp_5_Cold [Bcmp_5] 336MB/s ± 4% 343MB/s ± 6% +2.05% (p=0.000 n=30+30)
BM_LIBC_Bcmp_6_L1 [Bcmp_6] 2.87GB/s ± 0% 3.24GB/s ± 1% +12.88% (p=0.000 n=26+30)
BM_LIBC_Bcmp_6_L2 [Bcmp_6] 2.78GB/s ± 1% 3.20GB/s ± 1% +15.15% (p=0.000 n=26+30)
BM_LIBC_Bcmp_6_LLC [Bcmp_6] 926MB/s ±43% 1227MB/s ±76% +32.53% (p=0.000 n=27+30)
BM_LIBC_Bcmp_6_Cold [Bcmp_6] 716MB/s ± 4% 737MB/s ± 6% +3.02% (p=0.000 n=28+29)
BM_LIBC_Bcmp_7_L1 [Bcmp_7] 1.54GB/s ± 1% 1.56GB/s ± 0% +1.40% (p=0.000 n=29+30)
BM_LIBC_Bcmp_7_L2 [Bcmp_7] 1.47GB/s ± 1% 1.52GB/s ± 1% +2.97% (p=0.000 n=27+30)
BM_LIBC_Bcmp_7_LLC [Bcmp_7] 351MB/s ±23% 436MB/s ±83% +24.04% (p=0.005 n=24+29)
BM_LIBC_Bcmp_7_Cold [Bcmp_7] 283MB/s ± 4% 282MB/s ± 4% ~ (p=0.644 n=30+30)
BM_LIBC_Bcmp_8_L1 [Bcmp_8] 824MB/s ± 1% 1048MB/s ± 1% +27.18% (p=0.000 n=29+30)
BM_LIBC_Bcmp_8_L2 [Bcmp_8] 808MB/s ± 1% 1027MB/s ± 1% +27.12% (p=0.000 n=29+29)
BM_LIBC_Bcmp_8_LLC [Bcmp_8] 317MB/s ±79% 332MB/s ±74% ~ (p=0.338 n=30+29)
BM_LIBC_Bcmp_8_Cold [Bcmp_8] 207MB/s ± 5% 212MB/s ± 5% +2.27% (p=0.000 n=30+30)
```
- indus-skylake
```
name old speed new speed delta
BM_LIBC_Bcmp_Fleet_L1 2.06GB/s ± 2% 2.25GB/s ± 3% +9.66% (p=0.000 n=27+24)
BM_LIBC_Bcmp_Fleet_L2 1.96GB/s ± 2% 2.17GB/s ± 2% +10.61% (p=0.000 n=30+24)
BM_LIBC_Bcmp_Fleet_LLC 1.18GB/s ± 6% 1.32GB/s ± 5% +12.27% (p=0.000 n=28+28)
BM_LIBC_Bcmp_Fleet_Cold 456MB/s ± 2% 466MB/s ± 2% +2.22% (p=0.000 n=28+28)
BM_LIBC_Bcmp_0_L1 [Bcmp_0] 3.08GB/s ± 2% 3.20GB/s ± 1% +3.72% (p=0.000 n=28+22)
BM_LIBC_Bcmp_0_L2 [Bcmp_0] 2.92GB/s ± 1% 3.05GB/s ± 2% +4.49% (p=0.000 n=23+23)
BM_LIBC_Bcmp_0_LLC [Bcmp_0] 1.83GB/s ± 8% 1.94GB/s ± 4% +6.24% (p=0.000 n=25+27)
BM_LIBC_Bcmp_0_Cold [Bcmp_0] 654MB/s ± 2% 659MB/s ± 2% +0.76% (p=0.012 n=30+29)
BM_LIBC_Bcmp_1_L1 [Bcmp_1] 3.19GB/s ± 2% 3.34GB/s ± 2% +4.41% (p=0.000 n=26+23)
BM_LIBC_Bcmp_1_L2 [Bcmp_1] 3.05GB/s ± 2% 3.21GB/s ± 2% +5.32% (p=0.000 n=28+25)
BM_LIBC_Bcmp_1_LLC [Bcmp_1] 1.95GB/s ± 4% 2.03GB/s ±10% +3.61% (p=0.000 n=27+30)
BM_LIBC_Bcmp_1_Cold [Bcmp_1] 700MB/s ± 2% 702MB/s ± 2% ~ (p=0.150 n=30+30)
BM_LIBC_Bcmp_2_L1 [Bcmp_2] 1.69GB/s ± 2% 1.85GB/s ± 1% +9.31% (p=0.000 n=30+26)
BM_LIBC_Bcmp_2_L2 [Bcmp_2] 1.60GB/s ± 2% 1.78GB/s ± 2% +10.90% (p=0.000 n=26+27)
BM_LIBC_Bcmp_2_LLC [Bcmp_2] 1.01GB/s ± 5% 1.12GB/s ± 5% +11.40% (p=0.000 n=27+28)
BM_LIBC_Bcmp_2_Cold [Bcmp_2] 355MB/s ± 3% 360MB/s ± 3% +1.46% (p=0.000 n=30+30)
BM_LIBC_Bcmp_3_L1 [Bcmp_3] 1.98GB/s ± 2% 2.15GB/s ± 2% +8.89% (p=0.000 n=29+27)
BM_LIBC_Bcmp_3_L2 [Bcmp_3] 1.87GB/s ± 3% 2.05GB/s ± 2% +10.06% (p=0.000 n=30+26)
BM_LIBC_Bcmp_3_LLC [Bcmp_3] 1.19GB/s ± 4% 1.31GB/s ± 6% +9.82% (p=0.000 n=27+29)
BM_LIBC_Bcmp_3_Cold [Bcmp_3] 424MB/s ± 3% 431MB/s ± 3% +1.58% (p=0.000 n=28+30)
BM_LIBC_Bcmp_4_L1 [Bcmp_4] 849MB/s ± 2% 949MB/s ± 2% +11.84% (p=0.000 n=27+28)
BM_LIBC_Bcmp_4_L2 [Bcmp_4] 815MB/s ± 3% 913MB/s ± 3% +12.06% (p=0.000 n=29+30)
BM_LIBC_Bcmp_4_LLC [Bcmp_4] 512MB/s ± 9% 571MB/s ± 7% +11.40% (p=0.000 n=30+30)
BM_LIBC_Bcmp_4_Cold [Bcmp_4] 187MB/s ± 3% 192MB/s ± 2% +2.56% (p=0.000 n=30+28)
BM_LIBC_Bcmp_5_L1 [Bcmp_5] 1.55GB/s ± 2% 1.77GB/s ± 3% +13.93% (p=0.000 n=30+28)
BM_LIBC_Bcmp_5_L2 [Bcmp_5] 1.47GB/s ± 2% 1.70GB/s ± 2% +15.96% (p=0.000 n=27+26)
BM_LIBC_Bcmp_5_LLC [Bcmp_5] 939MB/s ± 5% 1084MB/s ± 4% +15.36% (p=0.000 n=28+27)
BM_LIBC_Bcmp_5_Cold [Bcmp_5] 340MB/s ± 2% 347MB/s ± 3% +1.93% (p=0.000 n=30+30)
BM_LIBC_Bcmp_6_L1 [Bcmp_6] 3.06GB/s ± 3% 3.40GB/s ± 2% +11.13% (p=0.000 n=30+28)
BM_LIBC_Bcmp_6_L2 [Bcmp_6] 2.89GB/s ± 3% 3.24GB/s ± 2% +12.20% (p=0.000 n=29+26)
BM_LIBC_Bcmp_6_LLC [Bcmp_6] 1.93GB/s ± 4% 2.09GB/s ±11% +8.16% (p=0.000 n=26+30)
BM_LIBC_Bcmp_6_Cold [Bcmp_6] 746MB/s ± 2% 762MB/s ± 2% +2.11% (p=0.000 n=30+28)
BM_LIBC_Bcmp_7_L1 [Bcmp_7] 1.59GB/s ± 2% 1.62GB/s ± 2% +1.72% (p=0.000 n=25+27)
BM_LIBC_Bcmp_7_L2 [Bcmp_7] 1.49GB/s ± 2% 1.53GB/s ± 2% +2.62% (p=0.000 n=27+29)
BM_LIBC_Bcmp_7_LLC [Bcmp_7] 852MB/s ±10% 909MB/s ± 6% +6.71% (p=0.000 n=30+29)
BM_LIBC_Bcmp_7_Cold [Bcmp_7] 283MB/s ± 3% 283MB/s ± 2% ~ (p=0.617 n=30+27)
BM_LIBC_Bcmp_8_L1 [Bcmp_8] 891MB/s ± 2% 1083MB/s ± 2% +21.64% (p=0.000 n=27+24)
BM_LIBC_Bcmp_8_L2 [Bcmp_8] 855MB/s ± 2% 1045MB/s ± 1% +22.31% (p=0.000 n=25+23)
BM_LIBC_Bcmp_8_LLC [Bcmp_8] 568MB/s ± 7% 659MB/s ± 8% +16.04% (p=0.000 n=29+30)
BM_LIBC_Bcmp_8_Cold [Bcmp_8] 207MB/s ± 2% 212MB/s ± 2% +2.31% (p=0.000 n=30+27)
```
- arcadia-rome
```
name old speed new speed delta
BM_LIBC_Bcmp_Fleet_L1 2.16GB/s ± 2% 2.27GB/s ± 2% +5.13% (p=0.000 n=26+30)
BM_LIBC_Bcmp_Fleet_L2 2.15GB/s ± 2% 2.25GB/s ± 2% +4.64% (p=0.000 n=27+30)
BM_LIBC_Bcmp_Fleet_LLC 1.73GB/s ± 3% 1.81GB/s ± 3% +4.66% (p=0.000 n=25+28)
BM_LIBC_Bcmp_Fleet_Cold 494MB/s ± 1% 496MB/s ± 2% +0.45% (p=0.023 n=22+24)
BM_LIBC_Bcmp_0_L1 [Bcmp_0] 3.30GB/s ± 1% 3.24GB/s ± 2% -1.70% (p=0.000 n=27+30)
BM_LIBC_Bcmp_0_L2 [Bcmp_0] 3.23GB/s ± 2% 3.19GB/s ± 2% -1.28% (p=0.000 n=28+28)
BM_LIBC_Bcmp_0_LLC [Bcmp_0] 2.59GB/s ± 3% 2.58GB/s ± 2% -0.65% (p=0.010 n=26+26)
BM_LIBC_Bcmp_0_Cold [Bcmp_0] 720MB/s ± 1% 707MB/s ± 3% -1.75% (p=0.000 n=22+25)
BM_LIBC_Bcmp_1_L1 [Bcmp_1] 3.37GB/s ± 1% 3.36GB/s ± 2% ~ (p=0.102 n=28+29)
BM_LIBC_Bcmp_1_L2 [Bcmp_1] 3.32GB/s ± 2% 3.30GB/s ± 2% -0.51% (p=0.038 n=28+29)
BM_LIBC_Bcmp_1_LLC [Bcmp_1] 2.67GB/s ± 4% 2.70GB/s ± 4% +0.96% (p=0.009 n=28+27)
BM_LIBC_Bcmp_1_Cold [Bcmp_1] 755MB/s ± 1% 751MB/s ± 2% -0.57% (p=0.000 n=22+25)
BM_LIBC_Bcmp_2_L1 [Bcmp_2] 1.79GB/s ± 1% 1.86GB/s ± 2% +3.92% (p=0.000 n=27+29)
BM_LIBC_Bcmp_2_L2 [Bcmp_2] 1.77GB/s ± 2% 1.82GB/s ± 2% +2.99% (p=0.000 n=28+29)
BM_LIBC_Bcmp_2_LLC [Bcmp_2] 1.41GB/s ± 4% 1.47GB/s ± 3% +3.97% (p=0.000 n=28+28)
BM_LIBC_Bcmp_2_Cold [Bcmp_2] 386MB/s ± 1% 389MB/s ± 1% +0.60% (p=0.000 n=21+23)
BM_LIBC_Bcmp_3_L1 [Bcmp_3] 2.07GB/s ± 2% 2.17GB/s ± 2% +4.87% (p=0.000 n=29+30)
BM_LIBC_Bcmp_3_L2 [Bcmp_3] 2.07GB/s ± 2% 2.13GB/s ± 2% +3.02% (p=0.000 n=28+30)
BM_LIBC_Bcmp_3_LLC [Bcmp_3] 1.66GB/s ± 2% 1.73GB/s ± 2% +4.08% (p=0.000 n=29+26)
BM_LIBC_Bcmp_3_Cold [Bcmp_3] 466MB/s ± 2% 469MB/s ± 3% +0.66% (p=0.001 n=22+25)
BM_LIBC_Bcmp_4_L1 [Bcmp_4] 861MB/s ± 1% 964MB/s ± 2% +11.98% (p=0.000 n=29+29)
BM_LIBC_Bcmp_4_L2 [Bcmp_4] 853MB/s ± 2% 935MB/s ± 2% +9.54% (p=0.000 n=28+29)
BM_LIBC_Bcmp_4_LLC [Bcmp_4] 707MB/s ± 3% 743MB/s ± 4% +5.08% (p=0.000 n=29+29)
BM_LIBC_Bcmp_4_Cold [Bcmp_4] 199MB/s ± 3% 199MB/s ± 2% ~ (p=0.107 n=29+25)
BM_LIBC_Bcmp_5_L1 [Bcmp_5] 1.65GB/s ± 1% 1.75GB/s ± 2% +6.15% (p=0.000 n=29+29)
BM_LIBC_Bcmp_5_L2 [Bcmp_5] 1.64GB/s ± 3% 1.73GB/s ± 2% +5.37% (p=0.000 n=29+29)
BM_LIBC_Bcmp_5_LLC [Bcmp_5] 1.32GB/s ± 2% 1.40GB/s ± 2% +6.21% (p=0.000 n=28+27)
BM_LIBC_Bcmp_5_Cold [Bcmp_5] 370MB/s ± 3% 371MB/s ± 2% +0.16% (p=0.008 n=29+25)
BM_LIBC_Bcmp_6_L1 [Bcmp_6] 3.25GB/s ± 2% 3.47GB/s ± 2% +6.74% (p=0.000 n=28+29)
BM_LIBC_Bcmp_6_L2 [Bcmp_6] 3.26GB/s ± 1% 3.44GB/s ± 1% +5.43% (p=0.000 n=28+29)
BM_LIBC_Bcmp_6_LLC [Bcmp_6] 2.66GB/s ± 2% 2.79GB/s ± 3% +4.90% (p=0.000 n=27+29)
BM_LIBC_Bcmp_6_Cold [Bcmp_6] 812MB/s ± 3% 799MB/s ± 2% -1.57% (p=0.000 n=29+25)
BM_LIBC_Bcmp_7_L1 [Bcmp_7] 1.71GB/s ± 2% 1.66GB/s ± 2% -3.14% (p=0.000 n=29+29)
BM_LIBC_Bcmp_7_L2 [Bcmp_7] 1.63GB/s ± 2% 1.59GB/s ± 2% -2.50% (p=0.000 n=29+28)
BM_LIBC_Bcmp_7_LLC [Bcmp_7] 1.25GB/s ± 4% 1.25GB/s ± 2% ~ (p=0.530 n=28+26)
BM_LIBC_Bcmp_7_Cold [Bcmp_7] 311MB/s ± 3% 308MB/s ± 1% ~ (p=0.127 n=29+24)
BM_LIBC_Bcmp_8_L1 [Bcmp_8] 869MB/s ± 2% 1098MB/s ± 2% +26.28% (p=0.000 n=27+29)
BM_LIBC_Bcmp_8_L2 [Bcmp_8] 873MB/s ± 2% 1075MB/s ± 1% +23.06% (p=0.000 n=27+29)
BM_LIBC_Bcmp_8_LLC [Bcmp_8] 743MB/s ± 4% 859MB/s ± 4% +15.58% (p=0.000 n=27+27)
BM_LIBC_Bcmp_8_Cold [Bcmp_8] 221MB/s ± 4% 221MB/s ± 3% +0.14% (p=0.034 n=29+25)
```
- ixion-haswell
```
name old speed new speed delta
BM_LIBC_Bcmp_Fleet_L1 2.27GB/s ± 5% 2.41GB/s ± 6% +6.10% (p=0.000 n=29+28)
BM_LIBC_Bcmp_Fleet_L2 2.14GB/s ± 6% 2.33GB/s ± 5% +9.21% (p=0.000 n=29+30)
BM_LIBC_Bcmp_Fleet_LLC 1.30GB/s ± 9% 1.43GB/s ± 8% +9.85% (p=0.000 n=30+30)
BM_LIBC_Bcmp_Fleet_Cold 475MB/s ± 6% 475MB/s ± 5% ~ (p=0.839 n=30+29)
BM_LIBC_Bcmp_0_L1 [Bcmp_0] 3.38GB/s ± 7% 3.46GB/s ± 6% +2.35% (p=0.009 n=30+29)
BM_LIBC_Bcmp_0_L2 [Bcmp_0] 3.20GB/s ± 5% 3.32GB/s ± 6% +3.52% (p=0.000 n=28+30)
BM_LIBC_Bcmp_0_LLC [Bcmp_0] 1.88GB/s ± 9% 2.00GB/s ± 6% +6.63% (p=0.000 n=30+28)
BM_LIBC_Bcmp_0_Cold [Bcmp_0] 664MB/s ± 6% 655MB/s ± 6% -1.32% (p=0.025 n=30+30)
BM_LIBC_Bcmp_1_L1 [Bcmp_1] 3.50GB/s ± 8% 3.61GB/s ±10% +3.09% (p=0.001 n=29+30)
BM_LIBC_Bcmp_1_L2 [Bcmp_1] 3.32GB/s ± 7% 3.48GB/s ± 8% +4.89% (p=0.000 n=29+30)
BM_LIBC_Bcmp_1_LLC [Bcmp_1] 2.02GB/s ± 7% 2.14GB/s ± 9% +5.82% (p=0.000 n=28+29)
BM_LIBC_Bcmp_1_Cold [Bcmp_1] 716MB/s ± 6% 709MB/s ± 5% -0.97% (p=0.040 n=30+28)
BM_LIBC_Bcmp_2_L1 [Bcmp_2] 1.83GB/s ± 7% 1.97GB/s ± 8% +7.90% (p=0.000 n=30+30)
BM_LIBC_Bcmp_2_L2 [Bcmp_2] 1.74GB/s ± 6% 1.92GB/s ± 6% +10.29% (p=0.000 n=30+29)
BM_LIBC_Bcmp_2_LLC [Bcmp_2] 1.05GB/s ± 9% 1.15GB/s ± 9% +9.73% (p=0.000 n=30+30)
BM_LIBC_Bcmp_2_Cold [Bcmp_2] 379MB/s ± 6% 372MB/s ± 6% -1.74% (p=0.012 n=30+30)
BM_LIBC_Bcmp_3_L1 [Bcmp_3] 2.17GB/s ± 5% 2.29GB/s ± 6% +5.61% (p=0.000 n=29+30)
BM_LIBC_Bcmp_3_L2 [Bcmp_3] 2.02GB/s ± 6% 2.20GB/s ± 6% +8.75% (p=0.000 n=29+30)
BM_LIBC_Bcmp_3_LLC [Bcmp_3] 1.22GB/s ± 8% 1.34GB/s ± 9% +9.19% (p=0.000 n=30+30)
BM_LIBC_Bcmp_3_Cold [Bcmp_3] 447MB/s ± 3% 441MB/s ± 7% -1.40% (p=0.033 n=30+30)
BM_LIBC_Bcmp_4_L1 [Bcmp_4] 902MB/s ± 6% 995MB/s ±10% +10.37% (p=0.000 n=30+30)
BM_LIBC_Bcmp_4_L2 [Bcmp_4] 863MB/s ± 5% 945MB/s ±11% +9.50% (p=0.000 n=29+30)
BM_LIBC_Bcmp_4_LLC [Bcmp_4] 528MB/s ±11% 559MB/s ±12% +5.75% (p=0.000 n=30+30)
BM_LIBC_Bcmp_4_Cold [Bcmp_4] 183MB/s ± 4% 181MB/s ± 7% ~ (p=0.088 n=28+30)
BM_LIBC_Bcmp_5_L1 [Bcmp_5] 1.70GB/s ± 6% 1.87GB/s ± 8% +10.14% (p=0.000 n=29+29)
BM_LIBC_Bcmp_5_L2 [Bcmp_5] 1.60GB/s ± 5% 1.80GB/s ± 9% +12.61% (p=0.000 n=29+30)
BM_LIBC_Bcmp_5_LLC [Bcmp_5] 994MB/s ±13% 1094MB/s ± 8% +10.10% (p=0.000 n=29+30)
BM_LIBC_Bcmp_5_Cold [Bcmp_5] 362MB/s ± 6% 358MB/s ± 7% ~ (p=0.123 n=30+30)
BM_LIBC_Bcmp_6_L1 [Bcmp_6] 3.31GB/s ± 5% 3.67GB/s ± 6% +10.90% (p=0.000 n=28+30)
BM_LIBC_Bcmp_6_L2 [Bcmp_6] 3.11GB/s ± 5% 3.53GB/s ± 5% +13.59% (p=0.000 n=30+30)
BM_LIBC_Bcmp_6_LLC [Bcmp_6] 1.98GB/s ± 9% 2.18GB/s ± 8% +10.34% (p=0.000 n=30+30)
BM_LIBC_Bcmp_6_Cold [Bcmp_6] 754MB/s ± 5% 752MB/s ± 5% ~ (p=0.592 n=30+30)
BM_LIBC_Bcmp_7_L1 [Bcmp_7] 1.72GB/s ± 5% 1.72GB/s ± 6% ~ (p=0.549 n=29+29)
BM_LIBC_Bcmp_7_L2 [Bcmp_7] 1.61GB/s ± 7% 1.63GB/s ± 8% ~ (p=0.191 n=30+29)
BM_LIBC_Bcmp_7_LLC [Bcmp_7] 913MB/s ± 8% 905MB/s ± 9% ~ (p=0.423 n=30+30)
BM_LIBC_Bcmp_7_Cold [Bcmp_7] 304MB/s ± 6% 287MB/s ± 4% -5.57% (p=0.000 n=30+30)
BM_LIBC_Bcmp_8_L1 [Bcmp_8] 961MB/s ± 5% 1124MB/s ± 6% +16.94% (p=0.000 n=30+30)
BM_LIBC_Bcmp_8_L2 [Bcmp_8] 915MB/s ± 8% 1100MB/s ± 7% +20.16% (p=0.000 n=30+30)
BM_LIBC_Bcmp_8_LLC [Bcmp_8] 593MB/s ± 8% 669MB/s ± 8% +12.92% (p=0.000 n=30+30)
BM_LIBC_Bcmp_8_Cold [Bcmp_8] 220MB/s ± 4% 220MB/s ± 6% ~ (p=0.572 n=30+30)
```
Co-authored-by: goldvitaly at google.com <%username%@google.com>
Commit: 78e1e6ace6c99ac3c96216a40836a1ac98d4f000
https://github.com/llvm/llvm-project/commit/78e1e6ace6c99ac3c96216a40836a1ac98d4f000
Author: ErikHogeman <erik.hogeman at arm.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
A llvm/test/Transforms/LoopVectorize/vector-to-scalar-cast.ll
Log Message:
-----------
[LV] Check for vector-to-scalar casts in legalizer (#106244)
The code makes assumptions later on the operations and their inputs
being scalar in the loops that are processed, so we should make sure
this is the case in the legalizer.
Commit: 12c4d26c1d6f03e7628c31c8d12fdf426575bb2c
https://github.com/llvm/llvm-project/commit/12c4d26c1d6f03e7628c31c8d12fdf426575bb2c
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
Log Message:
-----------
[Flang][OpenMP] NFC: DataSharingProcessor cleanup (#107391)
This patch removes unused and undefined method declarations from
`DataSharingProcessor`, as well as the unused `hasLastPrivateOp` class
member. The `insPt` class member is replaced by a local `InsertionGuard`
in the only place it is set and used.
Commit: c5de6611ce10b8ecf573f601b5f12de60424897d
https://github.com/llvm/llvm-project/commit/c5de6611ce10b8ecf573f601b5f12de60424897d
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
Log Message:
-----------
[Flang][OpenMP] NFC: Flang OpenMP passes cleanup (#107386)
For consistency, this patch renames the `FunctionFiltering` pass to
`FunctionFilteringPass`. Also, OpenMP pass-related `#define`s are
removed from flang/Optimizer/Transforms/Passes.h, since `#define`s don't
have an effect there after moving related passes to
flang/Optimizer/OpenMP/Passes.td.
Commit: e40c5b42fe8f489ea4bac4694ef58f09bd95263b
https://github.com/llvm/llvm-project/commit/e40c5b42fe8f489ea4bac4694ef58f09bd95263b
Author: Lily Brown <lbrown at modular.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/lib/Tools/lsp-server-support/Transport.cpp
Log Message:
-----------
[lsp] Fix format string in Reply (#107480)
PR #105745 requires that `formatv` calls have the correct number of
arguments. This call to `Logger::info` was incorrect.
Commit: d4e320e6f4dd78929cec44b342b6035a6bbd6323
https://github.com/llvm/llvm-project/commit/d4e320e6f4dd78929cec44b342b6035a6bbd6323
Author: Christian Sigg <csigg at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
Log Message:
-----------
[lldb][NFC] Fix -Wparentheses warning.
Fix `using the result of an assignment as a condition without parentheses` warning.
Commit: 50be4f17a0ff951f8a8e123e66c7024b067211c6
https://github.com/llvm/llvm-project/commit/50be4f17a0ff951f8a8e123e66c7024b067211c6
Author: Chaitanya <Krishna.Sankisa at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
Log Message:
-----------
[AMDGPU] Skip lowerNonKernelLDSAccesses if function is declaration. (#106975)
This PR skips lowering non-kernel LDS i.e lowerNonKernelLDSAccesses,
when function is a declaration or there are no lds globals to process.
Commit: a918fa117acfbb20d29039cb8bddab159a8173dc
https://github.com/llvm/llvm-project/commit/a918fa117acfbb20d29039cb8bddab159a8173dc
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
Log Message:
-----------
[clang] Emit -Wdangling diagnoses for cases where a gsl-pointer is construct from a gsl-owner object in a container. (#104556)
The warning is not emitted for the case `string_view c =
std::vector<std::string>({""}).at(0);` because we bail out during the
visit of the LHS at [this
point](https://github.com/llvm/llvm-project/blob/5d2c324fea2d7cf86ec50e4bb6b680acf89b2ed5/clang/lib/Sema/CheckExprLifetime.cpp#L341-L343)
in the code.
This bailout was introduced in [this
commit](https://github.com/llvm/llvm-project/commit/bcd0798c47ca865f95226859893016a17402441e)
to address a false positive with
`vector<vector::iterator>({""}).at(0);`. This PR refines that fix by
ensuring that, for initialization involving a gsl-pointer, we only
consider constructor calls that take the gsl-owner object.
Fixes #100384.
Commit: b11a70392c6ef3c481421f9f0a6651030333ebdc
https://github.com/llvm/llvm-project/commit/b11a70392c6ef3c481421f9f0a6651030333ebdc
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
Log Message:
-----------
[lldb] Fixed a typo in #107388
Commit: 8af0860529d75b61b66cb96ac05f503b0e2e845c
https://github.com/llvm/llvm-project/commit/8af0860529d75b61b66cb96ac05f503b0e2e845c
Author: Johannes Reifferscheid <jreiffers at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/lib/IR/AffineExpr.cpp
M mlir/unittests/IR/AffineExprTest.cpp
Log Message:
-----------
AffineExpr: Fix result of d0 + (d0 // -c) * c. (#107530)
Currently, this is rewritten to d0 mod -c. However, we do not support
modulo with a negative RHS in our lowering passes, so this triggers
undefined behavior.
It would be better to not have these ad hoc simplifications at all, but
I guess that ship has sailed.
Commit: 704da919bafa5b088223f9d77424f24ae754539e
https://github.com/llvm/llvm-project/commit/704da919bafa5b088223f9d77424f24ae754539e
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/test/DebugInfo/Generic/debug-ranges-duplication.ll
Log Message:
-----------
[DebugInfo][AIX] XFAIL debug-ranges-duplication.ll (#107525)
The test fails with `Assertion failed: Section && "Cannot switch to a
null section!"` because of unsupported DWARF 5 section.
Commit: cdd2c0693b6dd75816f64960a479aacbe4e34549
https://github.com/llvm/llvm-project/commit/cdd2c0693b6dd75816f64960a479aacbe4e34549
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UnconventionalAssignOperatorCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/unconventional-assign-operator-cxx23.cpp
Log Message:
-----------
[clang-tidy] fix misc-unconventional-assign-operator false positive for deducing this (#107409)
Fixes: #107119
When meeting c++23 deducing this, we should skip the first parameter
Commit: 222d3b031f6bf39873550a34152b9d05b9b6578a
https://github.com/llvm/llvm-project/commit/222d3b031f6bf39873550a34152b9d05b9b6578a
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/test/Analysis/TypeBasedAliasAnalysis/aggregates.ll
Log Message:
-----------
[TBAA] Fix the case where a subobject gets accessed at a non-zero offset. (#101485)
Commit: c9bdc2564dabd1601ac0d714ba3f7057f55f6329
https://github.com/llvm/llvm-project/commit/c9bdc2564dabd1601ac0d714ba3f7057f55f6329
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
Log Message:
-----------
[X86][MC] Cont. update for AVX10.2-BF16 (#107529)
Not an expert in this code, but looks like it fixed the crash for us. Picking it up.
Commit: 775f7f1c99562d0315be26aed7828e713bd3fc22
https://github.com/llvm/llvm-project/commit/775f7f1c99562d0315be26aed7828e713bd3fc22
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M flang/lib/Optimizer/Builder/Runtime/Numeric.cpp
M flang/test/Lower/Intrinsics/spacing.f90
Log Message:
-----------
[flang] lower SPACING f16/bf16 to new runtime APIs (#107541)
Use APIs added in https://github.com/llvm/llvm-project/pull/106575
This is needed to fix HDF5 builds that are blocked by SPACING TODOs for
REAL(2) and currently needs manual hacks.
Commit: 5d2b3378758b42391e90b1adf936537a66b038b6
https://github.com/llvm/llvm-project/commit/5d2b3378758b42391e90b1adf936537a66b038b6
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerPlatform.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M lldb/unittests/tools/lldb-server/tests/LLGSTest.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.h
Log Message:
-----------
[lldb][NFC] Used shared_fd_t (#107553)
Replaced `int connection_fd = -1` with `shared_fd_t connection_fd =
SharedSocket::kInvalidFD`.
This is prerequisite for #104238.
Commit: 1f70fcefa981e6e2b7e60678545766426fbefd96
https://github.com/llvm/llvm-project/commit/1f70fcefa981e6e2b7e60678545766426fbefd96
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/arm_fp16.td
A clang/include/clang/Basic/arm_immcheck_incl.td
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/arm_neon_incl.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/Sema/SemaARM.h
M clang/lib/Sema/SemaARM.cpp
M clang/test/CodeGen/aarch64-neon-luti.c
R clang/test/CodeGen/arm-neon-range-checks.c
R clang/test/Sema/aarch64-neon-bf16-ranges.c
R clang/test/Sema/aarch64-neon-fp16-ranges.c
A clang/test/Sema/aarch64-neon-immediate-ranges/bfloat16.c
A clang/test/Sema/aarch64-neon-immediate-ranges/conversions.c
A clang/test/Sema/aarch64-neon-immediate-ranges/copy-vector-lane.c
A clang/test/Sema/aarch64-neon-immediate-ranges/dotprod.c
A clang/test/Sema/aarch64-neon-immediate-ranges/extract-elt-from-vector.c
A clang/test/Sema/aarch64-neon-immediate-ranges/extract-vector-from-vectors.c
A clang/test/Sema/aarch64-neon-immediate-ranges/fp16-scalar.c
A clang/test/Sema/aarch64-neon-immediate-ranges/fp16-v84.c
A clang/test/Sema/aarch64-neon-immediate-ranges/fp16-vector.c
A clang/test/Sema/aarch64-neon-immediate-ranges/fused-multiply-accumulate.c
A clang/test/Sema/aarch64-neon-immediate-ranges/luti.c
A clang/test/Sema/aarch64-neon-immediate-ranges/matrix-multiplication.c
A clang/test/Sema/aarch64-neon-immediate-ranges/multiply-extended.c
A clang/test/Sema/aarch64-neon-immediate-ranges/saturating-multiply-accumulate.c
A clang/test/Sema/aarch64-neon-immediate-ranges/saturating-multiply-by-scalar-and-widen.c
A clang/test/Sema/aarch64-neon-immediate-ranges/set-lanes-to-value.c
A clang/test/Sema/aarch64-neon-immediate-ranges/set-vector-lane.c
A clang/test/Sema/aarch64-neon-immediate-ranges/sqrdmlah-ranges.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vcmla.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-load.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-multiply-accumulate-by-scalar.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-multiply-by-scalar-and-widen.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-multiply-by-scalar.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-multiply-subtract-by-scalar.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-left.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-right.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-store.c
R clang/test/Sema/aarch64-neon-ranges.c
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M llvm/docs/CommandGuide/tblgen.rst
A llvm/include/llvm/TableGen/AArch64ImmCheck.h
Log Message:
-----------
[Clang][AArch64] Add customisable immediate range checking to NEON (#100278)
This patch moves NEON immediate argument specification and checking to
the system currently shared by both SVE and SME.
In its current form, the TableGen definition of a NEON intrinsic cannot
control how its immediate arguments are range-checked, this information
must be inferred from the name of the intrinsic by NeonEmitter, which
also assumes that any NEON instruction will only ever receive a single
immediate argument. For SVE/SME instrinsics, this information is more
conveniently supplied in the TableGen definition.
As a result, for each immediate argument, NEON instructions must define
- The index of the immediate argument to be checked
- The type of immediate range check to be performed,
(e.g., ImmCheckShiftRight)
- The index of the argument whose type defines the context
of this immediate check (base type, vector size).
- **Difference from SVE/SME** If this definition generates a polymorphic
NEON builtin, the base type defined by this argument is overwritten by
that of the type code supplied to the overloaded builtin call. This
third argument is omitted in some cases due to this.
Here is an example for
[`vfma_laneq`](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiessimdisa=[Neon]&q=vfma_laneq)
- The immediate is supplied in argument 3
- The immediate is used as an index into the lanes of argument 2
- So we must perform an immediate check on argument 3, based on the type
information of argument 2.
- `ImmCheck<3, ImmCheckLaneIndex, 2>`
During this work, we discovered that the existing immediate
range-checking system was largely untested, which made it difficult to
make reliable progress. Missing tests have been added to verify this
implementation against all intrinsics which take constrained immediate
arguments. All test immediate range checking tests for NEON intrinsics
are moved to a dedicated directory
`clang/test/Sema/aarch64-neon-immediate-ranges/`.
Commit: 6ec889e53f1ae048cc9aee79c91118fc8bbc6974
https://github.com/llvm/llvm-project/commit/6ec889e53f1ae048cc9aee79c91118fc8bbc6974
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
M llvm/test/CodeGen/X86/abds-neg.ll
M llvm/test/CodeGen/X86/abdu-neg.ll
Log Message:
-----------
[DAG] Add support for neg(abd(x,y)) patterns.
Currently limited to cases which have legal/custom ABDS/ABDU handling - I'll extend this for all targets in future (similar to how we support neg(abs(x))) once I've addressed some outstanding regressions on aarch64/riscv.
Helps avoid a lot of extra cmov instructions on x86 in particular, and allows us to more easily improve the codegen in future commits.
Commit: 67f9183c113a340c58bdb9d5d3bfb850b8db4e90
https://github.com/llvm/llvm-project/commit/67f9183c113a340c58bdb9d5d3bfb850b8db4e90
Author: yronglin <yronglin777 at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/test/AST/ByteCode/constexpr-vectors.cpp
Log Message:
-----------
[clang][bytecode] Implement comparsion operators for vector type (#107258)
Implement ==, !=, <, <=, >, >= comparsion operators for vector type.
---------
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: 5cf3677a7bcdf5a9e603c054bd40c1282db984a9
https://github.com/llvm/llvm-project/commit/5cf3677a7bcdf5a9e603c054bd40c1282db984a9
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/test/Driver/Ofast.c
Log Message:
-----------
[clang] Pass -c to clang in test/Driver/Ofast.c
Without this, `-###` prints the linker invocation as well, which
can lead to `-Wno-msvc-not-found` warnings on Windows bots that
don't have MSVC on path, causing the test to fail.
Since the test isn't trying to test linker-related things, just
pass `-c`. See discussion on #98736.
Commit: 9d12d9316fa91f9832d13f6a1f756c612360d000
https://github.com/llvm/llvm-project/commit/9d12d9316fa91f9832d13f6a1f756c612360d000
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
Log Message:
-----------
[gn] port 1f70fcefa981e6e2b
Commit: fb6c10da1f6cb4eb9556548d51dafe97d953ba58
https://github.com/llvm/llvm-project/commit/fb6c10da1f6cb4eb9556548d51dafe97d953ba58
Author: Nabeel Omer <nabeel.omer at sony.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/test/Driver/ps4-ps5-toolchain.c
M llvm/docs/Extensions.rst
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCSectionELF.cpp
M llvm/lib/Object/ELF.cpp
A llvm/test/CodeGen/X86/jump-table-size-section.ll
Log Message:
-----------
[MC] Emit a jump table size section (#101962)
This patch will make LLVM emit a new section .llvm_jump_table_sizes
containing tuples of (jump table address, entry count) in object files.
This section is useful for tools that need to statically reconstruct the
control flow of executables.
At the moment this is only enabled by default for the PS5 target.
Commit: c782d54f0fb7a0ea56d4e1d5b49d176fed57cb6f
https://github.com/llvm/llvm-project/commit/c782d54f0fb7a0ea56d4e1d5b49d176fed57cb6f
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] port 1f70fcefa981e6e2b
Commit: c64dac2e6c39f0f7f1c676857e7d34c764b4d632
https://github.com/llvm/llvm-project/commit/c64dac2e6c39f0f7f1c676857e7d34c764b4d632
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/include/clang/Basic/TargetBuiltins.h
Log Message:
-----------
[clang] Fix noisy -Wcovered-switch-default warning after 1f70fcefa9 / #100278
Commit: a67b6e163528ea547ccbcd4850803f062df66d2e
https://github.com/llvm/llvm-project/commit/a67b6e163528ea547ccbcd4850803f062df66d2e
Author: Akash Banerjee <Akash.Banerjee at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M offload/test/offloading/fortran/target-map-dynamic.f90
Log Message:
-----------
Fix typo in test.
Commit: 71a0eb33178c79eafef2cf55bb8c87ea89e6491e
https://github.com/llvm/llvm-project/commit/71a0eb33178c79eafef2cf55bb8c87ea89e6491e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/pull-conditional-binop-through-shift.ll
M llvm/test/CodeGen/X86/select.ll
Log Message:
-----------
[X86] LowerSelect - generalize "select icmp(x,0), lhs, rhs" folding patterns. (#107272)
We have many cases where the condition is a "(and x, 1)" pattern (e.g. from a bool argument or some other simplified bitlogic), and we have a large number of existing generic/x86 patterns that make use of this (and trying to convert to a SETCC node can cause infinite loops).
Use the LowerSELECTWithCmpZero helper, simulating the comparison with adjusted operands.
Commit: 52fac608bd3fb93caf08c137cea4591372aa8f31
https://github.com/llvm/llvm-project/commit/52fac608bd3fb93caf08c137cea4591372aa8f31
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/test/Transforms/InstCombine/ashr-lshr.ll
Log Message:
-----------
[InstCombine] Fold `[l|a]shr iN (X-1)&~X, N-1 -> [z|s]ext(X==0)` (#107259)
Alive2: https://alive2.llvm.org/ce/z/kwvTFn
Closes #107228.
`ashr iN (X-1)&~X, N-1` also exists. See
https://github.com/dtcxzyw/llvm-opt-benchmark/issues/1274.
Commit: b0ae93e847141becea7a2eeff35dc566110c1f58
https://github.com/llvm/llvm-project/commit/b0ae93e847141becea7a2eeff35dc566110c1f58
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
A llvm/test/Analysis/CostModel/AArch64/fp-conversions-odd-vector-types.ll
R llvm/test/Analysis/CostModel/AArch64/vec3-fp-conversions.ll
Log Message:
-----------
[AArch64] Add more type combinations to vector fp conversion cost tests.
Generealize test coverage for https://github.com/llvm/llvm-project/pull/107303
Also adjust the name to reflect the fact that it is not limited to
vectorrs with 3 elements now.
Commit: bf57ecf06e688a716fc9ce47386228503fa02e47
https://github.com/llvm/llvm-project/commit/bf57ecf06e688a716fc9ce47386228503fa02e47
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
Log Message:
-----------
[AArch64] Prevent generating tbl instruction instead of smull (#106375)
Generating tbl instruction for zext in an expression like: mul(zext(i8),
sext) is not optimal.
Instead, allowing later optimisations to generate smull(zext, sext)
would do some of the type extensions implicitly and be faster.
Commit: e4bb68b8717a20c5828b479f83c8648c2596e598
https://github.com/llvm/llvm-project/commit/e4bb68b8717a20c5828b479f83c8648c2596e598
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/test/Analysis/ctor-array.cpp
M clang/test/Analysis/nullptr.cpp
Log Message:
-----------
[analyzer] Model constructor initializer for an array member (#107537)
Bind the array member to the compound region associated with the
initializer list, e.g.:
class C {
int arr[2];
C() : arr{1, 2} {}
};
C c;
This change enables correct values in `c.arr[0]` and `c.arr[1]`
CPP-5647
Commit: 6ab5829ab7f03417ccb13e75d68b241871701be1
https://github.com/llvm/llvm-project/commit/6ab5829ab7f03417ccb13e75d68b241871701be1
Author: Johannes de Fine Licht <johannes at musicmedia.dk>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Log Message:
-----------
[MLIR][LLVM][NFC] Remove dead interface and add namespace qualifiers (#107573)
The `GetResultPtrElementType` interface is dead now that MLIR has fully
moved to opaque pointers, and can be removed.
Add namespace qualifiers to all argument types and return types of
interface methods for when they're used outside of LLVM dialect.
Commit: a9daad8280c081ee15c16cf8515630816695fb0e
https://github.com/llvm/llvm-project/commit/a9daad8280c081ee15c16cf8515630816695fb0e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
Log Message:
-----------
AMDGPU: Update live intervals in convertToThreeAddress (#104610)
Fixes #98741
Commit: 383057e5a0b53a79926dbdbae4cfcd39bfb44645
https://github.com/llvm/llvm-project/commit/383057e5a0b53a79926dbdbae4cfcd39bfb44645
Author: Spencer Abson <Spencer.Abson at arm.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/Sema/SemaARM.cpp
Log Message:
-----------
[Clang][AArch64] Fix -Wcovered-switch-default warning (SemaARM)
Commit: 100d9b89947bb1d42af20010bb594fa4c02542fc
https://github.com/llvm/llvm-project/commit/100d9b89947bb1d42af20010bb594fa4c02542fc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/PowerPC/all-atomics.ll
M llvm/test/CodeGen/X86/atomic6432.ll
M llvm/test/CodeGen/X86/pr5145.ll
Log Message:
-----------
Reapply "AtomicExpand: Allow incrementally legalizing atomicrmw" (#107307)
This reverts commit 63da545ccdd41d9eb2392a8d0e848a65eb24f5fa.
Use reverse iteration in the instruction loop to avoid sanitizer
errors. This also has the side effect of avoiding the AArch64
codegen quality regressions.
Closes #107309
Commit: 9528bcd5327c0120c82c84031b52b167037aa650
https://github.com/llvm/llvm-project/commit/9528bcd5327c0120c82c84031b52b167037aa650
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
Log Message:
-----------
[IRSim] Avoid repeated hash lookups (NFC) (#107510)
Commit: bd1559533d88f0d32b7ca17aa316b07b7924be2d
https://github.com/llvm/llvm-project/commit/bd1559533d88f0d32b7ca17aa316b07b7924be2d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
Log Message:
-----------
[IndVars] Avoid repeated hash lookups (NFC) (#107513)
Commit: 2461bc1c7ad5a78f39f75c6e99acf502b83401d2
https://github.com/llvm/llvm-project/commit/2461bc1c7ad5a78f39f75c6e99acf502b83401d2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
Log Message:
-----------
[Convergence] Avoid repeated hash lookups (NFC) (#107515)
Commit: b8d6885ff67efbc3142a2b49506ed0cc2b95e054
https://github.com/llvm/llvm-project/commit/b8d6885ff67efbc3142a2b49506ed0cc2b95e054
Author: Daniil Fukalov <dfukalov at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang-tools-extra/clangd/Feature.cpp
M clang-tools-extra/clangd/unittests/ClangdTests.cpp
M clang-tools-extra/clangd/unittests/CompileCommandsTests.cpp
M clang-tools-extra/clangd/unittests/SerializationTests.cpp
M clang/include/clang/Interpreter/Value.h
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/tools/driver/driver.cpp
M clang/unittests/Driver/GCCVersionTest.cpp
Log Message:
-----------
[NFC] Add explicit #include llvm-config.h where its macros are used, clang part. (#107301)
(this is clang related part)
Without these explicit includes, removing other headers, who implicitly
include llvm-config.h, may have non-trivial side effects. For example,
`clagd` may report even `llvm-config.h` as "no used" in case it defines
a macro, that is explicitly used with #ifdef. It is actually amplified
with different build configs which use different set of macros.
Commit: 56b29074fe924243640547a9fec35bef0942b210
https://github.com/llvm/llvm-project/commit/56b29074fe924243640547a9fec35bef0942b210
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.h
Log Message:
-----------
[mlir] Avoid repeated hash lookups (NFC) (#107518)
Commit: a37f7ae6268b25ff1673c94a7294ab242b9a11d8
https://github.com/llvm/llvm-project/commit/a37f7ae6268b25ff1673c94a7294ab242b9a11d8
Author: Nicolas van Kempen <nvankemp at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang-tools-extra/clang-tidy/add_new_check.py
Log Message:
-----------
[clang-tidy] Add type annotations to add_new_check.py, fix minor bug (#106801)
```
> python3 -m mypy --strict clang-tools-extra/clang-tidy/add_new_check.py
Success: no issues found in 1 source file
```
Also fix a bug when `--standard` is not provided on the command line:
the
generated test case has a `None` causing issues:
```
> python3 clang-tools-extra/clang-tidy/add_new_check.py performance XXX
Updating clang-tools-extra/clang-tidy/performance/CMakeLists.txt...
Creating clang-tools-extra/clang-tidy/performance/XxxCheck.h...
Creating clang-tools-extra/clang-tidy/performance/XxxCheck.cpp...
Updating clang-tools-extra/clang-tidy/performance/PerformanceTidyModule.cpp...
Updating clang-tools-extra/docs/ReleaseNotes.rst...
Creating clang-tools-extra/test/clang-tidy/checkers/performance/XXX.cpp...
Creating clang-tools-extra/docs/clang-tidy/checks/performance/XXX.rst...
Updating clang-tools-extra/docs/clang-tidy/checks/list.rst...
Done. Now it's your turn!
> head -n 1 clang-tools-extra/test/clang-tidy/checkers/performance/XXX.cpp
// RUN: %check_clang_tidy None%s performance-XXX %t
```
Commit: 01eb071de014759101940096a31d65babc8af04e
https://github.com/llvm/llvm-project/commit/01eb071de014759101940096a31d65babc8af04e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M mlir/lib/IR/AttrTypeSubElements.cpp
Log Message:
-----------
[mlir] Avoid repeated hash lookups (NFC) (#107519)
Commit: 109cd11dc4aea6b3596f8b2cb5a719f35b190cfa
https://github.com/llvm/llvm-project/commit/109cd11dc4aea6b3596f8b2cb5a719f35b190cfa
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
A llvm/test/CodeGen/AMDGPU/aa-as-infer.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
Log Message:
-----------
[Attributor] Skip AS specialization for volatile memory instructions (#107250)
Commit: 4af249fe6e81abd137c95bc25f5060ae305134ca
https://github.com/llvm/llvm-project/commit/4af249fe6e81abd137c95bc25f5060ae305134ca
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/bindings/ocaml/llvm/llvm.ml
M llvm/bindings/ocaml/llvm/llvm.mli
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Utils/LowerAtomic.cpp
M llvm/test/Assembler/atomic.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/AArch64/atomicrmw-cond-sub-clamp.ll
A llvm/test/CodeGen/ARM/atomicrmw-cond-sub-clamp.ll
A llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll
A llvm/test/CodeGen/LoongArch/atomicrmw-cond-sub-clamp.ll
A llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
A llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
A llvm/test/CodeGen/VE/Scalar/atomicrmw-cond-sub-clamp.ll
A llvm/test/CodeGen/WebAssembly/atomicrmw-cond-sub-clamp.ll
A llvm/test/CodeGen/X86/atomicrmw-cond-sub-clamp.ll
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
Add usub_cond and usub_sat operations to atomicrmw (#105568)
These both perform conditional subtraction, returning the minuend and
zero respectively, if the difference is negative.
Commit: 61ba60c15416db03872e94217fcc215371caad5d
https://github.com/llvm/llvm-project/commit/61ba60c15416db03872e94217fcc215371caad5d
Author: Ben Langmuir <blangmuir at apple.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
Log Message:
-----------
[orc] Avoid pathological propogation order (#107488)
In certain pathological object files we were getting extremely slow
linking because we were repeatedly propogating dependencies to the same
blocks instead of accumulating as many changes as possible. Change the
order of iteration so that we go through every node in the worklist
before returning to any previous node, reducing the number of expensive
dependency iterations.
In practice, this took one case from 60 seconds to 2 seconds. Note: the
performance is still non-deterministic, because the block order itself
is non-deterministic.
rdar://133734391
Commit: 2cb4d1b1bd7bde2724b79976e859684bd3f5c771
https://github.com/llvm/llvm-project/commit/2cb4d1b1bd7bde2724b79976e859684bd3f5c771
Author: Sergey Kachkov <109674256+skachkov-sc at users.noreply.github.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/expander-crashes.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/missing-phi-operand-update.ll
M llvm/test/Transforms/LoopStrengthReduce/preserve-lcssa.ll
Log Message:
-----------
[LSR] Do not create duplicated PHI nodes while preserving LCSSA form (#107380)
Motivating example: https://godbolt.org/z/eb97zrxhx
Here we have 2 induction variables in the loop: one is corresponding to
i variable (add rdx, 4), the other - to res (add rax, 2). The second
induction variable can be removed by rewriteLoopExitValues() method
(final value of res at loop exit is unroll_iter * -2); however, this
doesn't happen because we have duplicated LCSSA phi nodes at loop exit:
```
; Preheader:
for.body.preheader.new: ; preds = %for.body.preheader
%unroll_iter = and i64 %N, -4
br label %for.body
; Loop:
for.body: ; preds = %for.body, %for.body.preheader.new
%lsr.iv = phi i64 [ %lsr.iv.next, %for.body ], [ 0, %for.body.preheader.new ]
%i.07 = phi i64 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ]
%inc.3 = add nuw i64 %i.07, 4
%lsr.iv.next = add nsw i64 %lsr.iv, -2
%niter.ncmp.3.not = icmp eq i64 %unroll_iter, %inc.3
br i1 %niter.ncmp.3.not, label %for.end.loopexit.unr-lcssa.loopexit, label %for.body, !llvm.loop !7
; Exit blocks
for.end.loopexit.unr-lcssa.loopexit: ; preds = %for.body
%inc.3.lcssa = phi i64 [ %inc.3, %for.body ]
%lsr.iv.next.lcssa11 = phi i64 [ %lsr.iv.next, %for.body ]
%lsr.iv.next.lcssa = phi i64 [ %lsr.iv.next, %for.body ]
br label %for.end.loopexit.unr-lcssa
```
rewriteLoopExitValues requires %lsr.iv.next value to have only 2 uses:
one in LCSSA phi node, the other - in induction phi node. Here we have 3
uses of this value because of duplicated lcssa nodes, so the transform
doesn't apply and leads to an extra add operation inside the loop. The
proposed solution is to accumulate inserted instructions that will
require LCSSA form update into SetVector and then call
formLCSSAForInstructions for this SetVector once, so the same
instructions don't process twice.
Commit: 00e40c9b5b1a8208c4f2b785138d79ad0e9107af
https://github.com/llvm/llvm-project/commit/00e40c9b5b1a8208c4f2b785138d79ad0e9107af
Author: Kolya Panchenko <87679760+nikolaypanchenko at users.noreply.github.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
Log Message:
-----------
[LV] Support binary and unary operations with EVL-vectorization (#93854)
The patch adds `VPWidenEVLRecipe` which represents `VPWidenRecipe` + EVL
argument. The new recipe replaces `VPWidenRecipe` in
`tryAddExplicitVectorLength` for each binary and unary operations.
Follow up patches will extend support for remaining cases, like `FCmp`
and `ICmp`
Commit: 3edd21ba6e35e981f3a91b71358eb41cdbab12da
https://github.com/llvm/llvm-project/commit/3edd21ba6e35e981f3a91b71358eb41cdbab12da
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang-tools-extra/clangd/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependencies for b8d6885ff67efbc3142a2b49506ed0cc2b95e054
Commit: 80cf21dad150ae8fb82e4a17f3bc594d1486b210
https://github.com/llvm/llvm-project/commit/80cf21dad150ae8fb82e4a17f3bc594d1486b210
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
M libc/cmake/modules/LLVMLibCCheckMPFR.cmake
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/test/UnitTest/CMakeLists.txt
M libc/test/integration/startup/CMakeLists.txt
M libc/utils/MPFRWrapper/CMakeLists.txt
Log Message:
-----------
[libc] Fix unit test compile flags propagation. (#106128)
With this change, I was able to build and test for aarch64 & riscv64 on
x86-64 host as follow:
Pre-requisite:
- cross build toolchain for aarch64
```
$ sudo apt install binutils-aarch64-linux-gnu gcc-aarch64-linux-gnu g++-aarch64-linux-gnu
```
- cross build toolchain for riscv64
```
$ sudo apt install binutils-riscv64-linux-gnu gcc-riscv64-linux-gnu g++-riscv64-linux-gnu
```
- qemu user:
```
$ sudo apt install qemu qemu-user qemu-user-static
```
CMake invocation:
```
$ cmake ../runtimes -GNinja -DLLVM_ENABLE_RUNTIMES=libc -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DLIBC_TARGET_TRIPLE=<aarch64-linux-gnu/riscv64-linux-gnu> -DCMAKE_BUILD_TYPE=Release -DLIBC_TEST_COMPILE_OPTIONS_DEFAULT="-static"
$ ninja libc
$ ninja check-libc
```
Commit: deba13409245aabf3fda8b82a873336ea5238d3a
https://github.com/llvm/llvm-project/commit/deba13409245aabf3fda8b82a873336ea5238d3a
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/include/llvm/Object/Minidump.h
M llvm/lib/Object/Minidump.cpp
M llvm/lib/ObjectYAML/MinidumpYAML.cpp
M llvm/unittests/Object/MinidumpTest.cpp
M llvm/unittests/ObjectYAML/MinidumpYAMLTest.cpp
Log Message:
-----------
[Minidump] Support multiple exceptions in a minidump (#107319)
A fork of #97470, splitting off the LLVM changes from the LLDB specific
changes. This patch enables a minidump file to have multiple exceptions,
exposed via an iterator of Expected streams.
Commit: d4d4e77918118f1444dc5ca230d4fdf82bb05b74
https://github.com/llvm/llvm-project/commit/d4d4e77918118f1444dc5ca230d4fdf82bb05b74
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lldb/include/lldb/API/SBMemoryRegionInfo.h
M lldb/include/lldb/API/SBSaveCoreOptions.h
M lldb/include/lldb/Symbol/SaveCoreOptions.h
A lldb/include/lldb/Target/CoreFileMemoryRanges.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Utility/RangeMap.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/include/lldb/lldb-private-interfaces.h
M lldb/source/API/SBSaveCoreOptions.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.h
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.h
M lldb/source/Plugins/ObjectFile/Minidump/ObjectFileMinidump.h
M lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
M lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.h
M lldb/source/Symbol/SaveCoreOptions.cpp
M lldb/source/Target/CMakeLists.txt
A lldb/source/Target/CoreFileMemoryRanges.cpp
M lldb/source/Target/Process.cpp
M lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py
M lldb/unittests/Process/Utility/CMakeLists.txt
A lldb/unittests/Process/Utility/CoreFileMemoryRangesTest.cpp
Log Message:
-----------
[LLDB] Reappply SBSaveCore AddMemoryList (#107159)
Reapplies #106293, testing identified issue in the merging code. I used
this opportunity to strip CoreFileMemoryRanges to it's own file and then
add unit tests on it's behavior.
Commit: eb0f12188a3afa10ba353a32328577dc0d898524
https://github.com/llvm/llvm-project/commit/eb0f12188a3afa10ba353a32328577dc0d898524
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M libcxx/include/__math/copysign.h
M libcxx/include/__math/remainder.h
M libcxx/include/__tuple/find_index.h
M libcxx/include/__tuple/make_tuple_types.h
M libcxx/include/__tuple/sfinae_helpers.h
M libcxx/include/__tuple/tuple_element.h
M libcxx/include/__tuple/tuple_indices.h
M libcxx/include/__tuple/tuple_like_ext.h
M libcxx/include/__tuple/tuple_like_no_subrange.h
M libcxx/include/__tuple/tuple_size.h
M libcxx/include/future
M libcxx/include/variant
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++][modules] Tweak a few includes (#107467)
Add a few missing includes, remove two unnecessary ones and use
__cstddef/size_t.h instead of <cstddef> in a few places. This is a
collection of miscellaneous findings that collectively unblock other
modularization patches.
Commit: f8350f13020a27e7aa74fd4ab7919503c24771ca
https://github.com/llvm/llvm-project/commit/f8350f13020a27e7aa74fd4ab7919503c24771ca
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__cstddef/byte.h
A libcxx/include/__fwd/byte.h
M libcxx/include/__type_traits/is_trivially_lexicographically_comparable.h
M libcxx/include/module.modulemap
M libcxx/utils/generate_iwyu_mapping.py
Log Message:
-----------
[libc++][modules] Introduce a forward-declaration for std::byte (#107402)
We need a forward-declaration so that we can know about std::byte from
some type traits without having to include std::byte's definition, which
(circularly) depends back on type traits.
Commit: ce192b87b2a09ee27e4077763db0486921a485c0
https://github.com/llvm/llvm-project/commit/ce192b87b2a09ee27e4077763db0486921a485c0
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[Vectorize] Fix a warning
This patch fixes:
llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp:1278:12: error:
unused variable 'Op0' [-Werror,-Wunused-variable]
Commit: 37086ea21cd966465694cc6998a6e937846ec28d
https://github.com/llvm/llvm-project/commit/37086ea21cd966465694cc6998a6e937846ec28d
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
A libcxx/test/std/iterators/iterator.primitives/iterator.traits/empty.compile.pass.cpp
R libcxx/test/std/iterators/iterator.primitives/iterator.traits/empty.verify.cpp
Log Message:
-----------
[libc++] Decouple iterator_traits test from precise Clang diagnostics (#107478)
This makes the test more robust and prevents it from breaking when the
diagnostic changes subtly (e.g. under modules).
Commit: cfc095118c149d6d95a828139ed54fb34e99a3f3
https://github.com/llvm/llvm-project/commit/cfc095118c149d6d95a828139ed54fb34e99a3f3
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-cuda.h
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
Log Message:
-----------
[flang][cuda] Do not check assignment semantic in cuf kernel (#107512)
Commit: ce91e2153f1a8f725a1e4853bb21e7dbfcdae9d7
https://github.com/llvm/llvm-project/commit/ce91e2153f1a8f725a1e4853bb21e7dbfcdae9d7
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/BPSectionOrderer.h
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/SectionPriorities.cpp
M lld/test/MachO/bp-section-orderer-errs.s
M lld/test/MachO/bp-section-orderer-stress.s
Log Message:
-----------
[lld][InstrProf] Sort startup functions for compression (#107348)
Commit: 62180dfd8d86af92219662d0cdb01672d801f86f
https://github.com/llvm/llvm-project/commit/62180dfd8d86af92219662d0cdb01672d801f86f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
M llvm/lib/Target/RISCV/RISCVCallingConv.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
DataLayout, ABI, and TargetLowering can all be obtained via the
MachineFunction reference in the State object. This is how the targets
that use TableGen for CC handlers get these objects.
This might be a little slower, but it simplies all the callers in
SelectionDAG and GlobalISel.
Commit: e1fdaaafc51bf7323813139b2809ffea43e65ee4
https://github.com/llvm/llvm-project/commit/e1fdaaafc51bf7323813139b2809ffea43e65ee4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
Log Message:
-----------
[AMDGPU] Work around a warning
This patch works around:
llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp:1101:13:
error: enumeration values 'USubCond' and 'USubSat' not handled in
switch [-Werror,-Wswitch]
I've notified the author in #105568.
Commit: 1accedc1eba1f00cd522012a1c5bb84e3686663b
https://github.com/llvm/llvm-project/commit/1accedc1eba1f00cd522012a1c5bb84e3686663b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/setcc-lowering.ll
Log Message:
-----------
[X86] setcc-lowering.ll - add nounwind to remove cfi noise. NFC.
Commit: c1f78d349704c4a6be6abb436687f3ce449d3778
https://github.com/llvm/llvm-project/commit/c1f78d349704c4a6be6abb436687f3ce449d3778
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerSELECTWithCmpZero - add missing description of fold and cleanup zero/allones extension code. NFC.
Commit: ce2e38653fab52cc53c7a267727b996c14c7af82
https://github.com/llvm/llvm-project/commit/ce2e38653fab52cc53c7a267727b996c14c7af82
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/CodeGen/AMDGPU/aa-as-infer.ll
Log Message:
-----------
[Attributor] Add support for atomic operations in `AAAddressSpace` (#106927)
Commit: c08f80e348ed84e4372d4a8687dfcaaa2df813aa
https://github.com/llvm/llvm-project/commit/c08f80e348ed84e4372d4a8687dfcaaa2df813aa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/select.ll
Log Message:
-----------
[X86] select.ll - add ADD/SUB identity select test cases
LowerSELECTWithCmpZero already handles "SELECT (X != 0), Y, (OR/XOR Y, Z) -> (OR/XOR Y, (AND (0 - X), Z))" - we can also handle ADD/SUB in a similar way, although SUB is more restricted as its not commutative.
Commit: fd13cc03bdc9696bcab98ddb9b177ed89650ca30
https://github.com/llvm/llvm-project/commit/fd13cc03bdc9696bcab98ddb9b177ed89650ca30
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
Log Message:
-----------
[RISCV] Use Subtarget variable instaed of TLI.getSubtarget(). NFC
Commit: a291fe5ed44fa37493d038c78ff4d73135fd85a9
https://github.com/llvm/llvm-project/commit/a291fe5ed44fa37493d038c78ff4d73135fd85a9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/test/CodeGenOpenCL/atomics-cas-remarks-gfx90a.cl
M clang/test/CodeGenOpenCL/atomics-unsafe-hw-remarks-gfx90a.cl
Log Message:
-----------
clang/AMDGPU: Update test message order
Order of atomic expansion remarks is backwards since
100d9b89947bb1d42af20010bb594fa4c02542fc
Commit: 0ffa377c6b2583ecb326af8b9084951a106d3881
https://github.com/llvm/llvm-project/commit/0ffa377c6b2583ecb326af8b9084951a106d3881
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/IR/ModuleSummaryIndexYAML.h
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
Log Message:
-----------
[ThinLTO] Shrink GlobalValueSummary by 8 bytes (#107342)
During the ThinLTO indexing step for one of our large applications, we
create 7.5 million instances of GlobalValueSummary.
Changing:
std::vector<ValueInfo> RefEdgeList;
to:
SmallVector<ValueInfo, 0> RefEdgeList;
in GlobalValueSummary reduces the size of each instance by 8 bytes.
The rest of the patch makes the same change to other places so that
the types stay compatible across function boundaries.
Commit: 2e9b3316ee8b4339e2f023173db780ea09c44a88
https://github.com/llvm/llvm-project/commit/2e9b3316ee8b4339e2f023173db780ea09c44a88
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/CMakeLists.txt
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan_context.cpp
A compiler-rt/lib/rtsan/rtsan_flags.cpp
A compiler-rt/lib/rtsan/rtsan_flags.h
A compiler-rt/lib/rtsan/rtsan_flags.inc
M compiler-rt/lib/rtsan/rtsan_stack.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_context.cpp
A compiler-rt/test/rtsan/unrecognized_flags.cpp
M llvm/test/Unit/lit.cfg.py
M llvm/utils/lit/lit/TestingConfig.py
M llvm/utils/lit/lit/llvm/config.py
Log Message:
-----------
[compiler-rt][rtsan] Introduce RTSAN_OPTIONS and flags (#107174)
This matches much of the boilerplate found in the other sanitizers.
Commit: df138625df5881c7e593db13fa13cf39d68856cf
https://github.com/llvm/llvm-project/commit/df138625df5881c7e593db13fa13cf39d68856cf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
Log Message:
-----------
AMDGPU: Remove unnecessary pointer bitcast
Commit: a6577791d4ed8ca7f548598fb179c473d275178b
https://github.com/llvm/llvm-project/commit/a6577791d4ed8ca7f548598fb179c473d275178b
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
LV: fix style after cursory reading (NFC) (#105830)
Commit: fb1494137e551448d8742d5e6367bf62e923598d
https://github.com/llvm/llvm-project/commit/fb1494137e551448d8742d5e6367bf62e923598d
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/include/clang/Basic/Features.def
A clang/test/Lexer/has_feature_realtime_sanitizer.cpp
Log Message:
-----------
[clang][rtsan] Add realtime_sanitizer to Features.def (#106650)
Allows us to introduce the scoped disabler in #106736
Commit: 59f8796aaabc1ce400a8698431d3c6bfab4ad1a4
https://github.com/llvm/llvm-project/commit/59f8796aaabc1ce400a8698431d3c6bfab4ad1a4
Author: Thomas Fransham <tfransham at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/CMakeLists.txt
M llvm/cmake/modules/AddLLVM.cmake
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/include/llvm/ADT/Any.h
M llvm/include/llvm/Analysis/LazyCallGraph.h
M llvm/include/llvm/Analysis/LoopInfo.h
M llvm/include/llvm/Analysis/LoopNestAnalysis.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/Support/Compiler.h
M llvm/tools/llvm-shlib/CMakeLists.txt
M llvm/utils/TableGen/Basic/CMakeLists.txt
M llvm/utils/TableGen/Common/CMakeLists.txt
Log Message:
-----------
Initial changes for llvm shared library build using explicit visibility annotations
These are my initial build and code changes to supporting building llvm
as shared library/DLL on windows(without force exporting all symbols)
and making symbol visibility hidden by default on Linux which adding
explicit symbol visibility macros to the whole llvm codebase.
Updated cmake code to allow building llvm-shlib on windows by appending
/WHOLEARCHIVE:lib to the linker options.
Remove the hardcoded CMake error from using LLVM_BUILD_LLVM_DYLIB on
windows.
Updated CMake to define new macros to control conditional export macros
in llvm/Support/Compiler.h
Use /Zc:dllexportInlines- when compiling with clang-cl on windows with a
opt out CMake option to disable using it.
Replace some use of LLVM_EXTERNAL_VISIBILITY with new export macros.
Some of the cmake and code changes are based on @tstellar's earlier PR
https://github.com/llvm/llvm-project/pull/67502.
I have Windows building using clang-cl, while for MSVC its at-least able
to build libllvm, but some tests can't build because llvm iterator
template metaprogramming that doesn't work well with dllexport. Linux
should build without issue. My full branch is here
https://github.com/fsfod/llvm-project/tree/llvm-export-api-20.0 and
including all the auto generated export macros from clang tooling based
system.
Commit: c014db47ca298ad7a0f52a57c3bfc2a9914371b2
https://github.com/llvm/llvm-project/commit/c014db47ca298ad7a0f52a57c3bfc2a9914371b2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT] Remove the const variant of LookupBucketFor in DenseMap (#107608)
DenseMap has const and non-const variants of LookupBucketFor to find a
bucket for insertion purposes. Now that queries (e.g. find, contains,
and erase) have been migrated to use doFind instead of
LookupBucketFor, nobody uses the const variant of LookupBucketFor.
This patch removes the const variant.
As far as the logistics go, the non-const variant calls the const
variant with a couple of const_cast, so this patch repurposes the
const variant as the non-const one while removing the original
non-const variant.
Commit: fd2da9e5818ec6e53100f92c9eb6ed4f1b0b99eb
https://github.com/llvm/llvm-project/commit/fd2da9e5818ec6e53100f92c9eb6ed4f1b0b99eb
Author: vporpo <vporpodas at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement PoisonValue (#107324)
This patch implements sandboxir::PoisonValue mirroring
llvm::PoisonValue.
Commit: 4c1a6a29cce08cd6229a0c5a8b18a8319588d858
https://github.com/llvm/llvm-project/commit/4c1a6a29cce08cd6229a0c5a8b18a8319588d858
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
A flang/test/Driver/q-unused-arguments.f90
Log Message:
-----------
[flang][Driver] Support -Qunused-arguments (#107462)
This partially addresses:
https://github.com/llvm/llvm-project/issues/89888
Commit: 0745219d4a8fc26fe149d851be285f78568afa70
https://github.com/llvm/llvm-project/commit/0745219d4a8fc26fe149d851be285f78568afa70
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-param-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
Log Message:
-----------
[AMDGPU] Add target intrinsic for s_buffer_prefetch_data (#107293)
Commit: 5d146c689e28e2878ba5a1aab9560e3c4fa2c2e1
https://github.com/llvm/llvm-project/commit/5d146c689e28e2878ba5a1aab9560e3c4fa2c2e1
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M compiler-rt/include/CMakeLists.txt
A compiler-rt/include/sanitizer/rtsan_interface.h
M compiler-rt/lib/rtsan/rtsan.h
A compiler-rt/test/rtsan/disabler.cpp
Log Message:
-----------
[compiler-rt][rtsan] Introduce rtsan_interface.h and ScopedDisabler (#106736)
Commit: 7f77db4ffca9b275b40e8720208a03dd6cbc390e
https://github.com/llvm/llvm-project/commit/7f77db4ffca9b275b40e8720208a03dd6cbc390e
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn
Log Message:
-----------
[gn] port 5d146c689e28
Commit: d60ca0c913f7521ee05da08a8a0c9dda1c439c88
https://github.com/llvm/llvm-project/commit/d60ca0c913f7521ee05da08a8a0c9dda1c439c88
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M compiler-rt/lib/builtins/divsc3.c
M compiler-rt/lib/builtins/fp_lib.h
M compiler-rt/test/builtins/Unit/divsc3_test.c
Log Message:
-----------
[compiler-rt][builtins]Adjust complex division for aarch64 (#106664)
Adjust __divsc3 to ensure consistent behavior across x86_64 and AArch64 when the divisor should be treated as infinity if one of its components is a NaN (including signaling NaNs).
Test plan: ninja check-all
Commit: 1a6df6756d3530e4de70bb8afa2acc1ddfb22867
https://github.com/llvm/llvm-project/commit/1a6df6756d3530e4de70bb8afa2acc1ddfb22867
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
Log Message:
-----------
[gn build] Port d4d4e7791811
Commit: f6196e7f9edcca9f178fbe5baa67da2bd94190f8
https://github.com/llvm/llvm-project/commit/f6196e7f9edcca9f178fbe5baa67da2bd94190f8
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port f8350f13020a
Commit: de88d7db7b77141297fbb5638ee1e18d1fba53b8
https://github.com/llvm/llvm-project/commit/de88d7db7b77141297fbb5638ee1e18d1fba53b8
Author: ziqingluo-90 <ziqing_luo at apple.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions.cpp
Log Message:
-----------
[-Wunsafe-buffer-usage] Fix a bug in "warning libc functions (#101583)"
The commit d7dd2c468fecae871ba67e891a3519c758c94b63 crashes for such
an example:
```
void printf() { printf(); }
```
Because it assumes `printf` must have arguments. This commit fixes
this issue.
(rdar://117182250)
Commit: 941841b19d4f8832012f0c6ccd57954917369a3b
https://github.com/llvm/llvm-project/commit/941841b19d4f8832012f0c6ccd57954917369a3b
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/unittests/IR/VectorTypesTest.cpp
Log Message:
-----------
[Vectorize] Update comment of getSubdividedVectorType (#107632)
The original comment here is wrong, as demonstrated by the included
test.
Update the comment to reflect what getSubdividedVectorType actually
does.
Commit: 876b0e60feb6ee4eabb1c8b52881117ce93b3c4c
https://github.com/llvm/llvm-project/commit/876b0e60feb6ee4eabb1c8b52881117ce93b3c4c
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M libc/hdr/types/CMakeLists.txt
M libc/src/signal/linux/CMakeLists.txt
Log Message:
-----------
[libc] Fix signal's dependency on the proxy header sighandler_t. (#107605)
Commit: 787cd8f0fee8659335b0ed501d6896275d936f3d
https://github.com/llvm/llvm-project/commit/787cd8f0fee8659335b0ed501d6896275d936f3d
Author: gulfemsavrun <gulfem at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
A compiler-rt/test/profile/Linux/instrprof-debug-info-correlate-debuginfod.c
A compiler-rt/test/profile/instrprof-binary-correlate-debuginfod.c
M compiler-rt/test/profile/lit.cfg.py
M llvm/docs/CommandGuide/llvm-profdata.rst
M llvm/include/llvm/ProfileData/InstrProfCorrelator.h
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/lib/ProfileData/InstrProfCorrelator.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/tools/llvm-profdata/CMakeLists.txt
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[InstrProf] Add debuginfod correlation support (#106606)
This patch adds debuginfod support into llvm-profdata to
find the assosicated executable by a build id in a raw
profile to correlate a profile with a provided correlation
kind (debug-info or binary).
Commit: 6cb2d40387f613c72ec8f66e47a5eb0f7e4b0f1f
https://github.com/llvm/llvm-project/commit/6cb2d40387f613c72ec8f66e47a5eb0f7e4b0f1f
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
M llvm/lib/Analysis/CtxProfAnalysis.cpp
A llvm/test/Analysis/CtxProfAnalysis/load-unapplicable.ll
Log Message:
-----------
[ctx_prof] Handle case when no root is in this Module. (#107463)
If none of the functions in this `Module` are roots in the contextual profile, we can't use it and should just return the `{}` case.
Commit: 3e7a95c9bf964c7c8f2647b208254b7e97022a16
https://github.com/llvm/llvm-project/commit/3e7a95c9bf964c7c8f2647b208254b7e97022a16
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-06 (Fri, 06 Sep 2024)
Changed paths:
A .github/workflows/commit-access-review.py
A .github/workflows/commit-access-review.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/pr-code-format.yml
M .github/workflows/release-asset-audit.py
M .github/workflows/release-binaries-save-stage/action.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M .mailmap
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/BinaryFunctionProfile.cpp
M bolt/lib/Passes/ValidateInternalCalls.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Profile/YAMLProfileWriter.cpp
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
A bolt/test/AArch64/internal-call.s
M bolt/test/X86/end-symbol.test
A bolt/test/X86/infer-fall-throughs.s
M bolt/test/X86/instrumentation-eh_frame_hdr.cpp
A bolt/test/X86/yaml-unknown-keys.test
M bolt/tools/merge-fdata/merge-fdata.cpp
M clang-tools-extra/clang-doc/BitcodeReader.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clang-tidy/add_new_check.py
M clang-tools-extra/clang-tidy/bugprone/CastingThroughVoidCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
M clang-tools-extra/clang-tidy/misc/UnconventionalAssignOperatorCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStdFormatCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStdPrintCheck.cpp
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.h
M clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
M clang-tools-extra/clangd/CollectMacros.cpp
M clang-tools-extra/clangd/CollectMacros.h
M clang-tools-extra/clangd/Feature.cpp
M clang-tools-extra/clangd/ModulesBuilder.cpp
M clang-tools-extra/clangd/ParsedAST.cpp
M clang-tools-extra/clangd/TUScheduler.cpp
M clang-tools-extra/clangd/TidyFastChecks.inc
M clang-tools-extra/clangd/unittests/ClangdTests.cpp
M clang-tools-extra/clangd/unittests/CompileCommandsTests.cpp
M clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
M clang-tools-extra/clangd/unittests/SerializationTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/unconventional-assign-operator.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-std-format.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-std-print.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/avoid-nested-conditional-operator.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
M clang-tools-extra/include-cleaner/lib/WalkAST.cpp
M clang-tools-extra/include-cleaner/unittests/WalkASTTest.cpp
M clang-tools-extra/test/clang-doc/basic-project.test
M clang-tools-extra/test/clang-doc/enum.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/casting-through-void.cpp
A clang-tools-extra/test/clang-tidy/checkers/misc/unconventional-assign-operator-cxx23.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-format-member.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-print-member.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion.c
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion.cpp
M clang-tools-extra/unittests/clang-doc/HTMLGeneratorTest.cpp
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_location.py
A clang/bindings/python/tests/cindex/test_source_range.py
M clang/cmake/caches/CrossWinToARMLinux.cmake
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Release.cmake
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ClangFormattedStatus.rst
M clang/docs/HLSL/ExpectedDifferences.rst
M clang/docs/InternalsManual.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/Multilib.rst
A clang/docs/RealtimeSanitizer.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/StandardCPlusPlusModules.rst
M clang/docs/UndefinedBehaviorSanitizer.rst
M clang/docs/UsersManual.rst
M clang/docs/analyzer/checkers.rst
M clang/docs/index.rst
M clang/docs/tools/clang-formatted-files.txt
M clang/docs/tools/generate_formatted_state.py
M clang/include/clang-c/CXSourceLocation.h
M clang/include/clang-c/Index.h
M clang/include/clang/APINotes/APINotesReader.h
M clang/include/clang/APINotes/APINotesWriter.h
M clang/include/clang/APINotes/Types.h
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/ASTNodeTraverser.h
M clang/include/clang/AST/Attr.h
M clang/include/clang/AST/Availability.h
M clang/include/clang/AST/CXXRecordDeclDefinitionBits.def
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclFriend.h
M clang/include/clang/AST/DeclID.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsage.h
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsNVPTX.def
M clang/include/clang/Basic/BuiltinsWebAssembly.def
M clang/include/clang/Basic/BuiltinsX86.def
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/include/clang/Basic/Features.def
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Basic/Sanitizers.def
M clang/include/clang/Basic/SourceManager.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetCXXABI.def
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Basic/TypeNodes.td
M clang/include/clang/Basic/arm_fp16.td
A clang/include/clang/Basic/arm_immcheck_incl.td
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/arm_neon_incl.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Driver/Multilib.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/SanitizerArgs.h
M clang/include/clang/ExtractAPI/API.h
M clang/include/clang/ExtractAPI/DeclarationFragments.h
M clang/include/clang/ExtractAPI/ExtractAPIVisitor.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Interpreter/Value.h
M clang/include/clang/Parse/Parser.h
R clang/include/clang/Rewrite/Core/DeltaTree.h
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
R clang/include/clang/Rewrite/Core/RewriteRope.h
M clang/include/clang/Rewrite/Core/Rewriter.h
M clang/include/clang/Sema/ExternalSemaSource.h
M clang/include/clang/Sema/Initialization.h
M clang/include/clang/Sema/MultiplexExternalSemaSource.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/include/clang/Sema/SemaARM.h
M clang/include/clang/Sema/SemaAVR.h
M clang/include/clang/Sema/SemaBPF.h
M clang/include/clang/Sema/SemaCUDA.h
M clang/include/clang/Sema/SemaCodeCompletion.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Sema/SemaHexagon.h
M clang/include/clang/Sema/SemaLoongArch.h
M clang/include/clang/Sema/SemaM68k.h
M clang/include/clang/Sema/SemaMIPS.h
M clang/include/clang/Sema/SemaMSP430.h
M clang/include/clang/Sema/SemaNVPTX.h
M clang/include/clang/Sema/SemaObjC.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Sema/SemaOpenCL.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Sema/SemaPPC.h
M clang/include/clang/Sema/SemaPseudoObject.h
M clang/include/clang/Sema/SemaRISCV.h
M clang/include/clang/Sema/SemaSYCL.h
M clang/include/clang/Sema/SemaSwift.h
M clang/include/clang/Sema/SemaSystemZ.h
M clang/include/clang/Sema/SemaWasm.h
M clang/include/clang/Sema/SemaX86.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/Serialization/TypeBitCodes.def
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CheckerHelpers.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/APINotes/APINotesFormat.h
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/APINotes/APINotesWriter.cpp
M clang/lib/APINotes/APINotesYAMLCompiler.cpp
M clang/lib/ARCMigrate/ARCMT.cpp
M clang/lib/ARCMigrate/ObjCMT.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/Availability.cpp
A clang/lib/AST/ByteCode/Boolean.h
A clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
A clang/lib/AST/ByteCode/ByteCodeEmitter.h
A clang/lib/AST/ByteCode/Compiler.cpp
A clang/lib/AST/ByteCode/Compiler.h
A clang/lib/AST/ByteCode/Context.cpp
A clang/lib/AST/ByteCode/Context.h
A clang/lib/AST/ByteCode/Descriptor.cpp
A clang/lib/AST/ByteCode/Descriptor.h
A clang/lib/AST/ByteCode/Disasm.cpp
A clang/lib/AST/ByteCode/DynamicAllocator.cpp
A clang/lib/AST/ByteCode/DynamicAllocator.h
A clang/lib/AST/ByteCode/EvalEmitter.cpp
A clang/lib/AST/ByteCode/EvalEmitter.h
A clang/lib/AST/ByteCode/EvaluationResult.cpp
A clang/lib/AST/ByteCode/EvaluationResult.h
A clang/lib/AST/ByteCode/Floating.cpp
A clang/lib/AST/ByteCode/Floating.h
A clang/lib/AST/ByteCode/Frame.cpp
A clang/lib/AST/ByteCode/Frame.h
A clang/lib/AST/ByteCode/Function.cpp
A clang/lib/AST/ByteCode/Function.h
A clang/lib/AST/ByteCode/FunctionPointer.cpp
A clang/lib/AST/ByteCode/FunctionPointer.h
A clang/lib/AST/ByteCode/Integral.h
A clang/lib/AST/ByteCode/IntegralAP.h
A clang/lib/AST/ByteCode/Interp.cpp
A clang/lib/AST/ByteCode/Interp.h
A clang/lib/AST/ByteCode/InterpBlock.cpp
A clang/lib/AST/ByteCode/InterpBlock.h
A clang/lib/AST/ByteCode/InterpBuiltin.cpp
A clang/lib/AST/ByteCode/InterpFrame.cpp
A clang/lib/AST/ByteCode/InterpFrame.h
A clang/lib/AST/ByteCode/InterpShared.cpp
A clang/lib/AST/ByteCode/InterpShared.h
A clang/lib/AST/ByteCode/InterpStack.cpp
A clang/lib/AST/ByteCode/InterpStack.h
A clang/lib/AST/ByteCode/InterpState.cpp
A clang/lib/AST/ByteCode/InterpState.h
A clang/lib/AST/ByteCode/MemberPointer.cpp
A clang/lib/AST/ByteCode/MemberPointer.h
A clang/lib/AST/ByteCode/Opcode.h
A clang/lib/AST/ByteCode/Opcodes.td
A clang/lib/AST/ByteCode/Pointer.cpp
A clang/lib/AST/ByteCode/Pointer.h
A clang/lib/AST/ByteCode/PrimType.cpp
A clang/lib/AST/ByteCode/PrimType.h
A clang/lib/AST/ByteCode/Primitives.h
A clang/lib/AST/ByteCode/Program.cpp
A clang/lib/AST/ByteCode/Program.h
A clang/lib/AST/ByteCode/Record.cpp
A clang/lib/AST/ByteCode/Record.h
A clang/lib/AST/ByteCode/Source.cpp
A clang/lib/AST/ByteCode/Source.h
A clang/lib/AST/ByteCode/State.cpp
A clang/lib/AST/ByteCode/State.h
M clang/lib/AST/CMakeLists.txt
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclFriend.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprClassification.cpp
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/FormatString.cpp
R clang/lib/AST/Interp/Boolean.h
R clang/lib/AST/Interp/ByteCodeEmitter.cpp
R clang/lib/AST/Interp/ByteCodeEmitter.h
R clang/lib/AST/Interp/Compiler.cpp
R clang/lib/AST/Interp/Compiler.h
R clang/lib/AST/Interp/Context.cpp
R clang/lib/AST/Interp/Context.h
R clang/lib/AST/Interp/Descriptor.cpp
R clang/lib/AST/Interp/Descriptor.h
R clang/lib/AST/Interp/Disasm.cpp
R clang/lib/AST/Interp/DynamicAllocator.cpp
R clang/lib/AST/Interp/DynamicAllocator.h
R clang/lib/AST/Interp/EvalEmitter.cpp
R clang/lib/AST/Interp/EvalEmitter.h
R clang/lib/AST/Interp/EvaluationResult.cpp
R clang/lib/AST/Interp/EvaluationResult.h
R clang/lib/AST/Interp/Floating.cpp
R clang/lib/AST/Interp/Floating.h
R clang/lib/AST/Interp/Frame.cpp
R clang/lib/AST/Interp/Frame.h
R clang/lib/AST/Interp/Function.cpp
R clang/lib/AST/Interp/Function.h
R clang/lib/AST/Interp/FunctionPointer.h
R clang/lib/AST/Interp/Integral.h
R clang/lib/AST/Interp/IntegralAP.h
R clang/lib/AST/Interp/Interp.cpp
R clang/lib/AST/Interp/Interp.h
R clang/lib/AST/Interp/InterpBlock.cpp
R clang/lib/AST/Interp/InterpBlock.h
R clang/lib/AST/Interp/InterpBuiltin.cpp
R clang/lib/AST/Interp/InterpFrame.cpp
R clang/lib/AST/Interp/InterpFrame.h
R clang/lib/AST/Interp/InterpShared.cpp
R clang/lib/AST/Interp/InterpShared.h
R clang/lib/AST/Interp/InterpStack.cpp
R clang/lib/AST/Interp/InterpStack.h
R clang/lib/AST/Interp/InterpState.cpp
R clang/lib/AST/Interp/InterpState.h
R clang/lib/AST/Interp/MemberPointer.cpp
R clang/lib/AST/Interp/MemberPointer.h
R clang/lib/AST/Interp/Opcode.h
R clang/lib/AST/Interp/Opcodes.td
R clang/lib/AST/Interp/Pointer.cpp
R clang/lib/AST/Interp/Pointer.h
R clang/lib/AST/Interp/PrimType.cpp
R clang/lib/AST/Interp/PrimType.h
R clang/lib/AST/Interp/Primitives.h
R clang/lib/AST/Interp/Program.cpp
R clang/lib/AST/Interp/Program.h
R clang/lib/AST/Interp/Record.cpp
R clang/lib/AST/Interp/Record.h
R clang/lib/AST/Interp/Source.cpp
R clang/lib/AST/Interp/Source.h
R clang/lib/AST/Interp/State.cpp
R clang/lib/AST/Interp/State.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/ODRHash.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/lib/Analysis/ThreadSafety.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/ABIInfoImpl.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuilder.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCall.h
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CodeGenTBAA.cpp
M clang/lib/CodeGen/CodeGenTBAA.h
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/CodeGenTypes.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/CodeGen/Targets/PPC.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/Multilib.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/HIPUtility.cpp
M clang/lib/Driver/ToolChains/HLSL.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/OHOS.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Driver/Types.cpp
M clang/lib/ExtractAPI/API.cpp
M clang/lib/ExtractAPI/DeclarationFragments.cpp
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
M clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Format/WhitespaceManager.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Frontend/PrintPreprocessedOutput.cpp
M clang/lib/Frontend/Rewrite/FixItRewriter.cpp
M clang/lib/Frontend/Rewrite/HTMLPrint.cpp
M clang/lib/Frontend/Rewrite/RewriteMacros.cpp
M clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp
M clang/lib/Frontend/Rewrite/RewriteObjC.cpp
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/__clang_cuda_device_functions.h
M clang/lib/Headers/__clang_cuda_math.h
M clang/lib/Headers/__clang_hip_math.h
A clang/lib/Headers/avx10_2_512bf16intrin.h
A clang/lib/Headers/avx10_2_512convertintrin.h
A clang/lib/Headers/avx10_2bf16intrin.h
A clang/lib/Headers/avx10_2convertintrin.h
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avxintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/gfniintrin.h
M clang/lib/Headers/hlsl/hlsl_basic_types.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/pmmintrin.h
M clang/lib/Headers/smmintrin.h
M clang/lib/Headers/tmmintrin.h
M clang/lib/Headers/wasm_simd128.h
M clang/lib/Headers/xmmintrin.h
M clang/lib/Lex/Lexer.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseObjc.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Parse/ParseTemplate.cpp
M clang/lib/Rewrite/CMakeLists.txt
R clang/lib/Rewrite/DeltaTree.cpp
M clang/lib/Rewrite/HTMLRewrite.cpp
R clang/lib/Rewrite/RewriteRope.cpp
M clang/lib/Rewrite/Rewriter.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/MultiplexExternalSemaSource.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaAvailability.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprObjC.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaMIPS.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaPPC.cpp
M clang/lib/Sema/SemaPseudoObject.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaSYCL.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaStmtAsm.cpp
M clang/lib/Sema/SemaSwift.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/BlockInCriticalSectionChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp
M clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StringChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/Taint.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/CallEvent.cpp
M clang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
M clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/lib/Tooling/Core/Replacement.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/lib/Tooling/Refactoring/AtomicChange.cpp
A clang/test/APINotes/Inputs/Headers/Fields.apinotes
A clang/test/APINotes/Inputs/Headers/Fields.h
M clang/test/APINotes/Inputs/Headers/module.modulemap
A clang/test/APINotes/fields.cpp
A clang/test/AST/ByteCode/arrays.cpp
A clang/test/AST/ByteCode/atomic.c
A clang/test/AST/ByteCode/atomic.cpp
A clang/test/AST/ByteCode/bitfields.cpp
A clang/test/AST/ByteCode/builtin-align-cxx.cpp
A clang/test/AST/ByteCode/builtin-constant-p.cpp
A clang/test/AST/ByteCode/builtin-functions.cpp
A clang/test/AST/ByteCode/builtins.cpp
A clang/test/AST/ByteCode/c.c
A clang/test/AST/ByteCode/c23.c
A clang/test/AST/ByteCode/codegen.c
A clang/test/AST/ByteCode/codegen.cpp
A clang/test/AST/ByteCode/comma.cpp
A clang/test/AST/ByteCode/complex.c
A clang/test/AST/ByteCode/complex.cpp
A clang/test/AST/ByteCode/cond.cpp
A clang/test/AST/ByteCode/const-eval.c
A clang/test/AST/ByteCode/const-fpfeatures.cpp
A clang/test/AST/ByteCode/const-temporaries.cpp
A clang/test/AST/ByteCode/constexpr-frame-describe.cpp
A clang/test/AST/ByteCode/constexpr-nqueens.cpp
A clang/test/AST/ByteCode/constexpr-subobj-initialization.cpp
A clang/test/AST/ByteCode/constexpr-vectors.cpp
A clang/test/AST/ByteCode/crash-GH49103-2.cpp
A clang/test/AST/ByteCode/cxx03.cpp
A clang/test/AST/ByteCode/cxx11-pedantic.cpp
A clang/test/AST/ByteCode/cxx11.cpp
A clang/test/AST/ByteCode/cxx17.cpp
A clang/test/AST/ByteCode/cxx20.cpp
A clang/test/AST/ByteCode/cxx23.cpp
A clang/test/AST/ByteCode/cxx26.cpp
A clang/test/AST/ByteCode/cxx2a.cpp
A clang/test/AST/ByteCode/cxx98.cpp
A clang/test/AST/ByteCode/depth-limit.cpp
A clang/test/AST/ByteCode/depth-limit2.cpp
A clang/test/AST/ByteCode/enums-targets.cpp
A clang/test/AST/ByteCode/enums.cpp
A clang/test/AST/ByteCode/eval-order.cpp
A clang/test/AST/ByteCode/floats.cpp
A clang/test/AST/ByteCode/functions.cpp
A clang/test/AST/ByteCode/hlsl.hlsl
A clang/test/AST/ByteCode/if.cpp
A clang/test/AST/ByteCode/intap.cpp
A clang/test/AST/ByteCode/invalid.cpp
A clang/test/AST/ByteCode/lambda.cpp
A clang/test/AST/ByteCode/lifetimes.cpp
A clang/test/AST/ByteCode/literals.cpp
A clang/test/AST/ByteCode/loops.cpp
A clang/test/AST/ByteCode/memberpointers.cpp
A clang/test/AST/ByteCode/ms.cpp
A clang/test/AST/ByteCode/mutable.cpp
A clang/test/AST/ByteCode/new-delete.cpp
A clang/test/AST/ByteCode/nullable.cpp
A clang/test/AST/ByteCode/objc.mm
A clang/test/AST/ByteCode/opencl.cl
A clang/test/AST/ByteCode/pointer-addition.c
A clang/test/AST/ByteCode/records.cpp
A clang/test/AST/ByteCode/references.cpp
A clang/test/AST/ByteCode/shifts.cpp
A clang/test/AST/ByteCode/spaceship.cpp
A clang/test/AST/ByteCode/switch.cpp
A clang/test/AST/ByteCode/sycl.cpp
A clang/test/AST/ByteCode/unions.cpp
A clang/test/AST/ByteCode/vectors.cpp
A clang/test/AST/ByteCode/weak.cpp
A clang/test/AST/HLSL/OutArgExpr.hlsl
M clang/test/AST/HLSL/RWBuffer-AST.hlsl
A clang/test/AST/HLSL/WaveSize.hlsl
M clang/test/AST/HLSL/ast-dump-comment-cbuffe-tbufferr.hlsl
M clang/test/AST/HLSL/cbuffer_tbuffer.hlsl
M clang/test/AST/HLSL/packoffset.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
M clang/test/AST/HLSL/resource_binding_attr.hlsl
R clang/test/AST/Interp/arrays.cpp
R clang/test/AST/Interp/atomic.c
R clang/test/AST/Interp/atomic.cpp
R clang/test/AST/Interp/bitfields.cpp
R clang/test/AST/Interp/builtin-align-cxx.cpp
R clang/test/AST/Interp/builtin-constant-p.cpp
R clang/test/AST/Interp/builtin-functions.cpp
R clang/test/AST/Interp/builtins.cpp
R clang/test/AST/Interp/c.c
R clang/test/AST/Interp/c23.c
R clang/test/AST/Interp/codegen.cpp
R clang/test/AST/Interp/comma.cpp
R clang/test/AST/Interp/complex.c
R clang/test/AST/Interp/complex.cpp
R clang/test/AST/Interp/cond.cpp
R clang/test/AST/Interp/const-eval.c
R clang/test/AST/Interp/const-fpfeatures.cpp
R clang/test/AST/Interp/const-temporaries.cpp
R clang/test/AST/Interp/constexpr-frame-describe.cpp
R clang/test/AST/Interp/constexpr-nqueens.cpp
R clang/test/AST/Interp/constexpr-subobj-initialization.cpp
R clang/test/AST/Interp/crash-GH49103-2.cpp
R clang/test/AST/Interp/cxx03.cpp
R clang/test/AST/Interp/cxx11.cpp
R clang/test/AST/Interp/cxx17.cpp
R clang/test/AST/Interp/cxx20.cpp
R clang/test/AST/Interp/cxx23.cpp
R clang/test/AST/Interp/cxx26.cpp
R clang/test/AST/Interp/cxx2a.cpp
R clang/test/AST/Interp/cxx98.cpp
R clang/test/AST/Interp/depth-limit.cpp
R clang/test/AST/Interp/depth-limit2.cpp
R clang/test/AST/Interp/enums-targets.cpp
R clang/test/AST/Interp/enums.cpp
R clang/test/AST/Interp/eval-order.cpp
R clang/test/AST/Interp/floats.cpp
R clang/test/AST/Interp/functions.cpp
R clang/test/AST/Interp/hlsl.hlsl
R clang/test/AST/Interp/if.cpp
R clang/test/AST/Interp/intap.cpp
R clang/test/AST/Interp/invalid.cpp
R clang/test/AST/Interp/lambda.cpp
R clang/test/AST/Interp/lifetimes.cpp
R clang/test/AST/Interp/literals.cpp
R clang/test/AST/Interp/loops.cpp
R clang/test/AST/Interp/memberpointers.cpp
R clang/test/AST/Interp/ms.cpp
R clang/test/AST/Interp/mutable.cpp
R clang/test/AST/Interp/new-delete.cpp
R clang/test/AST/Interp/nullable.cpp
R clang/test/AST/Interp/objc.mm
R clang/test/AST/Interp/opencl.cl
R clang/test/AST/Interp/pointer-addition.c
R clang/test/AST/Interp/records.cpp
R clang/test/AST/Interp/references.cpp
R clang/test/AST/Interp/shifts.cpp
R clang/test/AST/Interp/spaceship.cpp
R clang/test/AST/Interp/switch.cpp
R clang/test/AST/Interp/sycl.cpp
R clang/test/AST/Interp/unions.cpp
R clang/test/AST/Interp/vectors.cpp
R clang/test/AST/Interp/weak.cpp
M clang/test/AST/ast-dump-funcs-json.cpp
A clang/test/AST/cxx2c-variadic-friends.cpp
M clang/test/Analysis/analyzer-config.c
M clang/test/Analysis/asm.cpp
M clang/test/Analysis/block-in-critical-section-inheritance.cpp
A clang/test/Analysis/block-in-critical-section-nested-namespace.cpp
M clang/test/Analysis/builtin_signbit.cpp
M clang/test/Analysis/cfg.c
M clang/test/Analysis/cfg.cpp
M clang/test/Analysis/copy-elision.cpp
M clang/test/Analysis/ctor-array.cpp
M clang/test/Analysis/incorrect-checker-names.cpp
M clang/test/Analysis/loop-block-counts.c
M clang/test/Analysis/mmap-writeexec.c
M clang/test/Analysis/nullability.c
M clang/test/Analysis/nullability.mm
M clang/test/Analysis/nullptr.cpp
M clang/test/Analysis/stack-addr-ps.c
M clang/test/Analysis/stack-addr-ps.cpp
M clang/test/Analysis/stack-capture-leak-no-arc.mm
M clang/test/Analysis/stackaddrleak.c
M clang/test/Analysis/taint-generic.c
M clang/test/CXX/basic/basic.start/basic.start.main/p3.cpp
M clang/test/CXX/class/class.compare/class.compare.default/p1.cpp
M clang/test/CXX/drs/cwg14xx.cpp
A clang/test/CXX/drs/cwg1818.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg19xx.cpp
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg20xx.cpp
M clang/test/CXX/drs/cwg23xx.cpp
M clang/test/CXX/drs/cwg24xx.cpp
M clang/test/CXX/drs/cwg25xx.cpp
M clang/test/CXX/drs/cwg27xx.cpp
A clang/test/CXX/drs/cwg29xx.cpp
M clang/test/CXX/drs/cwg3xx.cpp
A clang/test/CXX/drs/cwg563.cpp
M clang/test/CXX/drs/cwg5xx.cpp
A clang/test/CXX/drs/cwg722.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/expr/expr.const/p2-0x.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.nontype/p1-11.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.normal/p1.cpp
M clang/test/CXX/temp/temp.decls/temp.mem/p1.cpp
M clang/test/CXX/temp/temp.res/temp.local/p8.cpp
M clang/test/CodeCompletion/variadic-template.cpp
M clang/test/CodeGen/2005-01-02-ConstantInits.c
M clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
M clang/test/CodeGen/PowerPC/ppc-emmintrin.c
M clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
A clang/test/CodeGen/PowerPC/transparent_union.c
M clang/test/CodeGen/RISCV/riscv-sdata-module-flag.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vundefined.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg7e16.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg3ei16.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
A clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c
A clang/test/CodeGen/X86/avx10_2_512convert-builtins.c
A clang/test/CodeGen/X86/avx10_2bf16-builtins.c
A clang/test/CodeGen/X86/avx10_2convert-builtins.c
M clang/test/CodeGen/X86/avx512vlbw-builtins.c
M clang/test/CodeGen/X86/cmpccxadd-builtins.c
A clang/test/CodeGen/X86/strictfp_patterns.c
M clang/test/CodeGen/X86/x86-atomic-double.c
M clang/test/CodeGen/X86/x86-atomic-long_double.c
A clang/test/CodeGen/X86/x86-intrinsics-imm.c
M clang/test/CodeGen/aarch64-elf-pauthabi.c
A clang/test/CodeGen/aarch64-neon-luti.c
A clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_faminmax.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c
A clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_faminmax.c
A clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_luti.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_loads.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_store.c
M clang/test/CodeGen/aarch64-targetattr.c
R clang/test/CodeGen/arm-neon-range-checks.c
M clang/test/CodeGen/attr-counted-by.c
A clang/test/CodeGen/bit-int-ubsan.c
A clang/test/CodeGen/bpf-attr-bpf-fastcall-1.c
M clang/test/CodeGen/builtin-cpu-supports.c
M clang/test/CodeGen/builtins-nvptx.c
M clang/test/CodeGen/builtins-wasm.c
M clang/test/CodeGen/catch-nullptr-and-nonzero-offset-when-nullptr-is-defined.c
M clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
M clang/test/CodeGen/catch-pointer-overflow-volatile.c
M clang/test/CodeGen/catch-pointer-overflow.c
M clang/test/CodeGen/compound-literal.c
M clang/test/CodeGen/ext-int.c
A clang/test/CodeGen/ffp-contract-fast-honor-pramga-option.cpp
A clang/test/CodeGen/ffp-contract-fhp-pragma-override.cpp
M clang/test/CodeGen/ffp-model.c
M clang/test/CodeGen/fp-reassoc-pragma.cpp
M clang/test/CodeGen/fp-reciprocal-pragma.cpp
M clang/test/CodeGen/hexagon-brev-ld-ptr-incdec.c
M clang/test/CodeGen/ifunc.c
A clang/test/CodeGen/ignore-overflow-pattern-false-pos.c
A clang/test/CodeGen/ignore-overflow-pattern.c
M clang/test/CodeGen/integer-overflow.c
M clang/test/CodeGen/kcfi-normalize.c
M clang/test/CodeGen/ms-intrinsics.c
M clang/test/CodeGen/ms-mixed-ptr-sizes.c
M clang/test/CodeGen/pgo-force-function-attrs.ll
A clang/test/CodeGen/rtsan_attribute_inserted.c
A clang/test/CodeGen/rtsan_entry_exit_insertion.c
A clang/test/CodeGen/rtsan_no_attribute_sanitizer_disabled.c
M clang/test/CodeGen/sanitize-ignorelist-mainfile.c
M clang/test/CodeGen/tls-maxalign-modflag.c
M clang/test/CodeGen/ubsan-pointer-overflow.m
M clang/test/CodeGen/vla.c
M clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
M clang/test/CodeGenCUDA/kernel-args.cu
A clang/test/CodeGenCXX/GH106182.cpp
M clang/test/CodeGenCXX/always_destroy.cpp
M clang/test/CodeGenCXX/amdgpu-kernel-arg-pointer-type.cpp
M clang/test/CodeGenCXX/attr-likelihood-iteration-stmt.cpp
M clang/test/CodeGenCXX/attr-no-destroy-d54344.cpp
M clang/test/CodeGenCXX/cxx2b-consteval-if.cpp
M clang/test/CodeGenCXX/debug-info-lambda-this.cpp
M clang/test/CodeGenCXX/for-range.cpp
A clang/test/CodeGenCXX/mangle-ms-auto-return.cpp
M clang/test/CodeGenCXX/mangle-ms-auto-templates-memptrs.cpp
M clang/test/CodeGenCXX/mangle-ms-auto-templates-nullptr.cpp
M clang/test/CodeGenCXX/mangle-ms-auto-templates.cpp
M clang/test/CodeGenCXX/microsoft-abi-template-static-init.cpp
M clang/test/CodeGenCXX/pr45964-decomp-transform.cpp
M clang/test/CodeGenCXX/vla.cpp
M clang/test/CodeGenCXX/vtable-available-externally.cpp
M clang/test/CodeGenCXX/windows-itanium-init-guard.cpp
A clang/test/CodeGenCoroutines/coro-dwarf-O2.cpp
A clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/buffer-array-operator.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl
M clang/test/CodeGenHLSL/builtins/all.hlsl
M clang/test/CodeGenHLSL/builtins/any.hlsl
M clang/test/CodeGenHLSL/builtins/dot-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/dot.hlsl
M clang/test/CodeGenHLSL/builtins/frac.hlsl
M clang/test/CodeGenHLSL/builtins/lerp.hlsl
M clang/test/CodeGenHLSL/builtins/normalize.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
A clang/test/CodeGenHLSL/builtins/saturate.hlsl
A clang/test/CodeGenHLSL/builtins/wave_is_first_lane.hlsl
A clang/test/CodeGenHLSL/default_validator_version.hlsl
A clang/test/CodeGenHLSL/implicit-norecurse-attrib.hlsl
M clang/test/CodeGenHLSL/semantics/DispatchThreadID.hlsl
A clang/test/CodeGenHLSL/static-local-ctor.hlsl
M clang/test/CodeGenHLSL/this-assignment-overload.hlsl
M clang/test/CodeGenHLSL/this-assignment.hlsl
M clang/test/CodeGenOpenCL/atomics-cas-remarks-gfx90a.cl
M clang/test/CodeGenOpenCL/atomics-unsafe-hw-remarks-gfx90a.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-param-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx12.cl
M clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx8.cl
M clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx90a.cl
M clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx940.cl
M clang/test/CodeGenSYCL/address-space-deduction.cpp
A clang/test/Driver/Inputs/MacOSX15.1.sdk/SDKSettings.json
M clang/test/Driver/Ofast.c
A clang/test/Driver/aarch64-negative-modifiers-for-default-features.c
A clang/test/Driver/aix-print-runtime-dir.c
M clang/test/Driver/arm-sb.c
M clang/test/Driver/arm-target-as-mimplicit-it.s
A clang/test/Driver/baremetal-multilib-custom-error.yaml
M clang/test/Driver/clang_f_opts.c
M clang/test/Driver/crel.c
A clang/test/Driver/cxx-static-destructors.cpp
M clang/test/Driver/darwin-builtin-modules.c
M clang/test/Driver/debug-options-as.c
M clang/test/Driver/debug-options.c
M clang/test/Driver/flags.c
M clang/test/Driver/fp-model.c
M clang/test/Driver/fsanitize.c
M clang/test/Driver/fuchsia.c
A clang/test/Driver/heinous-gnu-extensions.c
M clang/test/Driver/hip-toolchain-rdc.hip
A clang/test/Driver/mips-msa.c
A clang/test/Driver/mmapsyms.c
M clang/test/Driver/msse2avx.c
M clang/test/Driver/offload-packager.c
M clang/test/Driver/ohos.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/ps4-ps5-toolchain.c
M clang/test/Driver/ps4-sdk-root.c
M clang/test/Driver/ps5-linker.c
M clang/test/Driver/ps5-sdk-root.c
M clang/test/Driver/relax.c
M clang/test/Driver/riscv-cpus.c
R clang/test/Driver/riscv-sdata-warning.c
A clang/test/Driver/riscv-sdata.c
A clang/test/Driver/sparc-fix.c
M clang/test/Driver/sparc-target-features.c
M clang/test/Driver/wasm-features.c
M clang/test/ExtractAPI/anonymous_record_no_typedef.c
A clang/test/ExtractAPI/attributed-typedef.m
M clang/test/ExtractAPI/bool.c
M clang/test/ExtractAPI/emit-symbol-graph/multi_file.c
M clang/test/ExtractAPI/emit-symbol-graph/single_file.c
A clang/test/ExtractAPI/inherited_availability.m
M clang/test/ExtractAPI/macros.c
A clang/test/ExtractAPI/platform-serialization.c
A clang/test/ExtractAPI/submodule-macro.m
M clang/test/FixIt/fixit-availability-maccatalyst.m
M clang/test/FixIt/fixit-availability.mm
M clang/test/Headers/__clang_hip_math.hip
A clang/test/Headers/gpu_disabled_math.cpp
M clang/test/Headers/wasm.c
M clang/test/Index/complete-call.cpp
A clang/test/Interpreter/assigment-with-implicit-ctor.cpp
A clang/test/Interpreter/preprocessor.cpp
M clang/test/Lexer/cxx-features.cpp
A clang/test/Lexer/has_feature_realtime_sanitizer.cpp
A clang/test/Misc/cc1as-mmapsyms.c
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
R clang/test/Misc/target-invalid-cpu-note.c
A clang/test/Misc/target-invalid-cpu-note/aarch64.c
A clang/test/Misc/target-invalid-cpu-note/amdgcn.c
A clang/test/Misc/target-invalid-cpu-note/arm.c
A clang/test/Misc/target-invalid-cpu-note/avr.c
A clang/test/Misc/target-invalid-cpu-note/bpf.c
A clang/test/Misc/target-invalid-cpu-note/hexagon.c
A clang/test/Misc/target-invalid-cpu-note/lanai.c
A clang/test/Misc/target-invalid-cpu-note/mips.c
A clang/test/Misc/target-invalid-cpu-note/nvptx.c
A clang/test/Misc/target-invalid-cpu-note/powerpc.c
A clang/test/Misc/target-invalid-cpu-note/r600.c
A clang/test/Misc/target-invalid-cpu-note/riscv.c
A clang/test/Misc/target-invalid-cpu-note/sparc.c
A clang/test/Misc/target-invalid-cpu-note/systemz.c
A clang/test/Misc/target-invalid-cpu-note/wasm.c
A clang/test/Misc/target-invalid-cpu-note/x86.c
M clang/test/Misc/warning-flags.c
A clang/test/Modules/compare-file-size.py
M clang/test/Modules/enum-codegen.cpp
M clang/test/Modules/merge-using-decls.cpp
A clang/test/Modules/pr102721.cppm
A clang/test/Modules/pr106483.cppm
M clang/test/Modules/reduced-bmi-size.cppm
A clang/test/Modules/skip-func-def-odr-with-pch.cppm
A clang/test/Modules/warn-duplicated-decls-in-module-units.cppm
M clang/test/OpenMP/bug60602.cpp
M clang/test/OpenMP/declare_mapper_codegen.cpp
M clang/test/OpenMP/distribute_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/distribute_simd_codegen.cpp
M clang/test/OpenMP/for_linear_codegen.cpp
M clang/test/OpenMP/for_reduction_codegen.cpp
M clang/test/OpenMP/for_reduction_codegen_UDR.cpp
M clang/test/OpenMP/for_reduction_task_codegen.cpp
M clang/test/OpenMP/for_scan_codegen.cpp
M clang/test/OpenMP/for_simd_scan_codegen.cpp
M clang/test/OpenMP/irbuilder_for_iterator.cpp
M clang/test/OpenMP/irbuilder_for_rangefor.cpp
M clang/test/OpenMP/irbuilder_for_unsigned.c
M clang/test/OpenMP/irbuilder_for_unsigned_auto.c
M clang/test/OpenMP/irbuilder_for_unsigned_down.c
M clang/test/OpenMP/irbuilder_for_unsigned_dynamic.c
M clang/test/OpenMP/irbuilder_for_unsigned_dynamic_chunked.c
M clang/test/OpenMP/irbuilder_for_unsigned_runtime.c
M clang/test/OpenMP/irbuilder_for_unsigned_static_chunked.c
A clang/test/OpenMP/loop_collapse_1.c
A clang/test/OpenMP/loop_collapse_2.cpp
M clang/test/OpenMP/map_struct_ordering.cpp
M clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
M clang/test/OpenMP/master_taskloop_reduction_codegen.cpp
M clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
M clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp
M clang/test/OpenMP/nvptx_allocate_codegen.cpp
M clang/test/OpenMP/ordered_codegen.cpp
M clang/test/OpenMP/parallel_for_codegen.cpp
M clang/test/OpenMP/parallel_for_linear_codegen.cpp
M clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/parallel_for_scan_codegen.cpp
M clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
M clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
M clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp
M clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp
M clang/test/OpenMP/parallel_reduction_codegen.cpp
M clang/test/OpenMP/parallel_reduction_task_codegen.cpp
M clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
M clang/test/OpenMP/reduction_implicit_map.cpp
M clang/test/OpenMP/sections_reduction_task_codegen.cpp
M clang/test/OpenMP/target_data_use_device_addr_codegen.cpp
M clang/test/OpenMP/target_data_use_device_ptr_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_codegen.cpp
M clang/test/OpenMP/target_in_reduction_codegen.cpp
M clang/test/OpenMP/target_is_device_ptr_codegen.cpp
M clang/test/OpenMP/target_map_both_pointer_pointee_codegen.cpp
M clang/test/OpenMP/target_map_codegen_01.cpp
M clang/test/OpenMP/target_map_codegen_21.cpp
M clang/test/OpenMP/target_map_codegen_27.cpp
M clang/test/OpenMP/target_map_codegen_28.cpp
M clang/test/OpenMP/target_map_codegen_29.cpp
M clang/test/OpenMP/target_map_deref_array_codegen.cpp
M clang/test/OpenMP/target_map_member_expr_array_section_codegen.cpp
M clang/test/OpenMP/target_map_member_expr_codegen.cpp
M clang/test/OpenMP/target_map_nest_defalut_mapper_codegen.cpp
M clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
M clang/test/OpenMP/target_task_affinity_codegen.cpp
M clang/test/OpenMP/target_teams_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/target_update_codegen.cpp
M clang/test/OpenMP/task_codegen.c
M clang/test/OpenMP/task_codegen.cpp
M clang/test/OpenMP/task_in_reduction_codegen.cpp
M clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp
M clang/test/OpenMP/taskloop_in_reduction_codegen.cpp
M clang/test/OpenMP/taskloop_reduction_codegen.cpp
M clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp
M clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/Parser/attr-order.cpp
M clang/test/Parser/cxx11-user-defined-literals.cpp
A clang/test/Parser/cxx2c-variadic-friends-ext-diags.cpp
A clang/test/Parser/cxx2c-variadic-friends.cpp
A clang/test/Parser/friend-concept.cpp
A clang/test/Parser/function-parameter-limit.cpp
M clang/test/ParserHLSL/hlsl_is_rov_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_handle_attrs.hlsl
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Preprocessor/bpf-predefined-macros.c
M clang/test/Preprocessor/init-ppc.c
M clang/test/Preprocessor/init-ppc64.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Preprocessor/wasm-target-features.c
R clang/test/Sema/aarch64-neon-bf16-ranges.c
R clang/test/Sema/aarch64-neon-fp16-ranges.c
A clang/test/Sema/aarch64-neon-immediate-ranges/bfloat16.c
A clang/test/Sema/aarch64-neon-immediate-ranges/conversions.c
A clang/test/Sema/aarch64-neon-immediate-ranges/copy-vector-lane.c
A clang/test/Sema/aarch64-neon-immediate-ranges/dotprod.c
A clang/test/Sema/aarch64-neon-immediate-ranges/extract-elt-from-vector.c
A clang/test/Sema/aarch64-neon-immediate-ranges/extract-vector-from-vectors.c
A clang/test/Sema/aarch64-neon-immediate-ranges/fp16-scalar.c
A clang/test/Sema/aarch64-neon-immediate-ranges/fp16-v84.c
A clang/test/Sema/aarch64-neon-immediate-ranges/fp16-vector.c
A clang/test/Sema/aarch64-neon-immediate-ranges/fused-multiply-accumulate.c
A clang/test/Sema/aarch64-neon-immediate-ranges/luti.c
A clang/test/Sema/aarch64-neon-immediate-ranges/matrix-multiplication.c
A clang/test/Sema/aarch64-neon-immediate-ranges/multiply-extended.c
A clang/test/Sema/aarch64-neon-immediate-ranges/saturating-multiply-accumulate.c
A clang/test/Sema/aarch64-neon-immediate-ranges/saturating-multiply-by-scalar-and-widen.c
A clang/test/Sema/aarch64-neon-immediate-ranges/set-lanes-to-value.c
A clang/test/Sema/aarch64-neon-immediate-ranges/set-vector-lane.c
A clang/test/Sema/aarch64-neon-immediate-ranges/sqrdmlah-ranges.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vcmla.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-load.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-multiply-accumulate-by-scalar.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-multiply-by-scalar-and-widen.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-multiply-by-scalar.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-multiply-subtract-by-scalar.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-left.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-right.c
A clang/test/Sema/aarch64-neon-immediate-ranges/vector-store.c
R clang/test/Sema/aarch64-neon-ranges.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_imm_lane.cpp
A clang/test/Sema/attr-btf_type_tag.cpp
M clang/test/Sema/block-misc.c
M clang/test/Sema/block-return.c
A clang/test/Sema/bpf-attr-bpf-fastcall.c
M clang/test/Sema/builtin-unary-fp.c
M clang/test/Sema/c2x-nodiscard.c
M clang/test/Sema/constant-builtins-2.c
A clang/test/Sema/format-pointer.c
M clang/test/Sema/format-strings-pedantic.c
M clang/test/Sema/heinous-extensions-off.c
M clang/test/Sema/heinous-extensions-on.c
M clang/test/Sema/pre-c2x-compat.c
M clang/test/Sema/static-assert.c
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
A clang/test/SemaCXX/GH106182.cpp
M clang/test/SemaCXX/MicrosoftExtensions.cpp
M clang/test/SemaCXX/attr-annotate.cpp
M clang/test/SemaCXX/attr-lifetimebound.cpp
A clang/test/SemaCXX/builtin-is-within-lifetime.cpp
M clang/test/SemaCXX/builtins.cpp
M clang/test/SemaCXX/constant-expression-cxx11.cpp
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
A clang/test/SemaCXX/consteval-builtin.cpp
M clang/test/SemaCXX/consteval-cleanup.cpp
M clang/test/SemaCXX/constexpr-vectors.cpp
M clang/test/SemaCXX/cxx1z-decomposition.cpp
M clang/test/SemaCXX/cxx20-default-compare.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
M clang/test/SemaCXX/cxx2a-consteval.cpp
M clang/test/SemaCXX/cxx2a-constexpr-dynalloc.cpp
M clang/test/SemaCXX/cxx2a-explicit-bool.cpp
M clang/test/SemaCXX/cxx2a-template-lambdas.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
A clang/test/SemaCXX/cxx2c-constexpr-placement-new.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
A clang/test/SemaCXX/cxx2c-variadic-friends.cpp
M clang/test/SemaCXX/extern-c.cpp
M clang/test/SemaCXX/gh102293.cpp
M clang/test/SemaCXX/matrix-index-operator-sign-conversion.cpp
M clang/test/SemaCXX/no_destroy.cpp
M clang/test/SemaCXX/source_location.cpp
A clang/test/SemaCXX/static-assert-ext.cpp
M clang/test/SemaCXX/sugar-common-types.cpp
M clang/test/SemaCXX/sugared-auto.cpp
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaCXX/vector.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
A clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions-inline-namespace.cpp
A clang/test/SemaCXX/warn-unsafe-buffer-usage-libc-functions.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-test-unreachable.cpp
M clang/test/SemaHLSL/BuiltIns/normalize-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/saturate-errors.hlsl
A clang/test/SemaHLSL/Language/OutputParameters.hlsl
A clang/test/SemaHLSL/Language/TemplateOutArg.hlsl
A clang/test/SemaHLSL/Types/Traits/IsIntangibleType.hlsl
A clang/test/SemaHLSL/Types/Traits/IsIntangibleTypeErrors.hlsl
A clang/test/SemaHLSL/Types/Traits/ScalarizedLayoutCompatible.hlsl
A clang/test/SemaHLSL/Types/Traits/ScalarizedLayoutCompatibleErrors.hlsl
A clang/test/SemaHLSL/Types/typedefs.hlsl
A clang/test/SemaHLSL/WaveSize-invalid-param.hlsl
A clang/test/SemaHLSL/WaveSize-invalid-profiles.hlsl
A clang/test/SemaHLSL/WaveSize-sm6.6-6.5.hlsl
M clang/test/SemaHLSL/parameter_modifiers.hlsl
M clang/test/SemaHLSL/parameter_modifiers_ast.hlsl
M clang/test/SemaHLSL/resource_binding_attr_error.hlsl
A clang/test/SemaHLSL/resource_binding_attr_error_basic.hlsl
A clang/test/SemaHLSL/resource_binding_attr_error_other.hlsl
A clang/test/SemaHLSL/resource_binding_attr_error_resource.hlsl
A clang/test/SemaHLSL/resource_binding_attr_error_silence_diags.hlsl
A clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
M clang/test/SemaObjC/non-trivial-c-union.m
A clang/test/SemaOpenMP/gh104810.cpp
A clang/test/SemaTemplate/GH18291.cpp
M clang/test/SemaTemplate/alias-template-with-lambdas.cpp
M clang/test/SemaTemplate/concepts-friends.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/cwg2398.cpp
M clang/test/SemaTemplate/default-arguments.cpp
R clang/test/SemaTemplate/default-parm-init.cpp
A clang/test/SemaTemplate/explicit-instantiation-cxx20.cpp
M clang/test/SemaTemplate/temp_arg_nontype.cpp
M clang/test/SemaTemplate/temp_arg_type.cpp
M clang/test/SemaTemplate/temp_explicit.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/c-arcmt-test/c-arcmt-test.c
M clang/tools/c-index-test/c-index-test.c
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/clang-format/clang-format-diff.py
M clang/tools/clang-format/clang-format-sublime.py
M clang/tools/clang-format/clang-format-test.el
M clang/tools/clang-format/clang-format.el
M clang/tools/clang-format/clang-format.py
M clang/tools/clang-format/git-clang-format
M clang/tools/clang-format/git-clang-format.bat
M clang/tools/clang-repl/CMakeLists.txt
M clang/tools/driver/CMakeLists.txt
M clang/tools/driver/cc1as_main.cpp
M clang/tools/driver/driver.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M clang/tools/libclang/CXSourceLocation.cpp
M clang/tools/libclang/CXType.cpp
M clang/tools/libclang/libclang.map
M clang/tools/scan-build-py/CMakeLists.txt
M clang/tools/scan-build-py/tests/functional/cases/test_create_cdb.py
M clang/tools/scan-build/man/scan-build.1
M clang/tools/scan-view/share/startfile.py
M clang/unittests/AST/ASTImporterTest.cpp
A clang/unittests/AST/ByteCode/CMakeLists.txt
A clang/unittests/AST/ByteCode/Descriptor.cpp
A clang/unittests/AST/ByteCode/toAPValue.cpp
M clang/unittests/AST/CMakeLists.txt
R clang/unittests/AST/Interp/CMakeLists.txt
R clang/unittests/AST/Interp/Descriptor.cpp
R clang/unittests/AST/Interp/toAPValue.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
M clang/unittests/Analysis/FlowSensitive/ASTOpsTest.cpp
M clang/unittests/Basic/SourceManagerTest.cpp
M clang/unittests/Driver/GCCVersionTest.cpp
M clang/unittests/Driver/MultilibBuilderTest.cpp
M clang/unittests/Driver/MultilibTest.cpp
M clang/unittests/Driver/SimpleDiagnosticConsumer.h
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestComments.cpp
M clang/unittests/Format/FormatTestJS.cpp
M clang/unittests/Format/FormatTestObjC.cpp
M clang/unittests/Format/QualifierFixerTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Rewrite/CMakeLists.txt
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
M clang/utils/TableGen/ClangSyntaxEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M clang/utils/creduce-clang-crash.py
M clang/www/c_status.html
M clang/www/cxx_dr_status.html
M clang/www/cxx_status.html
M clang/www/make_cxx_dr_status
M cmake/Modules/HandleCompilerRT.cmake
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/include/CMakeLists.txt
A compiler-rt/include/sanitizer/rtsan_interface.h
M compiler-rt/lib/CMakeLists.txt
M compiler-rt/lib/asan/asan_allocator.h
M compiler-rt/lib/asan/asan_poisoning.cpp
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/builtins/aarch64/sme-abi-init.c
M compiler-rt/lib/builtins/cpu_model/aarch64.c
M compiler-rt/lib/builtins/cpu_model/riscv.c
M compiler-rt/lib/builtins/divsc3.c
M compiler-rt/lib/builtins/fp_lib.h
M compiler-rt/lib/builtins/int_math.h
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp
M compiler-rt/lib/ctx_profile/CtxInstrProfiling.h
M compiler-rt/lib/fuzzer/FuzzerUtilFuchsia.cpp
M compiler-rt/lib/hwasan/scripts/hwasan_symbolize
M compiler-rt/lib/interception/interception.h
M compiler-rt/lib/interception/interception_type_test.cpp
M compiler-rt/lib/nsan/nsan.cpp
M compiler-rt/lib/nsan/nsan_flags.inc
M compiler-rt/lib/nsan/nsan_interceptors.cpp
M compiler-rt/lib/orc/macho_platform.cpp
M compiler-rt/lib/profile/GCDAProfiling.c
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformFuchsia.c
M compiler-rt/lib/profile/InstrProfilingUtil.c
M compiler-rt/lib/profile/InstrProfilingUtil.h
M compiler-rt/lib/rtsan/CMakeLists.txt
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan.h
M compiler-rt/lib/rtsan/rtsan_context.cpp
M compiler-rt/lib/rtsan/rtsan_context.h
A compiler-rt/lib/rtsan/rtsan_flags.cpp
A compiler-rt/lib/rtsan/rtsan_flags.h
A compiler-rt/lib/rtsan/rtsan_flags.inc
M compiler-rt/lib/rtsan/rtsan_interceptors.cpp
M compiler-rt/lib/rtsan/rtsan_stack.cpp
M compiler-rt/lib/rtsan/rtsan_stack.h
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
M compiler-rt/lib/rtsan/tests/rtsan_test_context.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_functional.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common.h
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer.h
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_tls_get_addr.cpp
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/common.cpp
M compiler-rt/lib/scudo/standalone/common.h
M compiler-rt/lib/scudo/standalone/linux.cpp
M compiler-rt/lib/scudo/standalone/platform.h
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/primary64.h
M compiler-rt/lib/scudo/standalone/release.h
M compiler-rt/lib/scudo/standalone/secondary.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/timing_test.cpp
M compiler-rt/lib/ubsan/ubsan_value.cpp
M compiler-rt/lib/ubsan/ubsan_value.h
M compiler-rt/test/asan/TestCases/Darwin/cstring_section.c
M compiler-rt/test/asan/TestCases/Linux/allocator_oom_test.cpp
M compiler-rt/test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c
M compiler-rt/test/asan/TestCases/Posix/deep_call_stack.cpp
M compiler-rt/test/asan/TestCases/Posix/high-address-dereference.c
A compiler-rt/test/asan/TestCases/initialization-bug-no-global.cpp
M compiler-rt/test/builtins/Unit/divsc3_test.c
M compiler-rt/test/fuzzer/afl-driver-close-fd-mask.test
M compiler-rt/test/fuzzer/afl-driver-stderr.test
M compiler-rt/test/fuzzer/features_dir.test
M compiler-rt/test/fuzzer/focus-function.test
M compiler-rt/test/fuzzer/merge-posix.test
M compiler-rt/test/fuzzer/out-of-process-fuzz.test
M compiler-rt/test/fuzzer/ulimit.test
M compiler-rt/test/hwasan/TestCases/hwasan_symbolize.cpp
A compiler-rt/test/hwasan/TestCases/hwasan_symbolize_stack_overflow.cpp
M compiler-rt/test/hwasan/TestCases/print-memory-usage.c
M compiler-rt/test/lsan/TestCases/create_thread_leak.cpp
M compiler-rt/test/metadata/uar.cpp
M compiler-rt/test/msan/Linux/reexec_unlimited_stack.cpp
M compiler-rt/test/nsan/Posix/tls_reuse.c
A compiler-rt/test/nsan/intercep_strsep.cpp
A compiler-rt/test/nsan/nan.cpp
A compiler-rt/test/nsan/softmax.cpp
A compiler-rt/test/nsan/stable_sort.cpp
M compiler-rt/test/nsan/sum.cpp
A compiler-rt/test/nsan/swap.cpp
A compiler-rt/test/nsan/vec_sqrt.cpp
A compiler-rt/test/nsan/vec_sqrt_ext.cpp
A compiler-rt/test/profile/AIX/gcov-dlopen-dlclose.test
M compiler-rt/test/profile/ContinuousSyncMode/darwin-proof-of-concept.c
M compiler-rt/test/profile/ContinuousSyncMode/runtime-counter-relocation.c
M compiler-rt/test/profile/ContinuousSyncMode/set-file-object.c
M compiler-rt/test/profile/Linux/counter_promo_for.c
M compiler-rt/test/profile/Linux/counter_promo_nest.c
M compiler-rt/test/profile/Linux/counter_promo_while.c
A compiler-rt/test/profile/Linux/instrprof-debug-info-correlate-debuginfod.c
M compiler-rt/test/profile/Linux/instrprof-debug-info-correlate.c
A compiler-rt/test/profile/Posix/instrprof-dlopen-norpath.test
A compiler-rt/test/profile/Posix/instrprof-fork.c
A compiler-rt/test/profile/instrprof-binary-correlate-debuginfod.c
M compiler-rt/test/profile/lit.cfg.py
M compiler-rt/test/rtsan/CMakeLists.txt
A compiler-rt/test/rtsan/basic.cpp
A compiler-rt/test/rtsan/disabler.cpp
A compiler-rt/test/rtsan/inactive.cpp
A compiler-rt/test/rtsan/unrecognized_flags.cpp
M compiler-rt/test/sanitizer_common/TestCases/Linux/prctl.cpp
M compiler-rt/test/sanitizer_common/TestCases/Linux/resize_tls_dynamic.cpp
M compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c
M compiler-rt/test/sanitizer_common/lit.common.cfg.py
A compiler-rt/test/ubsan/TestCases/Integer/bit-int-pass.c
A compiler-rt/test/ubsan/TestCases/Integer/bit-int.c
M compiler-rt/test/ubsan/TestCases/TypeCheck/vptr.cpp
M compiler-rt/www/index.html
M cross-project-tests/debuginfo-tests/dexter/dex/utils/Version.py
M cross-project-tests/intrinsic-header-tests/wasm_simd128.c
M flang/docs/OpenMP-declare-target.md
M flang/docs/OpenMP-descriptor-management.md
M flang/include/flang/Common/Fortran-features.h
M flang/include/flang/Evaluate/integer.h
M flang/include/flang/Evaluate/real.h
M flang/include/flang/Frontend/TargetOptions.h
A flang/include/flang/Lower/Cuda.h
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/CMakeLists.txt
M flang/include/flang/Optimizer/CodeGen/CGPasses.td
M flang/include/flang/Optimizer/CodeGen/CodeGen.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Dialect/FIRType.h
A flang/include/flang/Optimizer/OpenMP/CMakeLists.txt
A flang/include/flang/Optimizer/OpenMP/Passes.h
A flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/include/flang/Optimizer/Support/InternalNames.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Runtime/CUDA/allocator.h
M flang/include/flang/Runtime/cpp-type.h
M flang/include/flang/Runtime/descriptor.h
M flang/include/flang/Runtime/numeric.h
M flang/include/flang/Semantics/expression.h
M flang/include/flang/Semantics/semantics.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Tools/CLOptions.inc
M flang/include/flang/Tools/TargetSetup.h
M flang/lib/Evaluate/fold-real.cpp
M flang/lib/Evaluate/integer.cpp
M flang/lib/Evaluate/intrinsics-library.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/DirectivesCommon.h
M flang/lib/Lower/Mangler.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/Decomposer.cpp
M flang/lib/Lower/OpenMP/Decomposer.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Numeric.cpp
M flang/lib/Optimizer/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Dialect/FIRAttr.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
A flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
A flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
A flang/lib/Optimizer/OpenMP/MarkDeclareTarget.cpp
M flang/lib/Optimizer/Support/InternalNames.cpp
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/CompilerGeneratedNames.cpp
M flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
M flang/lib/Optimizer/Transforms/LoopVersioning.cpp
R flang/lib/Optimizer/Transforms/OMPFunctionFiltering.cpp
R flang/lib/Optimizer/Transforms/OMPMapInfoFinalization.cpp
R flang/lib/Optimizer/Transforms/OMPMarkDeclareTarget.cpp
M flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M flang/lib/Parser/io-parsers.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/provenance.cpp
M flang/lib/Semantics/canonicalize-acc.cpp
M flang/lib/Semantics/canonicalize-directives.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-cuda.h
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/check-directive-structure.h
M flang/lib/Semantics/check-io.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/definable.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/runtime-type-info.cpp
M flang/lib/Semantics/semantics.cpp
M flang/lib/Semantics/tools.cpp
M flang/module/__fortran_builtins.f90
M flang/module/ieee_arithmetic.f90
M flang/runtime/CUDA/CMakeLists.txt
M flang/runtime/CUDA/allocator.cpp
M flang/runtime/assign.cpp
M flang/runtime/copy.cpp
M flang/runtime/edit-input.cpp
M flang/runtime/exceptions.cpp
M flang/runtime/external-unit.cpp
M flang/runtime/numeric-templates.h
M flang/runtime/numeric.cpp
M flang/runtime/random.cpp
M flang/runtime/stop.cpp
M flang/runtime/time-intrinsic.cpp
R flang/test/Analysis/AliasAnalysis/alias-analysis-9.fir
A flang/test/Analysis/AliasAnalysis/ptr-component.fir
M flang/test/CMakeLists.txt
M flang/test/Driver/cuda-option.f90
A flang/test/Driver/fno-openmp.f90
M flang/test/Driver/fopenmp.f90
M flang/test/Driver/fveclib-codegen.f90
M flang/test/Driver/mlir-debug-pass-pipeline.f90
M flang/test/Driver/mlir-pass-pipeline.f90
A flang/test/Driver/mmlir-opts-vs-opts.f90
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M libcxx/include/__iterator/concepts.h
M libcxx/include/__iterator/iterator_traits.h
M libcxx/include/__iterator/projected.h
M libcxx/include/__iterator/wrap_iter.h
M libcxx/include/__math/copysign.h
M libcxx/include/__math/hypot.h
M libcxx/include/__math/remainder.h
M libcxx/include/__math/traits.h
M libcxx/include/__mdspan/extents.h
M libcxx/include/__mdspan/layout_left.h
M libcxx/include/__mdspan/layout_right.h
M libcxx/include/__mdspan/layout_stride.h
M libcxx/include/__memory/allocator.h
A libcxx/include/__memory/noexcept_move_assign_container.h
M libcxx/include/__memory/pointer_traits.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__memory/uses_allocator.h
M libcxx/include/__ostream/basic_ostream.h
M libcxx/include/__pstl/backends/default.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/include/__random/mersenne_twister_engine.h
M libcxx/include/__random/seed_seq.h
M libcxx/include/__random/subtract_with_carry_engine.h
M libcxx/include/__ranges/subrange.h
M libcxx/include/__string/constexpr_c_functions.h
M libcxx/include/__tuple/find_index.h
M libcxx/include/__tuple/make_tuple_types.h
M libcxx/include/__tuple/sfinae_helpers.h
M libcxx/include/__tuple/tuple_element.h
M libcxx/include/__tuple/tuple_indices.h
M libcxx/include/__tuple/tuple_like_ext.h
M libcxx/include/__tuple/tuple_like_no_subrange.h
M libcxx/include/__tuple/tuple_size.h
M libcxx/include/__type_traits/aligned_storage.h
M libcxx/include/__type_traits/aligned_union.h
M libcxx/include/__type_traits/alignment_of.h
M libcxx/include/__type_traits/datasizeof.h
M libcxx/include/__type_traits/desugars_to.h
M libcxx/include/__type_traits/extent.h
M libcxx/include/__type_traits/is_allocator.h
M libcxx/include/__type_traits/is_array.h
M libcxx/include/__type_traits/is_base_of.h
M libcxx/include/__type_traits/is_bounded_array.h
M libcxx/include/__type_traits/is_member_pointer.h
M libcxx/include/__type_traits/is_nothrow_destructible.h
M libcxx/include/__type_traits/is_null_pointer.h
M libcxx/include/__type_traits/is_swappable.h
M libcxx/include/__type_traits/is_trivially_copyable.h
M libcxx/include/__type_traits/is_trivially_lexicographically_comparable.h
M libcxx/include/__type_traits/is_void.h
M libcxx/include/__type_traits/make_unsigned.h
R libcxx/include/__type_traits/noexcept_move_assign_container.h
M libcxx/include/__type_traits/rank.h
M libcxx/include/__type_traits/remove_all_extents.h
M libcxx/include/__type_traits/remove_extent.h
M libcxx/include/__type_traits/result_of.h
M libcxx/include/__type_traits/type_list.h
M libcxx/include/__utility/in_place.h
M libcxx/include/__utility/pair.h
M libcxx/include/__utility/swap.h
M libcxx/include/any
M libcxx/include/array
M libcxx/include/cmath
M libcxx/include/complex
M libcxx/include/cstddef
M libcxx/include/cstdio
M libcxx/include/cstdlib
M libcxx/include/cstring
M libcxx/include/ctime
M libcxx/include/cuchar
M libcxx/include/cwchar
M libcxx/include/exception
M libcxx/include/experimental/__simd/reference.h
M libcxx/include/experimental/__simd/scalar.h
M libcxx/include/experimental/__simd/simd.h
M libcxx/include/experimental/__simd/simd_mask.h
M libcxx/include/experimental/__simd/vec_ext.h
M libcxx/include/forward_list
M libcxx/include/future
M libcxx/include/iosfwd
M libcxx/include/istream
M libcxx/include/list
M libcxx/include/module.modulemap
M libcxx/include/new
M libcxx/include/print
M libcxx/include/regex
M libcxx/include/set
M libcxx/include/span
M libcxx/include/string
M libcxx/include/string_view
M libcxx/include/syncstream
M libcxx/include/tuple
M libcxx/include/type_traits
M libcxx/include/typeinfo
M libcxx/include/unordered_map
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5-bogner
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/6ae3fc135c68...3e7a95c9bf96
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