[all-commits] [llvm/llvm-project] 4af249: Add usub_cond and usub_sat operations to atomicrmw...

[anjenner via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4af249fe6e81abd137c95bc25f5060ae305134ca
      https://github.com/llvm/llvm-project/commit/4af249fe6e81abd137c95bc25f5060ae305134ca
  Author: anjenner <161845516+anjenner at users.noreply.github.com>
  Date:   2024-09-06 (Fri, 06 Sep 2024)

  Changed paths:
    M llvm/bindings/ocaml/llvm/llvm.ml
    M llvm/bindings/ocaml/llvm/llvm.mli
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/docs/LangRef.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/AsmParser/LLToken.h
    M llvm/include/llvm/Bitcode/LLVMBitCodes.h
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/include/llvm/IR/Instructions.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
    M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
    M llvm/lib/CodeGen/AtomicExpandPass.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
    M llvm/lib/IR/Instructions.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Transforms/Utils/LowerAtomic.cpp
    M llvm/test/Assembler/atomic.ll
    M llvm/test/Bitcode/compatibility.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    A llvm/test/CodeGen/AArch64/atomicrmw-cond-sub-clamp.ll
    A llvm/test/CodeGen/ARM/atomicrmw-cond-sub-clamp.ll
    A llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll
    A llvm/test/CodeGen/LoongArch/atomicrmw-cond-sub-clamp.ll
    A llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
    A llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
    A llvm/test/CodeGen/VE/Scalar/atomicrmw-cond-sub-clamp.ll
    A llvm/test/CodeGen/WebAssembly/atomicrmw-cond-sub-clamp.ll
    A llvm/test/CodeGen/X86/atomicrmw-cond-sub-clamp.ll
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
    M llvm/test/TableGen/GlobalISelEmitter.td
    M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
    M mlir/test/Target/LLVMIR/Import/instructions.ll
    M mlir/test/Target/LLVMIR/llvmir.mlir

  Log Message:
  -----------
  Add usub_cond and usub_sat operations to atomicrmw (#105568)

These both perform conditional subtraction, returning the minuend and
zero respectively, if the difference is negative.



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