[all-commits] [llvm/llvm-project] bf57ec: [AArch64] Prevent generating tbl instruction inste...

[Igor Kirillov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bf57ecf06e688a716fc9ce47386228503fa02e47
      https://github.com/llvm/llvm-project/commit/bf57ecf06e688a716fc9ce47386228503fa02e47
  Author: Igor Kirillov <igor.kirillov at arm.com>
  Date:   2024-09-06 (Fri, 06 Sep 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/zext-to-tbl.ll

  Log Message:
  -----------
  [AArch64] Prevent generating tbl instruction instead of smull (#106375)

Generating tbl instruction for zext in an expression like: mul(zext(i8),
sext) is not optimal.
Instead, allowing later optimisations to generate smull(zext, sext)
would do some of the type extensions implicitly and be faster.



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