[all-commits] [llvm/llvm-project] 3d7295: [RISCV] Model dest EEW and fix peepholes not check...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3d729571fdc86a40218e5743d4386d7d8edc36ae
      https://github.com/llvm/llvm-project/commit/3d729571fdc86a40218e5743d4386d7d8edc36ae
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-05 (Thu, 05 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
    M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)

Previously for vector peepholes that fold based on VL, we checked if the
VLMAX is the same as a proxy to check that the EEWs were the same. This
only worked at LMUL >= 1 because the EMULs of the Src output and user's
input had to be the same because the register classes needed to match.

At fractional LMULs we would have incorrectly folded something like
this:

    %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, 4, 4 /* e16 */, 0
    %y:vr = PseudoVMV_V_V_MF8 $noreg, %x, 4, 3 /* e8 */, 0

This models the EEW of the destination operands of vector instructions
with a TSFlag, which is enough to fix the incorrect folding.

There's some overlap with the TargetOverlapConstraintType and
IsRVVWideningReduction. If we model the source operands as well we may
be able to subsume them.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications