[all-commits] [llvm/llvm-project] ba3c1e: [RISCV] Correct the scheduler class for FCVT_S_BF1...
Amir Ayupov via All-commits
all-commits at lists.llvm.org
Wed Sep 4 20:01:25 PDT 2024
Branch: refs/heads/users/aaupov/spr/bolt-add-pseudo-probe-inline-tree-to-yaml-profile
Home: https://github.com/llvm/llvm-project
Commit: ba3c1edcc8cf96206df259bd07001fa7ee9957cb
https://github.com/llvm/llvm-project/commit/ba3c1edcc8cf96206df259bd07001fa7ee9957cb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
Log Message:
-----------
[RISCV] Correct the scheduler class for FCVT_S_BF16. (#107028)
Use FCvtF16ToF32 instead of FCvtF32ToF16.
Commit: 9a1d14a8d26778a5d2d24928ba11cc557c2df24b
https://github.com/llvm/llvm-project/commit/9a1d14a8d26778a5d2d24928ba11cc557c2df24b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/FunctionImport.h
Log Message:
-----------
[LTO] Don't make unnecessary copies of ImportIDTable (#106998)
Without this patch, {ImportMapTy,SortedImportList}::{begin,end} make
unnecessary copies of ImportIDTable via:
map_iterator(Imports.begin(), IDs);
The second parameter, IDs, is passed by value, so we make a copy of
MapVector inside ImportIDTable every time we call begin and end.
These begin and end show up as time-consuming functions in the
performance profile.
This patch fixes the problem by passing IDs by reference with
std::cref.
While we are at it, this patch deletes the copy constructor and
assignment operator. I cannot think of any legitimate need reason to
make a copy of the deduplication table.
Commit: dc19b59ea2502193c0e7bc16bb7d711c8053edcf
https://github.com/llvm/llvm-project/commit/dc19b59ea2502193c0e7bc16bb7d711c8053edcf
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
Log Message:
-----------
[RISCV] Rename test cases in bfloat-arith.ll and half-arith.ll. NFC
Use _bf16 or _h instead of _s. The _s was copied from float-arith.ll
Commit: 2cbd1bc830861bc08f78fb6cc11747b82f66c4c6
https://github.com/llvm/llvm-project/commit/2cbd1bc830861bc08f78fb6cc11747b82f66c4c6
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/test/Modules/no-local-decl-in-reduced-bmi.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview-std.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview.cppm
M clang/test/Modules/unreached-static-entities.cppm
Log Message:
-----------
Revert "[C++20] [Modules] Embed all source files for C++20 Modules (#102444)"
This reverts commit 2eeeff842f993a694159183a2834b4d305549cad.
See the post commit discussion in
https://github.com/llvm/llvm-project/commit/2eeeff842f993a694159183a2834b4d305549cad
Commit: 78abeca1d88593d7f2a27f3c3e140abe77236e7e
https://github.com/llvm/llvm-project/commit/78abeca1d88593d7f2a27f3c3e140abe77236e7e
Author: s-watanabe314 <watanabe.shu-06 at fujitsu.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaCXX/extern-c.cpp
Log Message:
-----------
[clang][Sema] Fix diagnostic for function overloading in extern "C" (#106033)
Fixes #80235
When trying to overload a function within `extern "C"`, the diagnostic
`functions that differ only in their return type cannot be overloaded`
is given. This diagnostic is inappropriate because overloading is
basically not allowed in the C language. However, if the redeclared
function has the `((overloadable))` attribute, it should be diagnosed as
`functions that differ only in their return type cannot be overloaded`.
This patch uses `isExternC()` to provide an appropriate diagnostic
during the diagnostic process. `isExternC()` updates the linkage
information cache internally, so calling it before merging functions can
cause clang to crash. An example is declaring `static void foo()` and
`void foo()` within an `extern "C"` block. Therefore, I decided to call
`isExternC()` after the compilation error is confirmed and select the
diagnostic message. The diagnostic message is `conflicting types for
'func'` similar to the diagnostic in C, and `functions that differ only
in their return type cannot be overloaded` if the `((overloadable))`
attribute is given.
Regression tests verify that the expected diagnostics are given when
trying to overload functions within `extern "C"` and when the
`((overloadable))` attribute is present.
---------
Co-authored-by: Sirraide <aeternalmail at gmail.com>
Commit: 9a1eded9b9afa3eab1e0b5cad5dbff3117d22391
https://github.com/llvm/llvm-project/commit/9a1eded9b9afa3eab1e0b5cad5dbff3117d22391
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-02 (Mon, 02 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
The LegalizeDAG expansion will go through memory since i16 isn't a legal
type. Avoid this by using FMV nodes.
Similar to what we did for #106886 for FNEG and FABS. Special care is
needed to handle the Sign operand being a different type.
Commit: 042104985cc37d28db5f22f8bdf582c1108977d8
https://github.com/llvm/llvm-project/commit/042104985cc37d28db5f22f8bdf582c1108977d8
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
A llvm/lib/Target/AMDGPU/SIShrinkInstructions.h
M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
Log Message:
-----------
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
Commit: 8e5b43c8effc0a01745bb7c53ca21fb6c8384c51
https://github.com/llvm/llvm-project/commit/8e5b43c8effc0a01745bb7c53ca21fb6c8384c51
Author: Akshat Oke <76596238+Akshat-Oke at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
Log Message:
-----------
[AMDGPU][NewPM] Have consistent property changes in GCNDPPCombine (#106520)
Commit: 7d7d2d2b54172f97300c02ec80bb568d35403cce
https://github.com/llvm/llvm-project/commit/7d7d2d2b54172f97300c02ec80bb568d35403cce
Author: Da-Viper <57949090+Da-Viper at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/instruction-breakpoint/TestDAP_instruction_breakpoint.py
Log Message:
-----------
[lldb-dap][test] Fix: Typo in unresolved test (#107030)
There is a typo in an assertion that causes the instruction break-point
test to be unresolved
Commit: 00c198b2ca6b6bee2d90e62d78816686ab056b1b
https://github.com/llvm/llvm-project/commit/00c198b2ca6b6bee2d90e62d78816686ab056b1b
Author: Michael Marjieh <99331190+mmarjieh at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
A llvm/test/CodeGen/PowerPC/sms-recmii.ll
M llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir
Log Message:
-----------
[MachinePipeliner] Make Recurrence MII More Accurate (#105475)
Current RecMII calculation is bigger than it needs to be. The
calculation was refined in this patch.
Commit: 7e6bad112c978d1dabfd2c6bef4674224b63583c
https://github.com/llvm/llvm-project/commit/7e6bad112c978d1dabfd2c6bef4674224b63583c
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
Log Message:
-----------
[RISCV] Rename `vcix_state` register to `sf_vcix_state`. NFC (#106995)
Since it's SiFive VCIX specific register, it's better to have a prefix
so that it's more understandable.
Commit: af5c18ad356ee334f3ec629149940f84d4b5f06d
https://github.com/llvm/llvm-project/commit/af5c18ad356ee334f3ec629149940f84d4b5f06d
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/www/index.html
Log Message:
-----------
[compiler-rt] [docs] Mention Windows as one of the supported OSes (#106874)
Compiler-rt can be built for Windows, and most parts of it work. Some
parts only really work on x86/x86_64 (like address sanitizers), but the
OS overall is supported.
Commit: 525ffd626231a8c6fecb0b886c272ff4568f09f5
https://github.com/llvm/llvm-project/commit/525ffd626231a8c6fecb0b886c272ff4568f09f5
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/test/Analysis/mmap-writeexec.c
Log Message:
-----------
[clang][analyzer] Bring alpha.security.MmapWriteExec checker out of alpha package (#102636)
Commit: 04ed12ca3f027a3a189d181e5e5880285ebc7916
https://github.com/llvm/llvm-project/commit/04ed12ca3f027a3a189d181e5e5880285ebc7916
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/test/API/functionalities/memory/holes/TestMemoryHoles.py
Log Message:
-----------
[lldb] Support partial memory reads on windows (#106981)
ReadProcessMemory will not perform the read if part of the memory is
unreadable (and even though the API has a `number_of_bytes_read`
argument). To make this work, I explicitly inspect the memory region
being read and only read the accessible part.
Commit: 6c8746b6e36260e31067765ac1c8dd6cd3f5b868
https://github.com/llvm/llvm-project/commit/6c8746b6e36260e31067765ac1c8dd6cd3f5b868
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
Log Message:
-----------
[Analysis] getIntrinsicForCallSite - add vectorization support for acos/asin/atan and cosh/sinh/tanh libcalls (#106844)
Followup to #106584 - ensure acos/asin/atan and cosh/sinh/tanh libcalls correctly map to the llvm intrinsic equivalents
Commit: 733a92d7bced7119986a93a1b4e1c760f92b9583
https://github.com/llvm/llvm-project/commit/733a92d7bced7119986a93a1b4e1c760f92b9583
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/constexpr-frame-describe.cpp
Log Message:
-----------
[clang][bytecode] Print Pointers via APValue (#107056)
Instead of doing this ourselves, just rely on printing the APValue.
Commit: a70d999203702e245a54bc694048c8817215c65e
https://github.com/llvm/llvm-project/commit/a70d999203702e245a54bc694048c8817215c65e
Author: Christian Sigg <csigg at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Attempt to fix issue fetching remote blob
Bazel builds currently fail with `Failed to fetch blobs because they do not exist remotely.`. These extra bazel flags hopefully fix it.
Commit: 6c59dfb0184aa11ec202f1cd8aee9e971a1565a4
https://github.com/llvm/llvm-project/commit/6c59dfb0184aa11ec202f1cd8aee9e971a1565a4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/movmsk-cmp.ll
Log Message:
-----------
[X86] Add test showing failure to remove freeze from all_of pattern
Commit: 851bacb7ce66213d667c6ed375ce43ab0ed3cd56
https://github.com/llvm/llvm-project/commit/851bacb7ce66213d667c6ed375ce43ab0ed3cd56
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/IR/DebugProgramInstruction.cpp
Log Message:
-----------
[IR] DebugProgramInstruction.cpp - fix GCC Wparentheses warning. NFC.
Commit: 4befe65cf065a1be8bb8f30d76a3f45ea45aa63f
https://github.com/llvm/llvm-project/commit/4befe65cf065a1be8bb8f30d76a3f45ea45aa63f
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Semantics/OpenMP/clause-order.f90
Log Message:
-----------
[flang][semantics][OpenMP] store DSA using ultimate sym (#107002)
Previously we tracked data sharing attributes by the symbol itself not
by the ultimate symbol. When the private clause came first, subsequent
uses of the symbol found a host-associated version instead of the
ultimate symbol and so the check didn't consider them to be the same
symbol. Always adding and checking for the ultimate symbol ensures that
we have the same behaviour no matter the order of clauses.
The modified list is only used for this multiple clause check.
Closes #78235
Commit: 377045ece6471a1e59bb5239707aad54ba035ff2
https://github.com/llvm/llvm-project/commit/377045ece6471a1e59bb5239707aad54ba035ff2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/movmsk-cmp.ll
Log Message:
-----------
[X86] canCreateUndefOrPoisonForTargetNode - X86ISD::CMPP (CMPPS/D) nodes do not generate poison
Commit: fe1a1eee2ff864d2ba00ad67e6360b7178e67d5c
https://github.com/llvm/llvm-project/commit/fe1a1eee2ff864d2ba00ad67e6360b7178e67d5c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/JumpThreading/pr22086.ll
M llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
M llvm/test/Transforms/SCCP/loadtest2.ll
M llvm/test/Transforms/SCCP/select.ll
Log Message:
-----------
[Tests] Regenerate test checks (NFC)
Commit: c3d8124617a0f7916123174001547eb3b4968644
https://github.com/llvm/llvm-project/commit/c3d8124617a0f7916123174001547eb3b4968644
Author: Nathan Gauër <brioche at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
A llvm/test/Other/spirv-sim/branch.spv
A llvm/test/Other/spirv-sim/call.spv
A llvm/test/Other/spirv-sim/constant.spv
A llvm/test/Other/spirv-sim/lit.local.cfg
A llvm/test/Other/spirv-sim/loop.spv
A llvm/test/Other/spirv-sim/simple-bad-result.spv
A llvm/test/Other/spirv-sim/simple.spv
A llvm/test/Other/spirv-sim/simulator-args.spv
A llvm/test/Other/spirv-sim/switch.spv
A llvm/test/Other/spirv-sim/wave-get-lane-index.spv
A llvm/test/Other/spirv-sim/wave-read-lane-first.spv
M llvm/test/lit.cfg.py
A llvm/utils/spirv-sim/instructions.py
A llvm/utils/spirv-sim/spirv-sim.py
Log Message:
-----------
[Utils][SPIR-V] Adding spirv-sim to LLVM (#104020)
Currently, the testing infrastructure for SPIR-V is based on FileCheck.
Those tests are great to check some level of codegen, but when the test
needs check both the CFG layout and the content of each basic-block,
things becomes messy.
- Because the CHECK/CHECK-DAG/CHECK-NEXT state is limited, it is
sometimes hard to catch the good block: if 2 basic blocks have similar
instructions, FileCheck can match the wrong one.
- Cross-lane interaction can be a bit difficult to understand, and
writting a FileCheck test that is strong enough to catch bad CFG
transforms while not being broken everytime some unrelated codegen part
changes is hard.
And lastly, the spirv-val tooling we have checks that the generated
SPIR-V respects the spec, not that it is correct in regards to the
source IR.
For those reasons, I believe the best way to test the structurizer is
to:
- run spirv-val to make sure the CFG respects the spec.
- simulate the function to validate result for each lane, making sure
the generated code is correct.
This simulator has no other dependencies than core python. It also only
supports a very limited set of instructions as we can test most features
through control-flow and some basic cross-lane interactions.
As-is, the added tests are just a harness for the simulator itself. If
this gets merged, the structurizer PR will benefit from this as I'll be
able to add extensive testing using this.
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: d24a2fd38e42f58d6f34f3e985d9387139c12478
https://github.com/llvm/llvm-project/commit/d24a2fd38e42f58d6f34f3e985d9387139c12478
Author: Aditi Medhane <Aditi.Medhane at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
A llvm/test/MachineVerifier/AMDGPU/lit.local.cfg
A llvm/test/MachineVerifier/AMDGPU/register-killed-inside-loop.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_bitcast.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_intrinsic.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_intrinsic_w_side_effects.mir
A llvm/test/MachineVerifier/AMDGPU/undef-should-only-be-set-on-subreg-defs.mir
A llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
A llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-nonentry-block.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-pseudo-terminators.mir
A llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
A llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
A llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
R llvm/test/MachineVerifier/register-killed-inside-loop.mir
R llvm/test/MachineVerifier/test_g_bitcast.mir
R llvm/test/MachineVerifier/test_g_intrinsic.mir
R llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir
R llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir
R llvm/test/MachineVerifier/undef-virt-reg-entry-block.mir
R llvm/test/MachineVerifier/undef-virt-reg-nonentry-block.mir
R llvm/test/MachineVerifier/verifier-ec-subreg-liveness.mir
R llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir
R llvm/test/MachineVerifier/verifier-pseudo-terminators.mir
R llvm/test/MachineVerifier/verify-implicit-def.mir
R llvm/test/MachineVerifier/verify-reg-sequence.mir
R llvm/test/MachineVerifier/writelane_m0.mir
Log Message:
-----------
[AMDGPU] Create dir for amdgpu specific machineverifier tests (#106960)
Move the AMDGPU target specific testcases in MachineVerifier separately
into new directory.
Reference :
https://github.com/llvm/llvm-project/pull/105494#discussion_r1735055750
Commit: 4d8903bd4e6ec29ab28be0d8949c7fde4a740fbe
https://github.com/llvm/llvm-project/commit/4d8903bd4e6ec29ab28be0d8949c7fde4a740fbe
Author: Pablo Antonio Martinez <pablo.antonio.martinez at huawei.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir
Log Message:
-----------
[mlir][vector] Refactor vector-transfer-to-vector-load-store.mlir (NFC) (#105509)
Overview of changes:
- All memref input arguments are re-named to %mem.
- All vector input arguments are re-named to %vec.
- All index input arguments are re-named to %idx.
- All tensor input arguments are re-named to %src/%dst.
- LIT variables were updated to be consistent with input arguments.
- Renamed all output arguments as %res.
- Removed unused argument in `transfer_write_broadcast_unit_dim`.
- Unified identation of `FileCheck` commands.
- Split `transfer_write_permutations` and `transfer_write_broadcast_unit_dim` into tensor and memref variants.
- Renamed `transfer_write_permutations_tensor` as `transfer_write_permutations_tensor_masked`.
Commit: 52b879594fa1e80c871fe227e96443c3c8a8cfc2
https://github.com/llvm/llvm-project/commit/52b879594fa1e80c871fe227e96443c3c8a8cfc2
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
Log Message:
-----------
[LoopUnroll] Avoid undef values in test (NFC)
Avoid most of the code being optimized away as a result of
optimization improvements.
Commit: 8861328303a5b1c45443bbd02338623e41df1da4
https://github.com/llvm/llvm-project/commit/8861328303a5b1c45443bbd02338623e41df1da4
Author: Nathan Gauër <brioche at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
R llvm/test/Other/spirv-sim/branch.spv
R llvm/test/Other/spirv-sim/call.spv
R llvm/test/Other/spirv-sim/constant.spv
R llvm/test/Other/spirv-sim/lit.local.cfg
R llvm/test/Other/spirv-sim/loop.spv
R llvm/test/Other/spirv-sim/simple-bad-result.spv
R llvm/test/Other/spirv-sim/simple.spv
R llvm/test/Other/spirv-sim/simulator-args.spv
R llvm/test/Other/spirv-sim/switch.spv
R llvm/test/Other/spirv-sim/wave-get-lane-index.spv
R llvm/test/Other/spirv-sim/wave-read-lane-first.spv
M llvm/test/lit.cfg.py
R llvm/utils/spirv-sim/instructions.py
R llvm/utils/spirv-sim/spirv-sim.py
Log Message:
-----------
Revert "[Utils][SPIR-V] Adding spirv-sim to LLVM" (#107084)
Reverts llvm/llvm-project#104020
Looks like it caused build failures.
Commit: 5e19e317c0c996b913fddf7f07b6b93285e8dea8
https://github.com/llvm/llvm-project/commit/5e19e317c0c996b913fddf7f07b6b93285e8dea8
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M libcxx/test/benchmarks/format.bench.cpp
M libcxx/test/benchmarks/format_to.bench.cpp
M libcxx/test/benchmarks/format_to_n.bench.cpp
M libcxx/test/benchmarks/formatted_size.bench.cpp
M libcxx/test/benchmarks/formatter_int.bench.cpp
M libcxx/test/benchmarks/lexicographical_compare_three_way.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
M libcxx/test/benchmarks/to_chars.bench.cpp
M libcxx/test/benchmarks/variant_visit_1.bench.cpp
M libcxx/test/benchmarks/variant_visit_2.bench.cpp
M libcxx/test/benchmarks/variant_visit_3.bench.cpp
Log Message:
-----------
[libc++][NFC] Canonicalize the benchmark suite a bit
This replaces `BENCHMARK_TEMPLATE` with `BENCHMARK` and uses
`BENCHMARK_MAIN()` when possible.
Commit: a5f03b4adcd147aeecc0e0d029660c12fb4d2951
https://github.com/llvm/llvm-project/commit/a5f03b4adcd147aeecc0e0d029660c12fb4d2951
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/TestDataFormatterGenericOptional.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/main.cpp
Log Message:
-----------
[lldb] Support "dereferencing" std::optional in `frame var` (#107077)
Commit: 4353530a6fc92c5748a73042371c2ddf487433e7
https://github.com/llvm/llvm-project/commit/4353530a6fc92c5748a73042371c2ddf487433e7
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/unittests/Host/MainLoopTest.cpp
Log Message:
-----------
[lldb/windows] Reset MainLoop events after handling them (#107061)
This prevents the callback function from being called in a busy loop.
Discovered by @slydiman on #106955.
Commit: 3d5e1ec6508c8425601d4cfaba4c8a8f18791e2b
https://github.com/llvm/llvm-project/commit/3d5e1ec6508c8425601d4cfaba4c8a8f18791e2b
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/include/lldb/Host/common/TCPSocket.h
M lldb/source/Host/common/TCPSocket.cpp
M lldb/unittests/Host/SocketTest.cpp
Log Message:
-----------
[lldb] Add a callback version of TCPSocket::Accept (#106955)
The existing function already used the MainLoop class, which allows one
to wait on multiple events at once. It needed to do this in order to
wait for v4 and v6 connections simultaneously. However, since it was
creating its own instance of MainLoop, this meant that it was impossible
to multiplex these sockets with anything else.
This patch simply adds a version of this function which uses an
externally provided main loop instance, which allows the caller to add
any events it deems necessary. The previous function becomes a very thin
wrapper over the new one.
Commit: 0748f4227cd6a4a32b155d4bb9ad3f07e1b54bfe
https://github.com/llvm/llvm-project/commit/0748f4227cd6a4a32b155d4bb9ad3f07e1b54bfe
Author: Him188 <tguan at nvidia.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/AArch64/fabs-fp128.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize 128-bit types for FABS (#104753)
This patch adds a common lower action for `G_FABS`, which generates `and
x8, x8, #0x7fffffffffffffff` to reset the sign bit. The action does not
support vectors since `G_AND` does not support fp128.
This approach is different than what SDAG is doing. SDAG stores the
value onto stack, clears the sign bit in the most significant byte, and
loads the value back into register. This involves multiple memory ops
and sounds slower.
Commit: aa4f81efb99c93da3283ff3178be8db51cd655e2
https://github.com/llvm/llvm-project/commit/aa4f81efb99c93da3283ff3178be8db51cd655e2
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/stack-addr-ps.cpp
Log Message:
-----------
[analyzer] Fix false positive for stack-addr leak on simple param ptr (#107003)
Assigning to a pointer parameter does not leak the stack address because
it stays within the function and is not shared with the caller.
Previous implementation reported any association of a pointer parameter
with a local address, which is too broad.
This fix enforces that the pointer to a stack variable is related by at
least one level of indirection.
CPP-5642
Fixes #106834
Commit: f77f60400f7a4c0c50bc3e3144cdade3bdf9aa3d
https://github.com/llvm/llvm-project/commit/f77f60400f7a4c0c50bc3e3144cdade3bdf9aa3d
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
Log Message:
-----------
[CodeGen] Remove checks that implicit operands are implicit
Commit: 0f5f440f24bc2af4e8ab481a99e03de438b12987
https://github.com/llvm/llvm-project/commit/0f5f440f24bc2af4e8ab481a99e03de438b12987
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
Log Message:
-----------
[clang][bytecode] Pass FPOptions to floating point ops (#107063)
So we don't have to retrieve them from the InterpFrame, which is slow.
Commit: c80cabfcbe88d2f67372bba982eadf45330a5e1b
https://github.com/llvm/llvm-project/commit/c80cabfcbe88d2f67372bba982eadf45330a5e1b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/SCCP/widening.ll
Log Message:
-----------
[SCCP] Avoid use of undef value in test (NFC)
Avoid optimization away most of the code if we resolve this to
a specific value.
Commit: 1a0cf245ac86c2f35c89cab47f83e9b474032e41
https://github.com/llvm/llvm-project/commit/1a0cf245ac86c2f35c89cab47f83e9b474032e41
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/plugins-nextgen/host/CMakeLists.txt
M offload/test/api/is_initial_device.c
M offload/test/lit.cfg
M offload/test/mapping/declare_mapper_nested_default_mappers_array.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_array_subscript.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_complex_structure.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_ptr_subscript.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_var.cpp
M offload/test/mapping/map_both_pointer_pointee.c
M offload/test/mapping/target_pointers_members_map.cpp
M offload/test/offloading/CUDA/basic_launch.cu
M offload/test/offloading/CUDA/basic_launch_blocks_and_threads.cu
M offload/test/offloading/CUDA/basic_launch_multi_arg.cu
M offload/test/offloading/CUDA/launch_tu.cu
M offload/test/offloading/dynamic-schedule-non-spmd.cpp
M offload/test/offloading/dynamic-schedule.cpp
M offload/test/offloading/fortran/dtype-array-constant-index-map.f90
M offload/test/offloading/fortran/dump_map_tables.f90
M offload/test/offloading/fortran/target-depend.f90
M offload/test/offloading/fortran/target-map-all-common-block-members.f90
M offload/test/offloading/fortran/target-map-common-block.f90
M offload/test/offloading/fortran/target-map-declare-target-link-common-block.f90
M offload/test/offloading/fortran/target-map-first-common-block-member.f90
M offload/test/offloading/fortran/target-map-mix-imp-exp-common-block-members.f90
M offload/test/offloading/fortran/target-map-second-common-block-member.f90
M offload/test/offloading/high_trip_count_block_limit.cpp
M offload/test/offloading/schedule.c
M offload/test/sanitizer/double_free.c
M offload/test/sanitizer/double_free_racy.c
M offload/test/sanitizer/free_host_ptr.c
M offload/test/sanitizer/free_wrong_ptr_kind.c
M offload/test/sanitizer/free_wrong_ptr_kind.cpp
M offload/test/sanitizer/kernel_crash.c
M offload/test/sanitizer/kernel_crash_async.c
M offload/test/sanitizer/kernel_crash_many.c
M offload/test/sanitizer/kernel_crash_single.c
M offload/test/sanitizer/kernel_trap.c
M offload/test/sanitizer/kernel_trap.cpp
M offload/test/sanitizer/kernel_trap_async.c
M offload/test/sanitizer/kernel_trap_many.c
M offload/test/sanitizer/ptr_outside_alloc_1.c
M offload/test/sanitizer/ptr_outside_alloc_2.c
M offload/test/sanitizer/use_after_free_1.c
M offload/test/sanitizer/use_after_free_2.c
Log Message:
-----------
[Offload] Change x86_64-pc-linux to x86_64-unknown-linux (#107023)
It appears that the RUNTIMES build prefers the x86-64-unknown-linux-gnu
triple notation for the host. This fixes runtime / test breakages when
compiler-rt is used as the CLANG_DEFAULT_RTLIB.
Commit: 70a19adbc60c738903bbbb8e6d5ef2d41b681089
https://github.com/llvm/llvm-project/commit/70a19adbc60c738903bbbb8e6d5ef2d41b681089
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformFuchsia.c
M compiler-rt/test/profile/ContinuousSyncMode/runtime-counter-relocation.c
M compiler-rt/test/profile/ContinuousSyncMode/set-file-object.c
Log Message:
-----------
[profile] Change __llvm_profile_counter_bias etc. types to match llvm (#102747)
As detailed in Issue #101667, two `profile` tests `FAIL` on 32-bit
SPARC, both Linux/sparc64 and Solaris/sparcv9 (where the tests work when
enabled):
```
Profile-sparc :: ContinuousSyncMode/runtime-counter-relocation.c
Profile-sparc :: ContinuousSyncMode/set-file-object.c
```
The Solaris linker provides the crucial clue as to what's wrong:
```
ld: warning: symbol '__llvm_profile_counter_bias' has differing sizes:
(file runtime-counter-relocation-17ff25.o value=0x8; file libclang_rt.profile-sparc.a(InstrProfilingFile.c.o) value=0x4);
runtime-counter-relocation-17ff25.o definition taken
```
In fact, the types in `llvm` and `compiler-rt` differ:
- `__llvm_profile_counter_bias`/`INSTR_PROF_PROFILE_COUNTER_BIAS_VAR` is
created in `llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp`
(`InstrLowerer::getCounterAddress`) as `int64_t`, while
`compiler-rt/lib/profile/InstrProfilingFile.c` uses `intptr_t`. While
this doesn't matter in the 64-bit case, the type sizes differ for
32-bit.
- `__llvm_profile_bitmap_bias`/`INSTR_PROF_PROFILE_BITMAP_BIAS_VAR` has
the same issue: created in `InstrProfiling.cpp`
(`InstrLowerer::getBitmapAddress`) as `int64_t`, while
`InstrProfilingFile.c` again uses `intptr_t`.
This patch changes the `compiler-rt` types to match `llvm`. At the same
time, the affected testcases are enabled on Solaris, too, where they now
just `PASS`.
Tested on `sparc64-unknown-linux-gnu`, `sparcv9-sun-solaris2.11`,
`x86_64-pc-linux-gnu`, and `amd64-pc-solaris2.11.
Commit: f381cd069965dabfeb277f30a4e532d7fd498f6e
https://github.com/llvm/llvm-project/commit/f381cd069965dabfeb277f30a4e532d7fd498f6e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/minbw-user-non-sizable.ll
Log Message:
-----------
[SLP]Fix PR107036: Check if the type of the user is sizable before requesting its size.
Only some instructions should be considered as potentially reducing the
size of the operands types, not all instructions should be considered.
Fixes https://github.com/llvm/llvm-project/issues/107036
Commit: 0797c184c636889f2897746dc71390ae28005c7c
https://github.com/llvm/llvm-project/commit/0797c184c636889f2897746dc71390ae28005c7c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
Log Message:
-----------
[SCCP] Explicitly mark gep as overdefined if ct eval fails
Don't just leave the result as unknown. I think this currently
works out thanks to undef resolution, but the correct thing to
do is set it to overdefined explicitly.
Commit: dd94537b40cfb8c480df27c08fc715ce91ba4089
https://github.com/llvm/llvm-project/commit/dd94537b40cfb8c480df27c08fc715ce91ba4089
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
Log Message:
-----------
[LV] Update call widening decision when scalarzing calls.
collectInstsToScalarize may decide to scalarize a call. If so, we have
to update the widening decision for the call, otherwise the call won't
be scalarized as expected during VPlan construction.
This issue was uncovered by f82543d509.
Commit: b74e09cb20e6218320013b54c9ba2f5c069d44b9
https://github.com/llvm/llvm-project/commit/b74e09cb20e6218320013b54c9ba2f5c069d44b9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/RISCV/unique-loads-insert-non-power-of-2.ll
Log Message:
-----------
[SLP]Check for the whole vector vectorization in unique scalars analysis
Need to check that thr whole number of register is attempted to
vectorize before actually trying to build the node to avoid compiler
crash.
Commit: ce8ec31298d5fbd81712af0f6bc34dae87f7f30c
https://github.com/llvm/llvm-project/commit/ce8ec31298d5fbd81712af0f6bc34dae87f7f30c
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/revec-shufflevector.ll
Log Message:
-----------
[SLP][REVEC] Support more mask pattern usage in shufflevector. (#106212)
Commit: a424b792053a48ef7e00636f28f3cc8faa23d637
https://github.com/llvm/llvm-project/commit/a424b792053a48ef7e00636f28f3cc8faa23d637
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_context.cpp
M compiler-rt/lib/rtsan/rtsan_context.h
M compiler-rt/lib/rtsan/rtsan_stack.cpp
M compiler-rt/lib/rtsan/rtsan_stack.h
M compiler-rt/test/rtsan/basic.cpp
Log Message:
-----------
[compiler-rt][rtsan] Record pc and bp higher up in the stack (#107014)
Functionally, this change affects only our printed stack traces. New
version does not expose any internal rtsan interworking
Commit: 20fa37bbfabca512b16a8497eb671a3bd4b5b96b
https://github.com/llvm/llvm-project/commit/20fa37bbfabca512b16a8497eb671a3bd4b5b96b
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[Vectorize] Fix -Wunused-variable in SLPVectorizer.cpp (NFC)
/llvm-project/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:10310:26:
error: unused variable 'isExtractSubvectorMask' [-Werror,-Wunused-variable]
bool isExtractSubvectorMask =
^
1 error generated.
Commit: d7c44eff42f7c05d364e4a00048c534a30cea24b
https://github.com/llvm/llvm-project/commit/d7c44eff42f7c05d364e4a00048c534a30cea24b
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/revec.ll
Log Message:
-----------
[SLP][REVEC] Update test. NFC.
Commit: 7852ebc088b925ef1c1940cbd56a93d9f8e3e330
https://github.com/llvm/llvm-project/commit/7852ebc088b925ef1c1940cbd56a93d9f8e3e330
Author: yonghong-song <yhs at fb.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/BPF.cpp
M clang/test/Preprocessor/bpf-predefined-macros.c
M llvm/lib/Target/BPF/BPFSubtarget.cpp
M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-3.ll
M llvm/test/CodeGen/BPF/CORE/no-narrow-load.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp2.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp3.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp4.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp5.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp6.ll
M llvm/test/CodeGen/BPF/adjust-opt-speculative1.ll
M llvm/test/CodeGen/BPF/adjust-opt-speculative2.ll
M llvm/test/CodeGen/BPF/alu8.ll
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/basictest.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
M llvm/test/CodeGen/BPF/cc_args.ll
M llvm/test/CodeGen/BPF/cc_args_be.ll
M llvm/test/CodeGen/BPF/cc_ret.ll
M llvm/test/CodeGen/BPF/cmp.ll
M llvm/test/CodeGen/BPF/cttz-ctlz.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/fi_ri.ll
M llvm/test/CodeGen/BPF/i128.ll
M llvm/test/CodeGen/BPF/intrinsics.ll
M llvm/test/CodeGen/BPF/load.ll
M llvm/test/CodeGen/BPF/loops.ll
M llvm/test/CodeGen/BPF/many_args1.ll
M llvm/test/CodeGen/BPF/objdump_atomics.ll
M llvm/test/CodeGen/BPF/objdump_cond_op.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/BPF/objdump_imm_hex.ll
M llvm/test/CodeGen/BPF/objdump_intrinsics.ll
M llvm/test/CodeGen/BPF/objdump_nop.ll
M llvm/test/CodeGen/BPF/objdump_static_var.ll
M llvm/test/CodeGen/BPF/objdump_trivial.ll
M llvm/test/CodeGen/BPF/pr57872.ll
M llvm/test/CodeGen/BPF/reloc-2.ll
M llvm/test/CodeGen/BPF/remove_truncate_1.ll
M llvm/test/CodeGen/BPF/remove_truncate_2.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/remove_truncate_6.ll
M llvm/test/CodeGen/BPF/remove_truncate_8.ll
M llvm/test/CodeGen/BPF/rodata_1.ll
M llvm/test/CodeGen/BPF/rodata_2.ll
M llvm/test/CodeGen/BPF/rodata_3.ll
M llvm/test/CodeGen/BPF/rodata_4.ll
M llvm/test/CodeGen/BPF/rodata_6.ll
M llvm/test/CodeGen/BPF/rodata_7.ll
M llvm/test/CodeGen/BPF/sanity.ll
M llvm/test/CodeGen/BPF/setcc.ll
M llvm/test/CodeGen/BPF/shifts.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/undef.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/tools/llvm-objdump/BPF/interleaved-source-test.ll
Log Message:
-----------
[BPF] Make -mcpu=v3 as the default (#107008)
Before llvm20, (void)__sync_fetch_and_add(...) always generates locked
xadd insns. In linux kernel upstream discussion [1], it is found that
for arm64 architecture, the original semantics of
(void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is
preferred in order for jit to emit proper native barrier insns.
In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will
generate the following insns:
- for cpu v1/v2: locked xadd insns to keep backward compatibility
- for cpu v3/v4: __atomic_fetch_add() insns
To ensure proper barrier semantics for (void)__sync_fetch_and_add(...),
cpu v3/v4 is recommended.
This patch enables cpu=v3 as the default cpu version. For users wanting
to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc
command line.
[1]
https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f
[2] https://github.com/llvm/llvm-project/pull/101428
[3] https://github.com/llvm/llvm-project/pull/106494
Commit: f70ccdaeb4ef9681ea490ea7779efbe72e643eda
https://github.com/llvm/llvm-project/commit/f70ccdaeb4ef9681ea490ea7779efbe72e643eda
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode][NFC] Move Call ops into Interp.cpp (#107104)
They are quite long and not templated.
Commit: df159d3cf8e681f8d225bd0b4ed0cbd97b16c588
https://github.com/llvm/llvm-project/commit/df159d3cf8e681f8d225bd0b4ed0cbd97b16c588
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
Log Message:
-----------
[GISEL][AArch64][NFC] Stop using wip_match_opcode for some opcodes (#106702)
This patch moves to the new style of writing
pattern for matching opcodes and thus deprecates using wip_match_opcoee.
It moves G_FCONSTANT, G_ICMP, G_STORE, and G_OR.
Commit: 05f5a91d00b02f4369f46d076411c700755ae041
https://github.com/llvm/llvm-project/commit/05f5a91d00b02f4369f46d076411c700755ae041
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/sink-foldable.ll
Log Message:
-----------
LICM: use IRBuilder in hoist BO assoc (#106978)
Use IRBuilder when creating the new invariant instruction, so that the
constant-folder has an opportunity to constant-fold the new Instruction
that we desire to create.
Commit: fedc7556ad5237cd11e29b8e70d412bdc39a4fa6
https://github.com/llvm/llvm-project/commit/fedc7556ad5237cd11e29b8e70d412bdc39a4fa6
Author: Nick Sarnie <sarnex at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/LTO/LTO.cpp
Log Message:
-----------
[ThinLTO] Don't always print ModulesToCompile debugging information (#106769)
Nothing went wrong in this case, we just successfully matched a module
by identifier. No need to print to std::error like we would for
something that should be user-visible.
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 3b6e255c8339b0945f5f55757ee193fe23b47e2c
https://github.com/llvm/llvm-project/commit/3b6e255c8339b0945f5f55757ee193fe23b47e2c
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/Transforms/LICM/update-scev-after-hoist.ll
Log Message:
-----------
LICM/test: regen a test with UTC (NFC) (#107117)
Commit: b7017ef44827314758ba32c97eacb2d3f08c18e6
https://github.com/llvm/llvm-project/commit/b7017ef44827314758ba32c97eacb2d3f08c18e6
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV] Rename sf_vcix_state to sf.vcix_state. NFC (#107115)
This PR: https://github.com/llvm/llvm-project/pull/106995 names the
vendor CSR in a wrong way, it should be `sf.` rather than `sf_` for
prefix.
Commit: e1bde1c5b203224b0fa68ee141ec2c7a079f5eac
https://github.com/llvm/llvm-project/commit/e1bde1c5b203224b0fa68ee141ec2c7a079f5eac
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SDAG] Fix a typo in comment
Commit: 2a9f93bf13c717af3fe06bc226047f96b3f9c21a
https://github.com/llvm/llvm-project/commit/2a9f93bf13c717af3fe06bc226047f96b3f9c21a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/MC/RISCV/fp-default-rounding-mode.s
M llvm/test/MC/RISCV/rv32zfbfmin-valid.s
Log Message:
-----------
[RISCV] Use RNE rounding mode for fcvt.s.bf16. Don't print the rounding mode if RNE. (#106948)
The rounding mode has no effect on the instruction behavior. Using RNE
matches what we do for fcvt.s.h, fcvt.d.f, fcvt.d.h which are similarily
not affected by the rounding mode.
This appears to match the behavior of binutils. According to compiler
explore, objdump is unable to disassembler fcvt.s.bf16 with a non-zero
rounding mode.
Commit: 59a3b4156836c3ea8589d7a39e7b4712fc8698ec
https://github.com/llvm/llvm-project/commit/59a3b4156836c3ea8589d7a39e7b4712fc8698ec
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M llvm/include/llvm/ADT/DenseMap.h
M mlir/lib/Transforms/SROA.cpp
Log Message:
-----------
[ADT] Deprecate DenseMap::getOrInsertDefault (#107040)
This patch deprecates DenseMap::getOrInsertDefault in favor of
DenseMap::operator[], which does the same thing, has been around
longer, and is also a household name as part of std::map and
std::unordered_map.
Note that DenseMap provides several equivalent ways to insert or
default-construct a key-value pair:
- operator[Key]
- try_emplace(Key).first->second
- getOrInsertDefault(Key)
- FindAndConstruct(Key).second
Commit: 86835d2d5a24ed00ed3747b77029c896ba935036
https://github.com/llvm/llvm-project/commit/86835d2d5a24ed00ed3747b77029c896ba935036
Author: Daniel Grumberg <dgrumberg at apple.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
Log Message:
-----------
[clang][ExtractAPI] Remove erroneous module name check in MacroCallbacks (#107059)
rdar://135044923
Commit: 93857afc24abeeacdd58277b4ab32d38daa1e531
https://github.com/llvm/llvm-project/commit/93857afc24abeeacdd58277b4ab32d38daa1e531
Author: Christian Sigg <csigg at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/unittests/Driver/SimpleDiagnosticConsumer.h
Log Message:
-----------
[clang][Driver] Add missing include after 26bf0b4ae7df7f5350f71afd40a57cdf8f98c588.
https://github.com/llvm/llvm-project/commit/26bf0b4ae7df7f5350f71afd40a57cdf8f98c588
Commit: 903d1c6ee5de4ee87c1737906c264e219c05d4cb
https://github.com/llvm/llvm-project/commit/903d1c6ee5de4ee87c1737906c264e219c05d4cb
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/tools/driver/CMakeLists.txt
M libclc/CMakeLists.txt
M llvm/tools/llvm-as/CMakeLists.txt
M llvm/tools/llvm-link/CMakeLists.txt
M llvm/tools/opt/CMakeLists.txt
Log Message:
-----------
[libclc] More cross compilation fixes (#97811)
* Move the setup_host_tool calls to the directories of their tool.
Although it works to call it in libclc, it can only appear in a single
location so it fails the "what if everyone did this?" test and causes
problems for downstream code that also wants to use native versions of
these tools from other projects.
* Correct the TARGET "${${tool}_target}" check. "${${tool}_target}" may
be set to the path to the executable, which works in dependencies but
cannot be tested using if(TARGET). For lack of a better alternative,
just check that "${${tool}_target}" is non-empty and trust that if it
is, it is set to a meaningful value. If somehow it turns out to be a
valid target, its value will still show up in error messages anyway.
* Account for llvm-spirv possibly being provided in-tree. Per
https://github.com/KhronosGroup/SPIRV-LLVM-Translator?tab=readme-ov-file#llvm-in-tree-build
it is possible to drop llvm-spirv into LLVM and have it built as part of
LLVM's build. In this configuration, cross builds of LLVM require a
native version of llvm-spirv to be built.
Commit: f1ef67ded5371ddeb0ee72ea435f61f58c9127c6
https://github.com/llvm/llvm-project/commit/f1ef67ded5371ddeb0ee72ea435f61f58c9127c6
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-binop.ll
M llvm/test/Transforms/LICM/update-scev-after-hoist.ll
Log Message:
-----------
LICM: extend hoist BO assoc to mul case (#106991)
Trivially extend hoistBOAssociation to also handle the BinaryOperator
Mul.
Alive2 proofs: https://alive2.llvm.org/ce/z/zjtR5g
Commit: 4da0aa382a706b002504134d38385e377bf20c89
https://github.com/llvm/llvm-project/commit/4da0aa382a706b002504134d38385e377bf20c89
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/lld/test/BUILD.gn
Log Message:
-----------
[gn build] Add missing llvm-strings dependency to check-lld (#106896)
This has been required by `lld/test/ELF/zsectionheader.s` since it was
added in 5d972c58.
Commit: df4746d1d076016095059da4af2a3c3cc54657fe
https://github.com/llvm/llvm-project/commit/df4746d1d076016095059da4af2a3c3cc54657fe
Author: Christian Sigg <csigg at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Change cache-silo-key to fix blob fetch issue.
Bazel builds currently fail with `Failed to fetch blobs because they do not exist remotely.`.
Set a cache-silo-key to start a new cache.
Commit: 2c7786e94a1058bd4f96794a1d4f70dcb86e5cc5
https://github.com/llvm/llvm-project/commit/2c7786e94a1058bd4f96794a1d4f70dcb86e5cc5
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/sphinx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelements-vector-ops-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Log Message:
-----------
Prefer use of 0.0 over -0.0 for fadd reductions w/nsz (in IR) (#106770)
This is a follow up to 924907bc6, and is mostly motivated by consistency
but does include one additional optimization. In general, we prefer 0.0
over -0.0 as the identity value for an fadd. We use that value in
several places, but don't in others. So, let's be consistent and use the
same identity (when nsz allows) everywhere.
This creates a bunch of test churn, but due to 924907bc6, most of that
churn doesn't actually indicate a change in codegen. The exception is
that this change enables the use of 0.0 for nsz, but *not* reasoc, fadd
reductions. Or said differently, it allows the neutral value of an
ordered fadd reduction to be 0.0.
Commit: 8e4b8155c1b80a68fcf854c305f06602b37da218
https://github.com/llvm/llvm-project/commit/8e4b8155c1b80a68fcf854c305f06602b37da218
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/CodeGen/M68k/pipeline.ll
Log Message:
-----------
[M68k] Fix compilation pipeline check
- After 'RemoveLoadsIntoFakeUses' is enabled to support llvm.fake.use
Commit: 9626e84faeaab200665bae9694458c2beb3d49c7
https://github.com/llvm/llvm-project/commit/9626e84faeaab200665bae9694458c2beb3d49c7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode][NFC] Simplify builtin-functions.cpp (#107118)
The effect is the same, but this version doesn't take as long to
evaluate.
Commit: 0b2f2537a5b717539b200bd7fa31cbc24679e96f
https://github.com/llvm/llvm-project/commit/0b2f2537a5b717539b200bd7fa31cbc24679e96f
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[LV] Separate AnyOf recurrence from getRecurrenceIdentity [NFC]
These recurrence types don't have a meaningful identity, and the
routine was abused to return the start value instead. Out of the
three callers to this routine, only one actually wants this
behavior. This is a prep change for removing the routine entirely
and commoning it with other copies of the same logic.
Commit: a8e1c6f99abc273677afed5eaaeee2c0296db59f
https://github.com/llvm/llvm-project/commit/a8e1c6f99abc273677afed5eaaeee2c0296db59f
Author: Giuseppe Rossini <giuseppe.rossini at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
A mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx12.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[MLIR][AMDGPU] Add support for fp8 ops on gfx12 (#106388)
This PR is adding support for `fp8` and `bfp8` on gfx12
Commit: ebdadcfeb9c63f56703bf47dfeb6aff5a66ddfa1
https://github.com/llvm/llvm-project/commit/ebdadcfeb9c63f56703bf47dfeb6aff5a66ddfa1
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchEmpty.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
M llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll
M llvm/test/CodeGen/SPIRV/transcoding/GlobalFunAnnotate.ll
Log Message:
-----------
[SPIR-V] Improve correctness of emitted MIR between passes for branching instructions (#106966)
This PR improves correctness of emitted MIR between passes for branching
instructions and thus increase number of passing tests when expensive
checks are on. Specifically, we address here such issues with machine
verifier as:
* fix switch generation: generate correct successors and undo the
"address taken" status to reflect that a successor doesn't actually
correspond to an IR-level basic block;
* fix incorrect definition of OpBranch and OpBranchConditional in
TableGen (SPIRVInstrInfo.td) to set isBarrier status properly and set a
correct type of virtual registers;
* fix a case when Phi refers to a type definition that goes after the
Phi instruction, so that the virtual register definition of the type
doesn't dominate all uses.
This PR decrease number of failing tests under expensive checks from 56
to 50.
Commit: 4f403e88f260cd1df3633fbcbe8fa8d1c8e0a745
https://github.com/llvm/llvm-project/commit/4f403e88f260cd1df3633fbcbe8fa8d1c8e0a745
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/debug-info/no-misplaced-opextinst.ll
Log Message:
-----------
[SPIR-V] Ensure that OpExtInst instructions generated by NonSemantic_Shader_DebugInfo_100 are not mixed up with other OpExtInst instructions (#107007)
This PR is to ensure that OpExtInst instructions generated by
NonSemantic_Shader_DebugInfo_100 are not mixed up with other OpExtInst
instructions.
Original implementation
(https://github.com/llvm/llvm-project/pull/97558) has introduced an
issue by moving OpExtInst instruction with the 3rd operand equal to
DebugSource (value 35) or DebugCompilationUnit (value 1) even if
OpExtInst is not generated by NonSemantic_Shader_DebugInfo_100
implementation code.
The reproducer is attached as a new test case. The code of the test case
reproduces the issue, because "lgamma" has the same code (35) inside
OpenCL_std as DebugSource inside NonSemantic_Shader_DebugInfo_100.
Commit: e89bcfc0e86cd4952c03fdf920d11c598ae6e16a
https://github.com/llvm/llvm-project/commit/e89bcfc0e86cd4952c03fdf920d11c598ae6e16a
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
Log Message:
-----------
[SandboxIR] Add tracking for ShuffleVectorInst::commute. (#106644)
Track it as an operand swap + a `setShuffleMask` and delegate to the
`llvm::ShuffleVectorInst` implementation.
Commit: fdc1b5d290edfefe93c2bf0582e8e4363bda63ee
https://github.com/llvm/llvm-project/commit/fdc1b5d290edfefe93c2bf0582e8e4363bda63ee
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/tools/opt/NewPMDriver.cpp
M llvm/tools/opt/NewPMDriver.h
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
[NFC][opt] Rename VerifierKind enums (#106789)
Make into enum class.
Output really should be InputOutput since it also verifies the input IR.
Commit: 46407366166dc84c95075cf273acc005605967fe
https://github.com/llvm/llvm-project/commit/46407366166dc84c95075cf273acc005605967fe
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M libcxx/modules/std/type_traits.inc
Log Message:
-----------
[libc++] Add missing `std::is_virtual_base_of` to `type_traits.inc` (#107009)
std::is_virtual_base_of was implemented in https://github.com/llvm/llvm-project/pull/105847
Commit: 26a4edf655aac138ef4f8cebf865d34b9ab4ff2d
https://github.com/llvm/llvm-project/commit/26a4edf655aac138ef4f8cebf865d34b9ab4ff2d
Author: Petr Hosek <phosek at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M cmake/Modules/HandleCompilerRT.cmake
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
Log Message:
-----------
[CMake][compiler-rt] Support for using compiler-rt atomic library (#106603)
Not every toolchain provides and want to use libatomic which is a part
of GCC, some toolchains may opt into using compiler-rt atomic library.
Commit: b91b1f0bd38c8e5d8f7eb30413ec799581e3d46e
https://github.com/llvm/llvm-project/commit/b91b1f0bd38c8e5d8f7eb30413ec799581e3d46e
Author: vporpo <vporpodas at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[SandboxIR] Implement remaining ConstantInt functions (#106775)
This patch adds the remaining ConstantInt:: functions and it also
implements the IntegerType class.
Commit: fb14f1df54c3e4edaaf3aa34268147f4da11d3b4
https://github.com/llvm/llvm-project/commit/fb14f1df54c3e4edaaf3aa34268147f4da11d3b4
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/CodeGen/pgo-force-function-attrs.ll
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Instrumentation/PGOForceFunctionAttrs/basic.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
Log Message:
-----------
[PGO][Pipeline] Enable PGOForceFunctionAttrs in PGO optimization pipelines (#106790)
Remove flag that turns on the PGOForceFunctionAttrs pass and always add
it to default pipelines when using PGO.
This is NFC by default since PGOOpt->ColdOptType is by default
ColdFuncOpt::Default.
Remove -O2 RUN line in basic.ll since we now have the pipeline tests.
Commit: 42f5277de16cd7fad01285ade9004675b8253ced
https://github.com/llvm/llvm-project/commit/42f5277de16cd7fad01285ade9004675b8253ced
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M libcxx/include/__config
M libcxx/include/__type_traits/datasizeof.h
M libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp
Log Message:
-----------
[libc++] Fix __datasizeof_v for Clang17 and 18 in C++03 (#106832)
This also disables the use of `__datasizeof`, since it's currently
broken for empty types.
Commit: 24b6b82487f15dd9d6cbe8a716dd13a6808a2528
https://github.com/llvm/llvm-project/commit/24b6b82487f15dd9d6cbe8a716dd13a6808a2528
Author: Damyan Pepper <damyanp at microsoft.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
Log Message:
-----------
[NFC] Add llvm_unreachable to getRCPrefix (#106822)
Commit: 884d7c137a587fdd7549bd8a26f887bbeda0cc86
https://github.com/llvm/llvm-project/commit/884d7c137a587fdd7549bd8a26f887bbeda0cc86
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
R llvm/test/Transforms/SLPVectorizer/RISCV/unique-loads-insert-non-power-of-2.ll
Log Message:
-----------
Revert "[SLP]Check for the whole vector vectorization in unique scalars analysis"
This reverts commit b74e09cb20e6218320013b54c9ba2f5c069d44b9 after
post-commit review. The number of parts is calculated incorrectly.
Commit: 571c8c2c88122d318ed84cd9e948613e3f1aac5f
https://github.com/llvm/llvm-project/commit/571c8c2c88122d318ed84cd9e948613e3f1aac5f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
Log Message:
-----------
Revert "[SLP]Initial support for non-power-of-2 (but still whole register) number of elements in operands."
This reverts commit a3ea90ffbbe47d9a1b3eab03324f09d7b8e0dcb3 after the
post commit review. The number of parts is calculated incorrectly.
Commit: 126940bde3e48ad9bf0a6966fc473e22d4dade7d
https://github.com/llvm/llvm-project/commit/126940bde3e48ad9bf0a6966fc473e22d4dade7d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] Use DenseMap::{find,try_emplace} (NFC) (#107123)
I'm planning to deprecate and eventually remove
DenseMap::FindAndConstruct in favor of operator[].
Commit: 15fa3ba547bc3ee04af5c32b8f723a97e3feefd8
https://github.com/llvm/llvm-project/commit/15fa3ba547bc3ee04af5c32b8f723a97e3feefd8
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M bolt/lib/Profile/YAMLProfileReader.cpp
A bolt/test/X86/yaml-unknown-keys.test
M bolt/tools/merge-fdata/merge-fdata.cpp
Log Message:
-----------
[BOLT][YAML] Allow unknown keys in the input (#100824)
This ensures forward compatibility, where old BOLT versions can consume
the profile created by newer versions with extra keys.
Test Plan: added yaml-unknown-keys.test
Commit: eec1fac9b51d06c8afafe9952a20ba7cd4c3ce1c
https://github.com/llvm/llvm-project/commit/eec1fac9b51d06c8afafe9952a20ba7cd4c3ce1c
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
Log Message:
-----------
[Clang] Fix handling of placeholder variables name in init captures (#107055)
We were incorrectly not deduplicating results when looking up `_` which,
for a lambda init capture, would result in an ambiguous lookup.
The same bug caused some diagnostic notes to be emitted twice.
Fixes #107024
Commit: 1fbb6b4efc9e9d257f0f7e5065f40f9b9677ca7c
https://github.com/llvm/llvm-project/commit/1fbb6b4efc9e9d257f0f7e5065f40f9b9677ca7c
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
Log Message:
-----------
[LV] Prefer FLT_MIN/MAX for fmin/fmax reductions with ninf (#107141)
Analogous to 2c7786e94a1058bd4f96794a1d4f70dcb86e5cc5, cleanup a case
where the vectorizer is emitting a non-canonical identity value given
the available flags. We use largest/smallest value during ISEL, and VP
expansion, but not during vectorization.
Since the fmin/fmax/fminimum/fmaximum intrinsics don't require a start
value, this difference is only visible when masking of inactive lanes is
required.
Primary motivation of this change is simply to remove a difference
between version of code which reason about the identity value of a
reduction so I can kill all but one off.
In review, it was pointed out that this is actually a functional fix as well.
The old code used inf on a noinf reduction instruction - whose
result is poison! That wasn't the intent of the code.
Commit: 451a3135a7afece0b6e7605376ce208435605934
https://github.com/llvm/llvm-project/commit/451a3135a7afece0b6e7605376ce208435605934
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/DominanceFrontier.h
M llvm/include/llvm/Analysis/DominanceFrontierImpl.h
M llvm/include/llvm/CodeGen/MachineDominanceFrontier.h
Log Message:
-----------
[DominanceFrontier] Remove unused functions (#106913)
Commit: eb05e8fde1ebc4cda2106b1236620a8a89b36b7c
https://github.com/llvm/llvm-project/commit/eb05e8fde1ebc4cda2106b1236620a8a89b36b7c
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/www/c_status.html
Log Message:
-----------
[clang] [docs] Clarify the issue with compiler-rt on Windows/MSVC (#106875)
Compiler-rt does support Windows just fine, even if outdated docs pages
didn't list it as one of the supported OSes, this is being rectified in
https://github.com/llvm/llvm-project/pull/106874.
MinGW is another environment configuration on Windows, where compiler-rt
or libgcc is linked in automatically, so there's no issue with having
such builtins functions available.
For MSVC style environments, compiler-rt builtins do work just fine, but
Clang doesn't automatically link them in. See e.g.
https://discourse.llvm.org/t/improve-autolinking-of-compiler-rt-and-libc-on-windows-with-lld-link/71392
for a discussion on how to improve this situation. But none of that
issue is that compiler-rt itself wouldn't support Windows.
Commit: fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10
https://github.com/llvm/llvm-project/commit/fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] Don't add DWARF debug info when assembling .s with clang-cl /Z7 (#106686)
This fixes a regression from f58330cbe44598eb2de0cca3b812f67fea0a71ca.
That commit changed the clang-cl options /Zi and /Z7 to be implemented
as aliases of -g rather than having separate handling.
This had the unintended effect, that when assembling .s files with
clang-cl, the /Z7 option (which implies using CodeView debug info) was
treated as a -g option, which causes `ClangAs::ConstructJob` to pick up
the option as part of `Args.getLastArg(options::OPT_g_Group)`, which
sets the `WantDebug` variable.
Within `Clang::ConstructJob`, we check for whether explicit `-gdwarf` or
`-gcodeview` options have been set, and if not, we pick the default
debug format for the current toolchain. However, in `ClangAs`, if debug
info has been enabled, it always adds DWARF debug info.
Add similar logic in `ClangAs` - check if the user has explicitly
requested either DWARF or CodeView, otherwise look up the toolchain
default. If we (either implicitly or explicitly) should be producing
CodeView, don't enable the default `ClangAs` DWARF generation.
This fixes the issue, where assembling a single `.s` file with clang-cl,
with the /Z7 option, causes the file to contain some DWARF sections.
This causes the output executable to contain DWARF, in addition to the
separate intended main PDB file.
By having the output executable contain DWARF sections, LLDB only looks
at the (very little) DWARF info in the executable, rather than looking
for a separate standalone PDB file. This caused an issue with LLDB's
tests, https://github.com/llvm/llvm-project/issues/101710.
Commit: 3bd161e98d89d31696002994771b7761f1c74859
https://github.com/llvm/llvm-project/commit/3bd161e98d89d31696002994771b7761f1c74859
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
Log Message:
-----------
[LV] Honor forced scalars in setVectorizedCallDecision.
Similarly to dd94537b4, setVectorizedCallDecision also did not consider
ForcedScalars. This lead to VPlans not reflecting the decision by the
legacy cost model (cost computation would use scalar cost, VPlan would
have VPWidenCallRecipe).
To fix this, check if the call has been forced to scalar in
setVectorizedCallDecision.
Note that this requires moving setVectorizedCallDecision after
collectLoopUniforms (which sets ForcedScalars). collectLoopUniforms does
not depend on call decisions and can safely be moved.
Fixes https://github.com/llvm/llvm-project/issues/107051.
Commit: 70f3511adaea4d3a9f8fadb23e84f518cc0654ab
https://github.com/llvm/llvm-project/commit/70f3511adaea4d3a9f8fadb23e84f518cc0654ab
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] [test] Fix the debug-options-as.c test on macOS
Separate the path, which may begin with e.g. /Users, with "--" from
the other options, to make it clear that it is a path, not an
option.
This fixes a test from fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10.
Commit: ec8e1c623a78536b956cc2c1d42ae75c4024ad66
https://github.com/llvm/llvm-project/commit/ec8e1c623a78536b956cc2c1d42ae75c4024ad66
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
Log Message:
-----------
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
This avoids having isel patterns that emit two instrutions. It also
allows us to remove sext.w and slli+srli pairs by using fcvt.s.w(u) on
RV64.
Commit: 319e8cd201e6744199da377fba237dd276063e49
https://github.com/llvm/llvm-project/commit/319e8cd201e6744199da377fba237dd276063e49
Author: Ian Anderson <iana at apple.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/Sema/SemaAvailability.cpp
M clang/test/FixIt/fixit-availability-maccatalyst.m
M clang/test/FixIt/fixit-availability.mm
Log Message:
-----------
[Clang][Sema] clang generates incorrect fix-its for API_AVAILABLE (#105855)
Apple's API_AVAILABLE macro has its own notion of platform names which
are supported by \_\_API_AVAILABLE_PLATFORM_<name> macros. They don't
follow a consistent naming convention, but there's at least one that
matches a valid availability attribute platform name. Instead of
lowercasing the source spelling name, search for a defined macro and use
that in the fix-it.
Commit: cdab6ffd6d32566277f71d9733e4b21750ea38c8
https://github.com/llvm/llvm-project/commit/cdab6ffd6d32566277f71d9733e4b21750ea38c8
Author: weiguozhi <57237827+weiguozhi at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
Log Message:
-----------
[X86] Don't save/restore fp/bp around terminator (#106462)
In function spillFPBP we already try to skip terminator, but there is a
logic error, so when there is only terminator instruction in the MBB, it
still tries to save/restore fp/bp around it if the terminator clobbers
fp/bp, for example a tail call with ghc calling convention.
Now this patch really skips terminator even if it is the only
instruction in the MBB.
Commit: cbb5f03f5042aa6d7c5d17963eba192861c9165c
https://github.com/llvm/llvm-project/commit/cbb5f03f5042aa6d7c5d17963eba192861c9165c
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] [test] Fix the debug-options-as.c test on PowerPC
Use an explicit MSVC triple with an architecture that does
have proper handling for MSVC style targets.
This fixes a test from fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10.
Commit: 0ef7b1d21ca7ce55f1c8d3ec739e64775572e9cc
https://github.com/llvm/llvm-project/commit/0ef7b1d21ca7ce55f1c8d3ec739e64775572e9cc
Author: Joshua Baehring <98630690+JoshuaMBa at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/secondary.h
Log Message:
-----------
[scudo] Update secondary cache released pages bound. (#106466)
`MaxReleasedCachePages` has been set to 4. Initially, in #105009 , we
set `MaxReleasedCachePages` to 0 so that the partial chunk heuristic
could be introduced incrementally as we observed its impact on retrieval
order and more generally, performance.
Co-authored-by: Joshua Baehring <josh.baehring at yale.edu>
Commit: 334d1238aafa8ca017d433caaf8f6e00f2622111
https://github.com/llvm/llvm-project/commit/334d1238aafa8ca017d433caaf8f6e00f2622111
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
Log Message:
-----------
[HLSL] Adjust resource binding diagnostic flags code (#106657)
Adjust register binding diagnostic flags code in a couple of ways:
- Store the resource class in the Flags struct to avoid duplicated
scanning for HLSLResourceClassAttribute
- Avoid unnecessary indirection when converting resource class to
register type
- Remove recursion and reduce duplicated code
Also fixes a case where struct with an array was incorrectly diagnosed
unfit for `c` register binding.
This will also simplify work that is needed to be done in this area for
llvm/llvm-project#104861.
Commit: dfc21acdfa0eb7f6f6bb563445959fb18ea863da
https://github.com/llvm/llvm-project/commit/dfc21acdfa0eb7f6f6bb563445959fb18ea863da
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] Convert global allocation for pinned variable (#106807)
ALLOCATE/DEALLOCATE statements for module allocatable variable with the
pinned attribute can be lowered to the standard runtime call and do not
need further action since these variables will have a unique descriptor
that is on the host.
Commit: b2dabd2b06cb0ca5ea534bafe33c5cff5521be18
https://github.com/llvm/llvm-project/commit/b2dabd2b06cb0ca5ea534bafe33c5cff5521be18
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[Sema] Fix warnings
This patch fixes:
clang/lib/Sema/SemaHLSL.cpp:838:12: error: unused variable
'TheVarDecl' [-Werror,-Wunused-variable]
clang/lib/Sema/SemaHLSL.cpp:840:19: error: unused variable
'CBufferOrTBuffer' [-Werror,-Wunused-variable]
Commit: d966d4708fe5084e47ca3d9d411935d6870aefff
https://github.com/llvm/llvm-project/commit/d966d4708fe5084e47ca3d9d411935d6870aefff
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/SupportFile.h
Log Message:
-----------
[lldb] Make SupportFile's FileSpec and Checksum const (NFC)
Commit: 98bde7fd872c10e49035d5dc5d2f2b44489f6a07
https://github.com/llvm/llvm-project/commit/98bde7fd872c10e49035d5dc5d2f2b44489f6a07
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Symbol/LineTable.cpp
Log Message:
-----------
[lldb] Avoid FileSpec indirection where we can use SupportFiles directly
Now that more parts of LLDB know about SupportFiles, avoid going through
FileSpec (and losing the Checksum in the process). Instead, use the
SupportFile directly.
Commit: 53d3d1ab9abf28e92a27fce0a99ae83720d27d75
https://github.com/llvm/llvm-project/commit/53d3d1ab9abf28e92a27fce0a99ae83720d27d75
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] Avoid two successive hash lookups on the same key (#107143)
This patch replaces the find-try_emplace sequence with just one call
to try_emplace, thereby avoiding two successive hash lookups on the
same key. I am not using the "inserted" boolean from try_emplace to
preserve the original behavior (that is, before PR 107123) that checks
to see if the value is nullptr or not.
Commit: db8ca88f578c2270ab2d461fa0dd5e7a1d1bad43
https://github.com/llvm/llvm-project/commit/db8ca88f578c2270ab2d461fa0dd5e7a1d1bad43
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/utils/TableGen/VTEmitter.cpp
Log Message:
-----------
[TableGen] Print all arguments to GET_VT_ATTR in the comment in GenVT.inc. NFC
Commit: 18cf14efe3e82b2343817fd174bcac48244c8f50
https://github.com/llvm/llvm-project/commit/18cf14efe3e82b2343817fd174bcac48244c8f50
Author: Scott Linder <Scott.Linder at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/docs/conf.py
M llvm/docs/conf.py
Log Message:
-----------
[Docs] Use cacheable myst_heading_slug_func value
Avoid creating an uncacheable conf variable by using a string instead of
a function reference. Also has the effect of avoiding triggering the
"config.cache" sphinx warning.
Requires myst_parser 0.19.0 (specifically
https://github.com/executablebooks/MyST-Parser/pull/696) which is over a
year old by now. Do we mandate any minimum version for these
dependencies?
Commit: db3792b87a4fd759e336c44946a3e2ec0008c993
https://github.com/llvm/llvm-project/commit/db3792b87a4fd759e336c44946a3e2ec0008c993
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
Log Message:
-----------
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
All of the test changes are because integer type legalization prefers to promote
fp_to_uint to fp_to_sint if neither is "Legal".
Commit: 7d3b81d06f96bc27673f31a7bd7d141ce4a2777b
https://github.com/llvm/llvm-project/commit/7d3b81d06f96bc27673f31a7bd7d141ce4a2777b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb] Bump the lldb-dap version number
Bump the lldb-dap version number so that we can publish and updated
version in the Visual Studio Marketplace.
Commit: 98bb354a0add4aeb614430f48a23f87992166239
https://github.com/llvm/llvm-project/commit/98bb354a0add4aeb614430f48a23f87992166239
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
Log Message:
-----------
[SLP]Fix PR107037: correctly track origonal/modified after vectorizations reduced values
Need to correctly track reduced values with multiple uses in the same
reduction emission attempt. Otherwise, the number of the reuses might be
calculated incorrectly, and may cause compiler crash.
Fixes https://github.com/llvm/llvm-project/issues/107037
Commit: d3c10b51a99d4476261f57ceaa7db60960cd5493
https://github.com/llvm/llvm-project/commit/d3c10b51a99d4476261f57ceaa7db60960cd5493
Author: Peter Lafreniere <peter at n8pjl.ca>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/test/CodeGen/M68k/Arith/add.ll
R llvm/test/CodeGen/M68k/Arith/sext-i1.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
A llvm/test/CodeGen/M68k/Data/link-unlnk.ll
A llvm/test/CodeGen/M68k/Data/load-extend.ll
A llvm/test/CodeGen/M68k/Data/load-imm.ll
A llvm/test/CodeGen/M68k/Data/sext-i1.ll
R llvm/test/CodeGen/M68k/link-unlnk.ll
R llvm/test/CodeGen/M68k/load-extend.ll
Log Message:
-----------
[M68k] Introduce more MOVI cases (#98377)
Add three more special cases for loading registers with immediates.
The first allows values in the range of [-255, 255] to be loaded with
MOVEQ, even if the register is more than 8 bits and the sign extention
is unwanted. This is done by loading the bitwise complement of the
desired value, then performing a NOT instruction on the loaded register.
This special case is only used when a simple MOVEQ cannot be used, and
is only used for 32 bit data registers. Address registers cannot support
MOVEQ, and the two-instruction sequence is no faster or smaller than a
plain MOVE instruction when loading 16 bit immediates on the 68000, and
likely slower for more sophisticated microarchitectures. However, the
instruction sequence is both smaller and faster than the corresponding
MOVE instruction for 32 bit register widths.
The second special case is for zeroing address registers. This simply
expands to subtracting a register with itself, consuming one instruction
word rather than 2-3, with a small improvement in speed as well.
The last special case is for assigning sign-extended 16-bit values to a
full address register. This takes advantage of the fact that the movea.w
instruction sign extends the output, permitting the immediate to be
smaller. This is similar to using lea with a 16-bit address, which is
not added in this patch as 16-bit absolute addressing is not yet
implemented.
This is a v2 submission of #90817. It also creates a 'Data' test
directory to better align with the backend's tablegen layout.
Commit: 1c874bbbd67c5795113fa307512ea514f06dac29
https://github.com/llvm/llvm-project/commit/1c874bbbd67c5795113fa307512ea514f06dac29
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/half-select-icmp.ll
Log Message:
-----------
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
Select only needs branches and moves so we don't need to promote it.
Promoting would canonicalize NaNs which select shouldn't do.
Commit: b24a304435632710bb54a0cd9cda1757abb8c160
https://github.com/llvm/llvm-project/commit/b24a304435632710bb54a0cd9cda1757abb8c160
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
Log Message:
-----------
[lld-macho] Always store symbol name length eagerly (NFC) (#106906)
The only instance where we weren't already passing a `StringRef` with a
known length to `Symbol`'s constructor is where the argument is a string
literal. Even in that case, lazy `strlen` calls don't make sense, as the
compiler can constant-evaluate the `StringRef(const char*)` constructor.
For symbols that go into the symbol table we need the length when
calculating the hash anyway. We could get away with not calling
`getName()` for local symbols, but the total contribution of `strlen` to
the run time is already below 1%, so that would just complicate the code
for a negligible benefit.
Commit: 3209766608d14fbb0add96916a28c3f98fed9460
https://github.com/llvm/llvm-project/commit/3209766608d14fbb0add96916a28c3f98fed9460
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Transforms/IPO/ModuleInliner.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
A llvm/test/Analysis/CtxProfAnalysis/inline.ll
A llvm/test/Analysis/CtxProfAnalysis/json_equals.py
M llvm/test/Analysis/CtxProfAnalysis/load.ll
M llvm/unittests/Transforms/Utils/CallPromotionUtilsTest.cpp
Log Message:
-----------
[ctx_prof] Add Inlining support (#106154)
Add an overload of `InlineFunction` that updates the contextual profile. If there is no contextual profile, this overload is equivalent to the non-contextual profile variant.
Post-inlining, the update mainly consists of:
- making the PGO instrumentation of the callee "the caller's": the owner function (the "name" parameter of the instrumentation instructions) becomes the caller, and new index values are allocated for each of the callee's indices (this happens for both increment and callsite instrumentation instructions)
- in the contextual profile:
- each context corresponding to the caller has its counters updated to incorporate the counters inherited from the callee at the inlined callsite. Counter values are copied as-is because no scaling is required since the profile is contextual.
- the contexts of the callee (at the inlined callsite) are moved to the caller.
- the callee context at the inlined callsite is deleted.
Commit: dce73e115e11cf75c0e50fb96a9ba046c880838e
https://github.com/llvm/llvm-project/commit/dce73e115e11cf75c0e50fb96a9ba046c880838e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
R llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
Log Message:
-----------
Revert "[SLP]Fix PR107037: correctly track origonal/modified after vectorizations reduced values"
This reverts commit 98bb354a0add4aeb614430f48a23f87992166239 to fix
buildbots https://lab.llvm.org/buildbot/#/builders/155/builds/2056 and https://lab.llvm.org/buildbot/#/builders/11/builds/4407
Commit: 18263c319092b878f25dd4025830f8e6691245d4
https://github.com/llvm/llvm-project/commit/18263c319092b878f25dd4025830f8e6691245d4
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_context.cpp
Log Message:
-----------
[compiler-rt][rtsan] Add scoped reporting lock (#107167)
Uses a static lock to ensure multiple threads reporting issues at the
same time don't have printing collisions. This isn't so important now,
but will be with continue mode in the future.
Commit: b076f6640e3c2781410588f4a8e4ccfeed8eb606
https://github.com/llvm/llvm-project/commit/b076f6640e3c2781410588f4a8e4ccfeed8eb606
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Target/TargetProperties.td
M lldb/test/API/functionalities/memory/big-read/TestMemoryReadMaximumSize.py
Log Message:
-----------
[lldb] Remove limit on max memory read size (#105765)
`memory read` will return an error if you try to read more than 1k bytes
in a single command, instructing you to set
`target.max-memory-read-size` or use `--force` if you intended to read
more than that. This is a safeguard for a command where people are being
explicit about how much memory they would like lldb to read (either to
display, or save to a file) and is an annoyance every time you need to
read more than a small amount. If someone confuses the --count argument
with the start address, lldb may begin dumping gigabytes of data but I'd
rather that behavior than requiring everyone to special-case their way
around a common use case.
I don't want to remove the setting because many people have added (much
larger) default max read sizes to their ~/.lldbinit files after hitting
this behavior. Another option would be to stop reading/using the value
in Target.cpp, but I see no harm in leaving the setting if someone
really does prefer to have a small cap on their memory read size.
Commit: 3e8840ba71bfcceeb598c2ca28d2d8784e24ba1e
https://github.com/llvm/llvm-project/commit/3e8840ba71bfcceeb598c2ca28d2d8784e24ba1e
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/VectorBuilder.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/IR/VectorBuilder.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
Remove "Target" from createXReduction naming [nfc]
Despite the stale comments, none of these actually use TTI, and they're
solely generating standard LLVM IR.
Commit: eaa95a1c2bd38332c1a4e634595f29d22b28ffea
https://github.com/llvm/llvm-project/commit/eaa95a1c2bd38332c1a4e634595f29d22b28ffea
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/test/CXX/drs/cwg24xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add test for CWG2486 (`noexcept` and function pointer conversion) (#107131)
[CWG2486](https://cplusplus.github.io/CWG/issues/2486.html) "Call to
`noexcept` function via `noexcept(false)` pointer/lvalue" allows
`noexcept` functions to be called via `noexcept(false)` pointers or
values. There appears to be no implementation divergence whatsoever:
https://godbolt.org/z/3afTfeEM8. That said, in C++14 and earlier we do
not issue all the diagnostics we issue in C++17 and newer, so I'm
specifying the status of the issue accordingly.
Commit: 83ad644afaac23577e3563d3ec1fac1b1fde37f4
https://github.com/llvm/llvm-project/commit/83ad644afaac23577e3563d3ec1fac1b1fde37f4
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.def
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10_2_512bf16intrin.h
A clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c
A clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
A llvm/test/CodeGen/X86/avx10.2-fma-commute.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt
A llvm/test/MC/X86/avx10.2-bf16-32-att.s
A llvm/test/MC/X86/avx10.2-bf16-32-intel.s
A llvm/test/MC/X86/avx10.2-bf16-64-att.s
A llvm/test/MC/X86/avx10.2-bf16-64-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86][AVX10.2] Support AVX10.2-BF16 new instructions. (#101603)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
Commit: 814aa432abf8e9f644903061029e6e27f6a418a8
https://github.com/llvm/llvm-project/commit/814aa432abf8e9f644903061029e6e27f6a418a8
Author: vporpo <vporpodas at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantAggregate (#107136)
This patch implements sandboxir:: ConstantAggregate, ConstantStruct,
ConstantArray and ConstantVector, mirroring LLVM IR.
Commit: 48bc8b0f7f49f5b23884a0d9d21056ec0bfffe24
https://github.com/llvm/llvm-project/commit/48bc8b0f7f49f5b23884a0d9d21056ec0bfffe24
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 83ad644afaac
Commit: ff0f2011e475141454028bce9cf7c6ff37a49620
https://github.com/llvm/llvm-project/commit/ff0f2011e475141454028bce9cf7c6ff37a49620
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
Log Message:
-----------
[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)
Previously, if Zfbfmin/Zfhmin were enabled, we only handled
build_vectors that could be turned into splat_vectors. We promoted them
to f32 splats by extending in the scalar domain and narrowing in the
vector domain.
This patch fixes a crash where we failed to account for whether the f32
vector type fit in LMUL<=8.
Because the new lowering occurs after type legalization, we have to be
careful to use XLenVT for the scalar integer type and use custom cast
nodes.
Commit: f1615e32379ff1ea125a8b3ac8792c3e0b5e6f2c
https://github.com/llvm/llvm-project/commit/f1615e32379ff1ea125a8b3ac8792c3e0b5e6f2c
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
Log Message:
-----------
[WebAssembly] Remove Kind argument from WebAssemblyOperand (NFC) (#107157)
The `Kind` argument does not need to passed separately.
Commit: c8763f04bf2162d3f0f4f967dfeb2f0feda0c75b
https://github.com/llvm/llvm-project/commit/c8763f04bf2162d3f0f4f967dfeb2f0feda0c75b
Author: Yun-Fly <yunfei.song at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
[mlir][tensor] Fix consumer fusion for `tensor.pack` without explicit `outer_dims_perm` attribute (#106687)
Commit: 99f02a874984f2b79c3fbd8ae6bbceb7366521ad
https://github.com/llvm/llvm-project/commit/99f02a874984f2b79c3fbd8ae6bbceb7366521ad
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A clang/test/CXX/drs/cwg1818.cpp
M clang/test/CXX/drs/cwg18xx.cpp
A clang/test/CXX/drs/cwg563.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add tests for CWG issues about language linkage (#107019)
This patch covers Core issues about language linkage during declaration
matching resolved in
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html),
namely [CWG563](https://cplusplus.github.io/CWG/issues/563.html) and
[CWG1818](https://cplusplus.github.io/CWG/issues/1818.html).
[CWG563](https://cplusplus.github.io/CWG/issues/563.html) "Linkage
specification for objects"
-----------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
> [CWG563](https://cplusplus.github.io/CWG/issues/563.html) is resolved
by simplifications that follow its suggestions.
Wording ([[dcl.link]/5](https://eel.is/c++draft/dcl.link#5)):
> In a
[linkage-specification](https://eel.is/c++draft/dcl.link#nt:linkage-specification),
the specified language linkage applies to the function types of all
function declarators and to all functions and variables whose names have
external linkage[.](https://eel.is/c++draft/dcl.link#5.sentence-5)
Now the wording clearly says that linkage-specification applies to
variables with external linkage.
[CWG1818](https://cplusplus.github.io/CWG/issues/1818.html) "Visibility
and inherited language linkage"
------------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
>
[CWG386](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#386),
[CWG1839](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1839),
[CWG1818](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1818),
[CWG2058](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#2058),
[CWG1900](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1900),
and Richard’s observation in [“are non-type names ignored in a
class-head-name or
enum-head-name?”](http://lists.isocpp.org/core/2017/01/1604.php) are
resolved by describing the limited lookup that occurs for a
declarator-id, including the changes in Richard’s [proposed resolution
for
CWG1839](http://wiki.edg.com/pub/Wg21cologne2019/CoreWorkingGroup/cwg1839.html)
(which also resolves CWG1818 and what of CWG2058 was not resolved along
with CWG2059) and rejecting the example from
[CWG1477](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#1477).
Wording ([[dcl.link]/6](https://eel.is/c++draft/dcl.link#6)):
> A redeclaration of an entity without a linkage specification inherits
the language linkage of the entity and (if applicable) its
type[.](https://eel.is/c++draft/dcl.link#6.sentence-2).
Answer to the question in the example is `extern "C"`, and not linkage
mismatch. Further analysis of the example is provided as inline comments
in the test itself. Note that https://eel.is/c++draft/dcl.link#7 does
NOT apply in this example, as it's focused squarely at declarations that
are already known to have C language linkage, and declarations of
variables in the global scope.
Commit: b057e16740311b9c690c0c991c48b5087bf24d9a
https://github.com/llvm/llvm-project/commit/b057e16740311b9c690c0c991c48b5087bf24d9a
Author: Reid Kleckner <rnk at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemorySSA.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/OperandTraits.h
M llvm/include/llvm/IR/Operator.h
M llvm/include/llvm/IR/User.h
M llvm/lib/IR/ConstantsContext.h
Log Message:
-----------
[IR] Remove unused MINARITY operand trait tpl args, NFC (#107165)
These don't look like they've been used since the original 'use-diet'
branch was merged in 2008 ( f6caff66a1bfa6464e6a17c0bcfcf06a09a9b909)
Commit: ed220e15718498d0f854f1044ddcbfee00739aa7
https://github.com/llvm/llvm-project/commit/ed220e15718498d0f854f1044ddcbfee00739aa7
Author: Elvis Wang <110374989+ElvisWang123 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan][NFC] Implement `VPWidenMemoryRecipe::computeCost()`. (#105614)
In this patch, we implement the `computeCost()` function in
`VPWidenMemoryRecipe`.
Commit: 9b5971ad0355d43a9bd37b1067d93ff8b08eba81
https://github.com/llvm/llvm-project/commit/9b5971ad0355d43a9bd37b1067d93ff8b08eba81
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-extmul.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
[AArch64][GlobalISel] Lower G_BUILD_VECTOR to G_INSERT_VECTOR_ELT (#105686)
The lowering happens in post-legalizer lowering if any source registers
from G_BUILD_VECTOR are not constants.
Add pattern pragment setting `scalar_to_vector ($src)` asequivalent to
`vector_insert (undef), ($src), (i61 0)`
Commit: 12c0823d67a8d5a61d6430aac609ef5e468267a6
https://github.com/llvm/llvm-project/commit/12c0823d67a8d5a61d6430aac609ef5e468267a6
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/tools/clang-format/git-clang-format.bat
Log Message:
-----------
[clang-format] Handle spaces in file paths in git-clang-format.bat (#107041)
This patch is provided by @jeliebig.
Fixes #107017.
Commit: a27ff17034d66d852ba83be7d237d6a623cb4ff4
https://github.com/llvm/llvm-project/commit/a27ff17034d66d852ba83be7d237d6a623cb4ff4
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a regression in annotating ObjCBlockLParen (#107021)
Fixes #106994.
Commit: b55186eefd73b3848e01c8471c47a9354969d652
https://github.com/llvm/llvm-project/commit/b55186eefd73b3848e01c8471c47a9354969d652
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/test/Preprocessor/init-ppc.c
M clang/test/Preprocessor/init-ppc64.c
Log Message:
-----------
[clang][Driver] Define soft float macros for PPC. (#106012)
Fixes #105972.
Co-authored-by: Qiu Chaofan <qcf at ecnelises.com>
Commit: 8d0816615f920b0783bafa903804b9e2a2fa4e91
https://github.com/llvm/llvm-project/commit/8d0816615f920b0783bafa903804b9e2a2fa4e91
Author: yifeizh2 <yifei.zhang at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[MLIR][Tensor] Fix source/dest type check in UnPackOp canonicalize (#106094)
Fix `RankedTensorType` equality check in unpack op canonicalization.
Commit: 812c96e8b9354e5e84d513f5b03172db5ad3b491
https://github.com/llvm/llvm-project/commit/812c96e8b9354e5e84d513f5b03172db5ad3b491
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Handle pointer/reference in macro definitions (#107074)
A macro definition needs its own scope stack in the annotator, so we add
the MacroBodyScopes stack and use ScopeStack to refer to it when in the
macro definition body.
Also, we need to have a scope type for a child block because its parent
line is parsed (and thus the scope type for the braces is popped off the
scope stack) before the lines in the child block are.
Fixes #99271.
Commit: f4b9839d6f7c9ec2967a42f2d5546a2a2ae77ca4
https://github.com/llvm/llvm-project/commit/f4b9839d6f7c9ec2967a42f2d5546a2a2ae77ca4
Author: Longsheng Mou <moulongsheng at huawei.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Conversion/TensorToSPIRV/TensorToSPIRV.cpp
M mlir/test/Conversion/TensorToSPIRV/tensor-ops-to-spirv.mlir
Log Message:
-----------
[mlir][TensorToSPIRV] Add type check for `tensor.extract` in TensorToSPIRV (#107110)
This patch add a type check for `tensor.extract` in TensorToSPIRV.
Only convert `tensor.extract` with supported element type. Fix #74466.
Commit: 37263b6c6741894ffbc0f61979c5c85db515ef2d
https://github.com/llvm/llvm-project/commit/37263b6c6741894ffbc0f61979c5c85db515ef2d
Author: Longsheng Mou <moulongsheng at huawei.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
[mlir][tosa] Add verifier for `tosa.pad` (#106351)
This patch adds verifier to `tosa.pad` which fixes a crash. `tosa.pad`
expect:
- same input and output tensor rank.
- 'padding' tensor rank equal to 2.
Fix #106168.
Commit: a628bc3c2e7314e4b7c9af0d10cf39a70c731d15
https://github.com/llvm/llvm-project/commit/a628bc3c2e7314e4b7c9af0d10cf39a70c731d15
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
Log Message:
-----------
[AArch64] Fix a warning
This patch fixes:
lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc:506:14:
error: unused variable 'GIMatchData_matchinfo'
[-Werror,-Wunused-variable]
Commit: 9a17a6016d02afa6e973f141ab1cada68571f2d2
https://github.com/llvm/llvm-project/commit/9a17a6016d02afa6e973f141ab1cada68571f2d2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Log Message:
-----------
[PowerPC] Use DenseMap::operator[] (NFC) (#107044)
Commit: f15e3e58c59b4d31eee24fa9debc5dfad0c20028
https://github.com/llvm/llvm-project/commit/f15e3e58c59b4d31eee24fa9debc5dfad0c20028
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
[CGOpenMPRuntime] Use DenseMap::operator[] (NFC) (#107158)
I'm planning to deprecate DenseMap::FindAndConstruct in favor of
DenseMap::operator[].
Commit: 86627149f6fd5148311b7b0aa1c7195a05a5d6a8
https://github.com/llvm/llvm-project/commit/86627149f6fd5148311b7b0aa1c7195a05a5d6a8
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
A llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
A llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
Log Message:
-----------
[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)
Any SGPR read by a VALU can potentially obscure SALU writes to the same
register.
Insert s_wait_alu instructions to mitigate the hazard on affected paths.
Compute a global cache of SGPRs with any VALU reads and use this to
avoid inserting mitigation for SGPRs never accessed by VALUs.
To avoid excessive search when compile time is priority implement
secondary mode where all SALU writes are mitigated.
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: a5ce66423bfff6f2185e5fe48bc6ffc0ade7df4d
https://github.com/llvm/llvm-project/commit/a5ce66423bfff6f2185e5fe48bc6ffc0ade7df4d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
Log Message:
-----------
[RISCV] Remove RISCVISD::FP_ROUND_BF16.
Use isel patterns on regular FP_ROUND. For double->bf16 we need
to emit two instructions. Note the double->bf16 conversion does
double rounding, but I don't know a good way to fix that.
Commit: 0ad6cee926865d7210eed9e67bfb20dce19c6633
https://github.com/llvm/llvm-project/commit/0ad6cee926865d7210eed9e67bfb20dce19c6633
Author: Elvis Wang <110374989+ElvisWang123 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/cast.ll
Log Message:
-----------
[RISCV] Fix missing `i64` to `double` tests in the cast.ll. (NFC) (#106972)
Commit: 8b28e2ebb36d72cfffe04904e3e1b9fdfa36ef94
https://github.com/llvm/llvm-project/commit/8b28e2ebb36d72cfffe04904e3e1b9fdfa36ef94
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
Log Message:
-----------
[WebAssembly] Rename legacy EH tests (#107166)
Give each test in `cfg-stackify-eh-legacy.ll` a name rather than
something like `test5`, because I plan to copy many of these test into a
new file that tests for the new EH (exnref) and some of the tests here
are not applicable to the new EH so the numbering will be different,
which can make things confusing.
Also this removes `test_` prefixes in the test function names in
`exception-legacy.ll`, because, well, we all know they are tests.
Commit: 9fef09fd2918e7d8c357b98a9a798fe207941f73
https://github.com/llvm/llvm-project/commit/9fef09fd2918e7d8c357b98a9a798fe207941f73
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
M clang/test/CodeGen/X86/x86-atomic-double.c
M clang/test/CodeGen/X86/x86-atomic-long_double.c
Log Message:
-----------
[Clang][CodeGen] Fix type for atomic float incdec operators (#107075)
`llvm::ConstantFP::get(llvm::LLVMContext&, APFloat(float))` always
returns a f32 constant.
Fix https://github.com/llvm/llvm-project/issues/107054.
Commit: 6c607cfb2c2d8acd2b92d7ed8106ab1e4fc0d79d
https://github.com/llvm/llvm-project/commit/6c607cfb2c2d8acd2b92d7ed8106ab1e4fc0d79d
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
Log Message:
-----------
[RISCV] Preserve tail agnostic policy in foldVMV_V_V (#105788)
This patch helps avoid regressions in an upcoming patch by making sure
we don't accidentally lose a tail agnostic policy when folding a vmv.v.v
into its source.
The previous comment about RISCVInsertVSETVLI relaxing the policy didn't
take into account the fact that there's a policy operand on vmv.v.v,
which can be tail agnostic.
If the tail is agnostic (via either the policy operand or the passthru
being undef) and vmv.v.v's VL <= Src's VL, then Src's tail can be made
agnostic.
Commit: c94bd96c277e0b48e198fdc831bb576d9a04aced
https://github.com/llvm/llvm-project/commit/c94bd96c277e0b48e198fdc831bb576d9a04aced
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGStmt.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
Log Message:
-----------
[Clang][CodeGen] Don't emit assumptions if current block is unreachable. (#106936)
Fixes https://github.com/llvm/llvm-project/issues/106898.
When emitting an infinite loop, clang codegen will delete the whole
block and leave builder's current block as nullptr:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/clang/lib/CodeGen/CGStmt.cpp#L597-L600
Then clang will create `zext (icmp slt %a, %b)` without parent block for
`a < b`. It will crash here:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/clang/lib/CodeGen/CGExprScalar.cpp#L416-L420
Even if we disabled this optimization, it still crashes in
`Builder.CreateAssumption`:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/llvm/lib/IR/IRBuilder.cpp#L551-L561
This patch disables assumptions emission if current block is null.
Commit: 3e798476de466e8a051d3e753db379731a8d9705
https://github.com/llvm/llvm-project/commit/3e798476de466e8a051d3e753db379731a8d9705
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
Log Message:
-----------
[LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32 when we don't have Zvfh. (#106652)
The fp_extend will canonicalize NaNs which is not the semantics of
FNEG/FABS/FCOPYSIGN.
For fixed vectors I'm scalarizing due to test changes on other targets
where the scalarization is expected. I will try to address in a follow
up.
For scalable vectors, we bitcast to integer and use integer logic ops.
Commit: 41402c6a8aa3a4336122bdb4530fb05538efedba
https://github.com/llvm/llvm-project/commit/41402c6a8aa3a4336122bdb4530fb05538efedba
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
Log Message:
-----------
[RISCV][GISel] Use CCValAssign::getCustomReg for converting f16/f32<->GPR. (#105700)
This gives us much better control of the generated code for GISel. I've
tried to closely match the current gisel code, but it looks like we had
2 layers of G_ANYEXT in some cases before.
SelectionDAG now checks needsCustom() instead of detecting the special
cases in the Bitcast handler.
Unfortunately, IRTranslator for bitcast still generates copies between
register classes of different sizes. Because of this we can't handle
i16<->f16 bitcasts without crashing. Not sure if I should teach
RISCVInstrInfo::copyPhysReg to allow copies between FPR16 and GPR or if
I should convert the copies to instructions in GISel.
Commit: 4a44898be5d46694b59aa411f2b45a52f2ce8411
https://github.com/llvm/llvm-project/commit/4a44898be5d46694b59aa411f2b45a52f2ce8411
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
Log Message:
-----------
[RISCV] Add passthru to vmv.v.v intrinsic tests. NFC
This prevents them from being optimized away in an upcoming peephole
Commit: 3449ed8dece600f387357b71ff74ae4bc46828b6
https://github.com/llvm/llvm-project/commit/3449ed8dece600f387357b71ff74ae4bc46828b6
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
Revert "[clang-format] Correctly annotate braces in macro definition (#106662)"
This reverts commit 0fa78b6c7bd43c2498700a98c47a02cf4fd06388 due to
regression.
Fixes #107096.
Commit: 7deda4ed0c712fb830d25f4e3090ff04f7adbcf9
https://github.com/llvm/llvm-project/commit/7deda4ed0c712fb830d25f4e3090ff04f7adbcf9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Use MCRegister for variables returned from AllocateReg. NFC
Avoids a cast from Register to MCRegister for the CCValAssign
functions.
Commit: 06286832db0c4ee1899f9cee1b8f6234e45f16c7
https://github.com/llvm/llvm-project/commit/06286832db0c4ee1899f9cee1b8f6234e45f16c7
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
Reland "Revert "AtomicExpand: Allow incrementally legalizing atomicrmw"" (#106793)
Reverts llvm/llvm-project#106792
The first commit of PR is pure revert, the rest is a possible fix.
Commit: 427e202a401514cb28bf2ca621baae8e1b2f552f
https://github.com/llvm/llvm-project/commit/427e202a401514cb28bf2ca621baae8e1b2f552f
Author: Princeton Ferro <princetonferro at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Support/APInt.cpp
Log Message:
-----------
[APInt] improve initialization performance (#106945)
The purpose is to save an extra memset in both cases:
1. When `int64_t(val) < 0`, zeroing out is redundant as the subsequent
for-loop will initialize to `val .. 0xFFFFF ....`. Instead we should
only create an uninitialized buffer, and transform the slow for-loop
into a memset to initialize the higher words to `0xFF`.
2. In the other case, first we create an uninitialized array (`new
int64_t[]`) and _then_ we zero it out with `memset`. But this can be
combined in one operation with `new int64_t[]()`, which
default-initializes the array.
On one example where use of APInt was heavy, this improved compile time
by 1%.
Commit: 4bccb01355edcfedacafede3e7878d74e2b0a28f
https://github.com/llvm/llvm-project/commit/4bccb01355edcfedacafede3e7878d74e2b0a28f
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaCXX/source_location.cpp
Log Message:
-----------
[Clang] Workaround dependent source location issues (#106925)
In #78436 we made some SourceLocExpr dependent to
deal with the fact that their value should reflect the name of
specialized function - rather than the rtemplate in which they are first
used.
However SourceLocExpr are unusual in two ways
- They don't depend on template arguments
- They morally depend on the context in which they are used (rather than
called from).
It's fair to say that this is quite novels and confuses clang. In
particular, in some cases, we used to create dependent SourceLocExpr and
never subsequently transform them, leaving dependent objects in
instantiated functions types. To work around that we avoid replacing
SourceLocExpr when we think they could remain dependent.
It's certainly not perfect but it fixes a number of reported bugs, and
seem to only affect scenarios in which the value of the SourceLocExpr
does not matter (overload resolution).
Fixes #106428
Fixes #81155
Fixes #80210
Fixes #85373
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: de37da8e37c4c9042563e186068adca98bf59e07
https://github.com/llvm/llvm-project/commit/de37da8e37c4c9042563e186068adca98bf59e07
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/MachineOutliner.cpp
A llvm/test/CodeGen/AArch64/machine-outliner-bundle.mir
Log Message:
-----------
[MachineOutliner] Preserve instruction bundles (#106402)
When the machine outliner copies instructions from a source function
into an outlined function, it was doing it using `CloneMachineInstr`,
which is documented as not preserving the interior of any instruction
bundle. So outlining code that includes an instruction bundle would
fail, because in the outlined version, the bundle would be empty, so
instructions would go missing in the move.
This occurs when any bundled instruction appears in the outlined code,
so there was no need to construct an unusual test case: I've just copied
a function from the existing `stp-opt-with-renaming.mir`, which happens
to contain an SVE instruction bundle. Including two identical copies of
that function makes the outliner merge them, and then we check that it
didn't destroy the interior of the bundle in the process.
Commit: 01e56849001b4ace984e9557abc82bc051e03677
https://github.com/llvm/llvm-project/commit/01e56849001b4ace984e9557abc82bc051e03677
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCXX/attr-lifetimebound.cpp
Log Message:
-----------
[clang] Respect the lifetimebound in assignment operator. (#106997)
Fixes #106372
Commit: a55e10693d8772e6cc83b240a8b041eeb7fcab92
https://github.com/llvm/llvm-project/commit/a55e10693d8772e6cc83b240a8b041eeb7fcab92
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M bolt/lib/Profile/YAMLProfileReader.cpp
A bolt/test/X86/yaml-unknown-keys.test
M bolt/tools/merge-fdata/merge-fdata.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/BuiltinsX86.def
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10_2_512bf16intrin.h
A clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAvailability.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/constexpr-frame-describe.cpp
M clang/test/Analysis/mmap-writeexec.c
M clang/test/Analysis/stack-addr-ps.cpp
A clang/test/CXX/drs/cwg1818.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg24xx.cpp
A clang/test/CXX/drs/cwg563.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
A clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c
A clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M clang/test/CodeGen/X86/x86-atomic-double.c
M clang/test/CodeGen/X86/x86-atomic-long_double.c
M clang/test/CodeGen/pgo-force-function-attrs.ll
M clang/test/Driver/debug-options-as.c
M clang/test/FixIt/fixit-availability-maccatalyst.m
M clang/test/FixIt/fixit-availability.mm
M clang/test/Modules/no-local-decl-in-reduced-bmi.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview-std.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview.cppm
M clang/test/Modules/unreached-static-entities.cppm
M clang/test/Preprocessor/bpf-predefined-macros.c
M clang/test/Preprocessor/init-ppc.c
M clang/test/Preprocessor/init-ppc64.c
M clang/test/SemaCXX/attr-lifetimebound.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
M clang/test/SemaCXX/extern-c.cpp
M clang/test/SemaCXX/source_location.cpp
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
M clang/tools/clang-format/git-clang-format.bat
M clang/tools/driver/CMakeLists.txt
M clang/unittests/Driver/SimpleDiagnosticConsumer.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/www/c_status.html
M clang/www/cxx_dr_status.html
M cmake/Modules/HandleCompilerRT.cmake
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformFuchsia.c
M compiler-rt/lib/rtsan/rtsan_context.cpp
M compiler-rt/lib/rtsan/rtsan_context.h
M compiler-rt/lib/rtsan/rtsan_stack.cpp
M compiler-rt/lib/rtsan/rtsan_stack.h
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
M compiler-rt/lib/scudo/standalone/secondary.h
M compiler-rt/test/profile/ContinuousSyncMode/runtime-counter-relocation.c
M compiler-rt/test/profile/ContinuousSyncMode/set-file-object.c
M compiler-rt/test/rtsan/basic.cpp
M compiler-rt/www/index.html
M cross-project-tests/lit.cfg.py
M cross-project-tests/lit.site.cfg.py.in
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
A flang/test/Semantics/OpenMP/clause-order.f90
M libclc/CMakeLists.txt
M libcxx/include/__config
M libcxx/include/__type_traits/datasizeof.h
M libcxx/modules/std/type_traits.inc
M libcxx/test/benchmarks/format.bench.cpp
M libcxx/test/benchmarks/format_to.bench.cpp
M libcxx/test/benchmarks/format_to_n.bench.cpp
M libcxx/test/benchmarks/formatted_size.bench.cpp
M libcxx/test/benchmarks/formatter_int.bench.cpp
M libcxx/test/benchmarks/lexicographical_compare_three_way.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
M libcxx/test/benchmarks/to_chars.bench.cpp
M libcxx/test/benchmarks/variant_visit_1.bench.cpp
M libcxx/test/benchmarks/variant_visit_2.bench.cpp
M libcxx/test/benchmarks/variant_visit_3.bench.cpp
M libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
M lldb/docs/conf.py
M lldb/include/lldb/Host/common/TCPSocket.h
M lldb/include/lldb/Utility/SupportFile.h
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Host/common/TCPSocket.cpp
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/Target/TargetProperties.td
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/TestDataFormatterGenericOptional.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/main.cpp
M lldb/test/API/functionalities/memory/big-read/TestMemoryReadMaximumSize.py
M lldb/test/API/functionalities/memory/holes/TestMemoryHoles.py
M lldb/test/API/lit.cfg.py
M lldb/test/API/lit.site.cfg.py.in
M lldb/test/API/tools/lldb-dap/instruction-breakpoint/TestDAP_instruction_breakpoint.py
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.site.cfg.py.in
M lldb/tools/lldb-dap/package.json
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M llvm/CMakeLists.txt
M llvm/docs/conf.py
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Analysis/DominanceFrontier.h
M llvm/include/llvm/Analysis/DominanceFrontierImpl.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/MemorySSA.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/MachineDominanceFrontier.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/OperandTraits.h
M llvm/include/llvm/IR/Operator.h
M llvm/include/llvm/IR/User.h
M llvm/include/llvm/IR/VectorBuilder.h
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Transforms/IPO/FunctionImport.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/VectorBuilder.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/lib/Support/APInt.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
A llvm/lib/Target/AMDGPU/SIShrinkInstructions.h
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/BPF/BPFSubtarget.cpp
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Transforms/IPO/ModuleInliner.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/CostModel/RISCV/cast.ll
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
A llvm/test/Analysis/CtxProfAnalysis/inline.ll
A llvm/test/Analysis/CtxProfAnalysis/json_equals.py
M llvm/test/Analysis/CtxProfAnalysis/load.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
A llvm/test/CodeGen/AArch64/fabs-fp128.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/load.ll
A llvm/test/CodeGen/AArch64/machine-outliner-bundle.mir
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-extmul.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
A llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
A llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-3.ll
M llvm/test/CodeGen/BPF/CORE/no-narrow-load.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp2.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp3.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp4.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp5.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp6.ll
M llvm/test/CodeGen/BPF/adjust-opt-speculative1.ll
M llvm/test/CodeGen/BPF/adjust-opt-speculative2.ll
M llvm/test/CodeGen/BPF/alu8.ll
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/basictest.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
M llvm/test/CodeGen/BPF/cc_args.ll
M llvm/test/CodeGen/BPF/cc_args_be.ll
M llvm/test/CodeGen/BPF/cc_ret.ll
M llvm/test/CodeGen/BPF/cmp.ll
M llvm/test/CodeGen/BPF/cttz-ctlz.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/fi_ri.ll
M llvm/test/CodeGen/BPF/i128.ll
M llvm/test/CodeGen/BPF/intrinsics.ll
M llvm/test/CodeGen/BPF/load.ll
M llvm/test/CodeGen/BPF/loops.ll
M llvm/test/CodeGen/BPF/many_args1.ll
M llvm/test/CodeGen/BPF/objdump_atomics.ll
M llvm/test/CodeGen/BPF/objdump_cond_op.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/BPF/objdump_imm_hex.ll
M llvm/test/CodeGen/BPF/objdump_intrinsics.ll
M llvm/test/CodeGen/BPF/objdump_nop.ll
M llvm/test/CodeGen/BPF/objdump_static_var.ll
M llvm/test/CodeGen/BPF/objdump_trivial.ll
M llvm/test/CodeGen/BPF/pr57872.ll
M llvm/test/CodeGen/BPF/reloc-2.ll
M llvm/test/CodeGen/BPF/remove_truncate_1.ll
M llvm/test/CodeGen/BPF/remove_truncate_2.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/remove_truncate_6.ll
M llvm/test/CodeGen/BPF/remove_truncate_8.ll
M llvm/test/CodeGen/BPF/rodata_1.ll
M llvm/test/CodeGen/BPF/rodata_2.ll
M llvm/test/CodeGen/BPF/rodata_3.ll
M llvm/test/CodeGen/BPF/rodata_4.ll
M llvm/test/CodeGen/BPF/rodata_6.ll
M llvm/test/CodeGen/BPF/rodata_7.ll
M llvm/test/CodeGen/BPF/sanity.ll
M llvm/test/CodeGen/BPF/setcc.ll
M llvm/test/CodeGen/BPF/shifts.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/undef.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/M68k/Arith/add.ll
R llvm/test/CodeGen/M68k/Arith/sext-i1.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
A llvm/test/CodeGen/M68k/Data/link-unlnk.ll
A llvm/test/CodeGen/M68k/Data/load-extend.ll
A llvm/test/CodeGen/M68k/Data/load-imm.ll
A llvm/test/CodeGen/M68k/Data/sext-i1.ll
R llvm/test/CodeGen/M68k/link-unlnk.ll
R llvm/test/CodeGen/M68k/load-extend.ll
M llvm/test/CodeGen/M68k/pipeline.ll
A llvm/test/CodeGen/PowerPC/sms-recmii.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/half-select-icmp.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchEmpty.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
M llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll
A llvm/test/CodeGen/SPIRV/debug-info/no-misplaced-opextinst.ll
M llvm/test/CodeGen/SPIRV/transcoding/GlobalFunAnnotate.ll
M llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
A llvm/test/CodeGen/X86/avx10.2-fma-commute.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/Instrumentation/PGOForceFunctionAttrs/basic.ll
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt
M llvm/test/MC/RISCV/fp-default-rounding-mode.s
M llvm/test/MC/RISCV/rv32zfbfmin-valid.s
A llvm/test/MC/X86/avx10.2-bf16-32-att.s
A llvm/test/MC/X86/avx10.2-bf16-32-intel.s
A llvm/test/MC/X86/avx10.2-bf16-64-att.s
A llvm/test/MC/X86/avx10.2-bf16-64-intel.s
A llvm/test/MachineVerifier/AMDGPU/lit.local.cfg
A llvm/test/MachineVerifier/AMDGPU/register-killed-inside-loop.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_bitcast.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_intrinsic.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_intrinsic_w_side_effects.mir
A llvm/test/MachineVerifier/AMDGPU/undef-should-only-be-set-on-subreg-defs.mir
A llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
A llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-nonentry-block.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-pseudo-terminators.mir
A llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
A llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
A llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
R llvm/test/MachineVerifier/register-killed-inside-loop.mir
R llvm/test/MachineVerifier/test_g_bitcast.mir
R llvm/test/MachineVerifier/test_g_intrinsic.mir
R llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir
R llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir
R llvm/test/MachineVerifier/undef-virt-reg-entry-block.mir
R llvm/test/MachineVerifier/undef-virt-reg-nonentry-block.mir
R llvm/test/MachineVerifier/verifier-ec-subreg-liveness.mir
R llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir
R llvm/test/MachineVerifier/verifier-pseudo-terminators.mir
R llvm/test/MachineVerifier/verify-implicit-def.mir
R llvm/test/MachineVerifier/verify-reg-sequence.mir
R llvm/test/MachineVerifier/writelane_m0.mir
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/Transforms/JumpThreading/pr22086.ll
M llvm/test/Transforms/LICM/hoist-binop.ll
M llvm/test/Transforms/LICM/sink-foldable.ll
M llvm/test/Transforms/LICM/update-scev-after-hoist.ll
M llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/sphinx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SCCP/loadtest2.ll
M llvm/test/Transforms/SCCP/select.ll
M llvm/test/Transforms/SCCP/widening.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelements-vector-ops-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
A llvm/test/Transforms/SLPVectorizer/X86/minbw-user-non-sizable.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/revec-shufflevector.ll
M llvm/test/Transforms/SLPVectorizer/revec.ll
M llvm/test/tools/llvm-objdump/BPF/interleaved-source-test.ll
M llvm/tools/llvm-as/CMakeLists.txt
M llvm/tools/llvm-link/CMakeLists.txt
M llvm/tools/opt/CMakeLists.txt
M llvm/tools/opt/NewPMDriver.cpp
M llvm/tools/opt/NewPMDriver.h
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
M llvm/unittests/Transforms/Utils/CallPromotionUtilsTest.cpp
M llvm/utils/TableGen/VTEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/lld/test/BUILD.gn
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/TensorToSPIRV/TensorToSPIRV.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Transforms/SROA.cpp
A mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx12.mlir
M mlir/test/Conversion/TensorToSPIRV/tensor-ops-to-spirv.mlir
M mlir/test/Dialect/Tensor/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M offload/CMakeLists.txt
M offload/plugins-nextgen/host/CMakeLists.txt
M offload/test/api/is_initial_device.c
M offload/test/lit.cfg
M offload/test/mapping/declare_mapper_nested_default_mappers_array.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_array_subscript.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_complex_structure.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_ptr_subscript.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_var.cpp
M offload/test/mapping/map_both_pointer_pointee.c
M offload/test/mapping/target_pointers_members_map.cpp
M offload/test/offloading/CUDA/basic_launch.cu
M offload/test/offloading/CUDA/basic_launch_blocks_and_threads.cu
M offload/test/offloading/CUDA/basic_launch_multi_arg.cu
M offload/test/offloading/CUDA/launch_tu.cu
M offload/test/offloading/dynamic-schedule-non-spmd.cpp
M offload/test/offloading/dynamic-schedule.cpp
M offload/test/offloading/fortran/dtype-array-constant-index-map.f90
M offload/test/offloading/fortran/dump_map_tables.f90
M offload/test/offloading/fortran/target-depend.f90
M offload/test/offloading/fortran/target-map-all-common-block-members.f90
M offload/test/offloading/fortran/target-map-common-block.f90
M offload/test/offloading/fortran/target-map-declare-target-link-common-block.f90
M offload/test/offloading/fortran/target-map-first-common-block-member.f90
M offload/test/offloading/fortran/target-map-mix-imp-exp-common-block-members.f90
M offload/test/offloading/fortran/target-map-second-common-block-member.f90
M offload/test/offloading/high_trip_count_block_limit.cpp
M offload/test/offloading/schedule.c
M offload/test/sanitizer/double_free.c
M offload/test/sanitizer/double_free_racy.c
M offload/test/sanitizer/free_host_ptr.c
M offload/test/sanitizer/free_wrong_ptr_kind.c
M offload/test/sanitizer/free_wrong_ptr_kind.cpp
M offload/test/sanitizer/kernel_crash.c
M offload/test/sanitizer/kernel_crash_async.c
M offload/test/sanitizer/kernel_crash_many.c
M offload/test/sanitizer/kernel_crash_single.c
M offload/test/sanitizer/kernel_trap.c
M offload/test/sanitizer/kernel_trap.cpp
M offload/test/sanitizer/kernel_trap_async.c
M offload/test/sanitizer/kernel_trap_many.c
M offload/test/sanitizer/ptr_outside_alloc_1.c
M offload/test/sanitizer/ptr_outside_alloc_2.c
M offload/test/sanitizer/use_after_free_1.c
M offload/test/sanitizer/use_after_free_2.c
M utils/bazel/.bazelrc
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Commit: 85c8e9e851ca26e853b57504b18a2816cc4a5d67
https://github.com/llvm/llvm-project/commit/85c8e9e851ca26e853b57504b18a2816cc4a5d67
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M bolt/include/bolt/Profile/YAMLProfileWriter.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Profile/YAMLProfileWriter.cpp
A bolt/test/X86/yaml-unknown-keys.test
M bolt/tools/merge-fdata/merge-fdata.cpp
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/BuiltinsX86.def
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10_2_512bf16intrin.h
A clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAvailability.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/constexpr-frame-describe.cpp
M clang/test/Analysis/mmap-writeexec.c
M clang/test/Analysis/stack-addr-ps.cpp
A clang/test/CXX/drs/cwg1818.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg24xx.cpp
A clang/test/CXX/drs/cwg563.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
A clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c
A clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M clang/test/CodeGen/X86/x86-atomic-double.c
M clang/test/CodeGen/X86/x86-atomic-long_double.c
M clang/test/CodeGen/pgo-force-function-attrs.ll
M clang/test/Driver/debug-options-as.c
M clang/test/FixIt/fixit-availability-maccatalyst.m
M clang/test/FixIt/fixit-availability.mm
M clang/test/Modules/no-local-decl-in-reduced-bmi.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview-std.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview.cppm
M clang/test/Modules/unreached-static-entities.cppm
M clang/test/Preprocessor/bpf-predefined-macros.c
M clang/test/Preprocessor/init-ppc.c
M clang/test/Preprocessor/init-ppc64.c
M clang/test/SemaCXX/attr-lifetimebound.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
M clang/test/SemaCXX/extern-c.cpp
M clang/test/SemaCXX/source_location.cpp
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
M clang/tools/clang-format/git-clang-format.bat
M clang/tools/driver/CMakeLists.txt
M clang/unittests/Driver/SimpleDiagnosticConsumer.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/www/c_status.html
M clang/www/cxx_dr_status.html
M cmake/Modules/HandleCompilerRT.cmake
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformFuchsia.c
M compiler-rt/lib/rtsan/rtsan_context.cpp
M compiler-rt/lib/rtsan/rtsan_context.h
M compiler-rt/lib/rtsan/rtsan_stack.cpp
M compiler-rt/lib/rtsan/rtsan_stack.h
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
M compiler-rt/lib/scudo/standalone/secondary.h
M compiler-rt/test/profile/ContinuousSyncMode/runtime-counter-relocation.c
M compiler-rt/test/profile/ContinuousSyncMode/set-file-object.c
M compiler-rt/test/rtsan/basic.cpp
M compiler-rt/www/index.html
M cross-project-tests/lit.cfg.py
M cross-project-tests/lit.site.cfg.py.in
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
A flang/test/Semantics/OpenMP/clause-order.f90
M libclc/CMakeLists.txt
M libcxx/include/__config
M libcxx/include/__type_traits/datasizeof.h
M libcxx/modules/std/type_traits.inc
M libcxx/test/benchmarks/format.bench.cpp
M libcxx/test/benchmarks/format_to.bench.cpp
M libcxx/test/benchmarks/format_to_n.bench.cpp
M libcxx/test/benchmarks/formatted_size.bench.cpp
M libcxx/test/benchmarks/formatter_int.bench.cpp
M libcxx/test/benchmarks/lexicographical_compare_three_way.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
M libcxx/test/benchmarks/to_chars.bench.cpp
M libcxx/test/benchmarks/variant_visit_1.bench.cpp
M libcxx/test/benchmarks/variant_visit_2.bench.cpp
M libcxx/test/benchmarks/variant_visit_3.bench.cpp
M libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
M lldb/docs/conf.py
M lldb/include/lldb/Host/common/TCPSocket.h
M lldb/include/lldb/Utility/SupportFile.h
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Host/common/TCPSocket.cpp
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/Target/TargetProperties.td
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/TestDataFormatterGenericOptional.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/main.cpp
M lldb/test/API/functionalities/memory/big-read/TestMemoryReadMaximumSize.py
M lldb/test/API/functionalities/memory/holes/TestMemoryHoles.py
M lldb/test/API/lit.cfg.py
M lldb/test/API/lit.site.cfg.py.in
M lldb/test/API/tools/lldb-dap/instruction-breakpoint/TestDAP_instruction_breakpoint.py
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.site.cfg.py.in
M lldb/tools/lldb-dap/package.json
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M llvm/CMakeLists.txt
M llvm/docs/conf.py
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Analysis/DominanceFrontier.h
M llvm/include/llvm/Analysis/DominanceFrontierImpl.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/MemorySSA.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/MachineDominanceFrontier.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/OperandTraits.h
M llvm/include/llvm/IR/Operator.h
M llvm/include/llvm/IR/User.h
M llvm/include/llvm/IR/VectorBuilder.h
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Transforms/IPO/FunctionImport.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/VectorBuilder.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/lib/Support/APInt.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
A llvm/lib/Target/AMDGPU/SIShrinkInstructions.h
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/BPF/BPFSubtarget.cpp
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Transforms/IPO/ModuleInliner.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/CostModel/RISCV/cast.ll
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
A llvm/test/Analysis/CtxProfAnalysis/inline.ll
A llvm/test/Analysis/CtxProfAnalysis/json_equals.py
M llvm/test/Analysis/CtxProfAnalysis/load.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
A llvm/test/CodeGen/AArch64/fabs-fp128.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/load.ll
A llvm/test/CodeGen/AArch64/machine-outliner-bundle.mir
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-extmul.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
A llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
A llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-3.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-1.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-2.ll
M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-3.ll
M llvm/test/CodeGen/BPF/CORE/no-narrow-load.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2-bpfeb.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp2.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp3.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp4.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp5.ll
M llvm/test/CodeGen/BPF/adjust-opt-icmp6.ll
M llvm/test/CodeGen/BPF/adjust-opt-speculative1.ll
M llvm/test/CodeGen/BPF/adjust-opt-speculative2.ll
M llvm/test/CodeGen/BPF/alu8.ll
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/basictest.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
M llvm/test/CodeGen/BPF/cc_args.ll
M llvm/test/CodeGen/BPF/cc_args_be.ll
M llvm/test/CodeGen/BPF/cc_ret.ll
M llvm/test/CodeGen/BPF/cmp.ll
M llvm/test/CodeGen/BPF/cttz-ctlz.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/fi_ri.ll
M llvm/test/CodeGen/BPF/i128.ll
M llvm/test/CodeGen/BPF/intrinsics.ll
M llvm/test/CodeGen/BPF/load.ll
M llvm/test/CodeGen/BPF/loops.ll
M llvm/test/CodeGen/BPF/many_args1.ll
M llvm/test/CodeGen/BPF/objdump_atomics.ll
M llvm/test/CodeGen/BPF/objdump_cond_op.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/BPF/objdump_imm_hex.ll
M llvm/test/CodeGen/BPF/objdump_intrinsics.ll
M llvm/test/CodeGen/BPF/objdump_nop.ll
M llvm/test/CodeGen/BPF/objdump_static_var.ll
M llvm/test/CodeGen/BPF/objdump_trivial.ll
M llvm/test/CodeGen/BPF/pr57872.ll
M llvm/test/CodeGen/BPF/reloc-2.ll
M llvm/test/CodeGen/BPF/remove_truncate_1.ll
M llvm/test/CodeGen/BPF/remove_truncate_2.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/remove_truncate_6.ll
M llvm/test/CodeGen/BPF/remove_truncate_8.ll
M llvm/test/CodeGen/BPF/rodata_1.ll
M llvm/test/CodeGen/BPF/rodata_2.ll
M llvm/test/CodeGen/BPF/rodata_3.ll
M llvm/test/CodeGen/BPF/rodata_4.ll
M llvm/test/CodeGen/BPF/rodata_6.ll
M llvm/test/CodeGen/BPF/rodata_7.ll
M llvm/test/CodeGen/BPF/sanity.ll
M llvm/test/CodeGen/BPF/setcc.ll
M llvm/test/CodeGen/BPF/shifts.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/undef.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/M68k/Arith/add.ll
R llvm/test/CodeGen/M68k/Arith/sext-i1.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
A llvm/test/CodeGen/M68k/Data/link-unlnk.ll
A llvm/test/CodeGen/M68k/Data/load-extend.ll
A llvm/test/CodeGen/M68k/Data/load-imm.ll
A llvm/test/CodeGen/M68k/Data/sext-i1.ll
R llvm/test/CodeGen/M68k/link-unlnk.ll
R llvm/test/CodeGen/M68k/load-extend.ll
M llvm/test/CodeGen/M68k/pipeline.ll
A llvm/test/CodeGen/PowerPC/sms-recmii.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/half-select-icmp.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchEmpty.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
M llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll
A llvm/test/CodeGen/SPIRV/debug-info/no-misplaced-opextinst.ll
M llvm/test/CodeGen/SPIRV/transcoding/GlobalFunAnnotate.ll
M llvm/test/CodeGen/Thumb2/pipeliner-preserve-ties.mir
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
A llvm/test/CodeGen/X86/avx10.2-fma-commute.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/Instrumentation/PGOForceFunctionAttrs/basic.ll
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt
M llvm/test/MC/RISCV/fp-default-rounding-mode.s
M llvm/test/MC/RISCV/rv32zfbfmin-valid.s
A llvm/test/MC/X86/avx10.2-bf16-32-att.s
A llvm/test/MC/X86/avx10.2-bf16-32-intel.s
A llvm/test/MC/X86/avx10.2-bf16-64-att.s
A llvm/test/MC/X86/avx10.2-bf16-64-intel.s
A llvm/test/MachineVerifier/AMDGPU/lit.local.cfg
A llvm/test/MachineVerifier/AMDGPU/register-killed-inside-loop.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_bitcast.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_intrinsic.mir
A llvm/test/MachineVerifier/AMDGPU/test_g_intrinsic_w_side_effects.mir
A llvm/test/MachineVerifier/AMDGPU/undef-should-only-be-set-on-subreg-defs.mir
A llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
A llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-nonentry-block.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
A llvm/test/MachineVerifier/AMDGPU/verifier-pseudo-terminators.mir
A llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
A llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
A llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
R llvm/test/MachineVerifier/register-killed-inside-loop.mir
R llvm/test/MachineVerifier/test_g_bitcast.mir
R llvm/test/MachineVerifier/test_g_intrinsic.mir
R llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir
R llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir
R llvm/test/MachineVerifier/undef-virt-reg-entry-block.mir
R llvm/test/MachineVerifier/undef-virt-reg-nonentry-block.mir
R llvm/test/MachineVerifier/verifier-ec-subreg-liveness.mir
R llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir
R llvm/test/MachineVerifier/verifier-pseudo-terminators.mir
R llvm/test/MachineVerifier/verify-implicit-def.mir
R llvm/test/MachineVerifier/verify-reg-sequence.mir
R llvm/test/MachineVerifier/writelane_m0.mir
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/Transforms/JumpThreading/pr22086.ll
M llvm/test/Transforms/LICM/hoist-binop.ll
M llvm/test/Transforms/LICM/sink-foldable.ll
M llvm/test/Transforms/LICM/update-scev-after-hoist.ll
M llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/sphinx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SCCP/loadtest2.ll
M llvm/test/Transforms/SCCP/select.ll
M llvm/test/Transforms/SCCP/widening.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelements-vector-ops-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
A llvm/test/Transforms/SLPVectorizer/X86/minbw-user-non-sizable.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/revec-shufflevector.ll
M llvm/test/Transforms/SLPVectorizer/revec.ll
M llvm/test/tools/llvm-objdump/BPF/interleaved-source-test.ll
M llvm/tools/llvm-as/CMakeLists.txt
M llvm/tools/llvm-link/CMakeLists.txt
M llvm/tools/opt/CMakeLists.txt
M llvm/tools/opt/NewPMDriver.cpp
M llvm/tools/opt/NewPMDriver.h
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
M llvm/unittests/Transforms/Utils/CallPromotionUtilsTest.cpp
M llvm/utils/TableGen/VTEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/lld/test/BUILD.gn
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/TensorToSPIRV/TensorToSPIRV.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Transforms/SROA.cpp
A mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx12.mlir
M mlir/test/Conversion/TensorToSPIRV/tensor-ops-to-spirv.mlir
M mlir/test/Dialect/Tensor/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M offload/CMakeLists.txt
M offload/plugins-nextgen/host/CMakeLists.txt
M offload/test/api/is_initial_device.c
M offload/test/lit.cfg
M offload/test/mapping/declare_mapper_nested_default_mappers_array.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_array_subscript.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_complex_structure.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_ptr_subscript.cpp
M offload/test/mapping/declare_mapper_nested_default_mappers_var.cpp
M offload/test/mapping/map_both_pointer_pointee.c
M offload/test/mapping/target_pointers_members_map.cpp
M offload/test/offloading/CUDA/basic_launch.cu
M offload/test/offloading/CUDA/basic_launch_blocks_and_threads.cu
M offload/test/offloading/CUDA/basic_launch_multi_arg.cu
M offload/test/offloading/CUDA/launch_tu.cu
M offload/test/offloading/dynamic-schedule-non-spmd.cpp
M offload/test/offloading/dynamic-schedule.cpp
M offload/test/offloading/fortran/dtype-array-constant-index-map.f90
M offload/test/offloading/fortran/dump_map_tables.f90
M offload/test/offloading/fortran/target-depend.f90
M offload/test/offloading/fortran/target-map-all-common-block-members.f90
M offload/test/offloading/fortran/target-map-common-block.f90
M offload/test/offloading/fortran/target-map-declare-target-link-common-block.f90
M offload/test/offloading/fortran/target-map-first-common-block-member.f90
M offload/test/offloading/fortran/target-map-mix-imp-exp-common-block-members.f90
M offload/test/offloading/fortran/target-map-second-common-block-member.f90
M offload/test/offloading/high_trip_count_block_limit.cpp
M offload/test/offloading/schedule.c
M offload/test/sanitizer/double_free.c
M offload/test/sanitizer/double_free_racy.c
M offload/test/sanitizer/free_host_ptr.c
M offload/test/sanitizer/free_wrong_ptr_kind.c
M offload/test/sanitizer/free_wrong_ptr_kind.cpp
M offload/test/sanitizer/kernel_crash.c
M offload/test/sanitizer/kernel_crash_async.c
M offload/test/sanitizer/kernel_crash_many.c
M offload/test/sanitizer/kernel_crash_single.c
M offload/test/sanitizer/kernel_trap.c
M offload/test/sanitizer/kernel_trap.cpp
M offload/test/sanitizer/kernel_trap_async.c
M offload/test/sanitizer/kernel_trap_many.c
M offload/test/sanitizer/ptr_outside_alloc_1.c
M offload/test/sanitizer/ptr_outside_alloc_2.c
M offload/test/sanitizer/use_after_free_1.c
M offload/test/sanitizer/use_after_free_2.c
M utils/bazel/.bazelrc
Log Message:
-----------
YAMLProfileWriter::getInlineTree
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/50c021b09950...85c8e9e851ca
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