[all-commits] [llvm/llvm-project] c82a54: [RISCV] Support fixed vector VP_LOAD/STORE for bf1...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c82a5496c80747981efb8d25ad8bc4d8c6785b2e
      https://github.com/llvm/llvm-project/commit/c82a5496c80747981efb8d25ad8bc4d8c6785b2e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-04 (Wed, 04 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

  Log Message:
  -----------
  [RISCV] Support fixed vector VP_LOAD/STORE for bf16 and f16 without Zvfh. (#107297)

This allows odd sized vector load/store to be legalized to a
VP_LOAD/STORE using EVL.

I changed the bf16 tests in fixed-vectors-load.ll and
fixed-vectors-store.ll to use an illegal type to be consistent with the
intent of these files. A legal type is already tested in
fixed-vectors-load-store.ll



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