[all-commits] [llvm/llvm-project] 26ba18: [PowerPC] Improve pwr7 codegen for v4i8 load (#104...

[RolandF77 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 26ba186bd0a22fac7d08ed566b00c03236b6b7a9
      https://github.com/llvm/llvm-project/commit/26ba186bd0a22fac7d08ed566b00c03236b6b7a9
  Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
  Date:   2024-09-04 (Wed, 04 Sep 2024)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/load-and-splat.ll
    M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
    M llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
    M llvm/test/CodeGen/PowerPC/test-vector-insert.ll
    M llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll
    M llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll
    M llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll
    M llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll

  Log Message:
  -----------
  [PowerPC] Improve pwr7 codegen for v4i8 load (#104507)

There are no partial vector loads on pwr7 so current v4i8 codegen is an
int load then store to vector sized temp and re-load as vector. Try to
use lfiwax to load 32 bits into an FP reg and take advantage of VSX FP
and vector reg sharing to move the result to the right vector position.



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