[all-commits] [llvm/llvm-project] 660e34: [lldb][RISCV] Support optionally disabled FPR for ...

[Alexey Merzlyakov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 660e34fd38c3fb39fba1871bbf5b2eb3a48bf277
      https://github.com/llvm/llvm-project/commit/660e34fd38c3fb39fba1871bbf5b2eb3a48bf277
  Author: Alexey Merzlyakov <60094858+AlexeyMerzlyakov at users.noreply.github.com>
  Date:   2024-09-04 (Wed, 04 Sep 2024)

  Changed paths:
    M lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
    M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
    M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
    M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
    M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
    M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
    M lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
    M lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
    M lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
    M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
    R lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
    A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.gpr_fpr.core
    A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.gpr_fpr.out
    A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.gpr_only.core
    A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.gpr_only.out
    R lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
    A lldb/test/API/functionalities/postmortem/elf-core/main_fpr.c

  Log Message:
  -----------
  [lldb][RISCV] Support optionally disabled FPR for riscv64 (#104547)

The PR adds the support optionally enabled/disabled FP-registers to LLDB
`RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V
builds having no FP-registers, like RV64IMAC or RV64IMACV.

To aim this, patch adds `opt_regsets` flags mechanism. It re-works
RegisterInfo class to work with flexibly allocated (depending on
`opt_regsets` flag) `m_register_sets` and `m_register_infos` vectors
instead of statically defined structures. The registration of regsets is
being arranged by `m_per_regset_regnum_range` map.

The patch flows are spread to `NativeRegisterContextLinux_riscv64` and
`RegisterContextCorePOSIX_riscv64` classes, that were tested on:
 - x86_64 host working with coredumps
- RV64GC and RV64IMAC targets working with coredumps and natively in
run-time with binaries

`EmulateInstructionRISCV` is out of scope of this patch, and its
behavior did not change, using maximum set of registers.

According testcase built for RV64IMAC (no-FPR) was added to
`TestLinuxCore.py`.



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