[all-commits] [llvm/llvm-project] 6c143a: [CodeGen][NewPM] Port MachineCSE pass to new pass ...

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c143a86cddbc6d0431dd643bfc7d4f017042512
      https://github.com/llvm/llvm-project/commit/6c143a86cddbc6d0431dd643bfc7d4f017042512
  Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
  Date:   2024-09-04 (Wed, 04 Sep 2024)

  Changed paths:
    A llvm/include/llvm/CodeGen/MachineCSE.h
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Passes/CodeGenPassBuilder.h
    M llvm/include/llvm/Passes/MachinePassRegistry.def
    M llvm/lib/CodeGen/CodeGen.cpp
    M llvm/lib/CodeGen/MachineCSE.cpp
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/Passes/PassBuilder.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir
    M llvm/test/CodeGen/AArch64/sve-pfalse-machine-cse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
    M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
    M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
    M llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
    M llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir
    M llvm/test/CodeGen/Thumb/machine-cse-physreg.mir
    M llvm/test/CodeGen/X86/cse-two-preds.mir
    M llvm/test/DebugInfo/MIR/X86/machine-cse.mir

  Log Message:
  -----------
  [CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)



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