[all-commits] [llvm/llvm-project] 884d7c: Revert "[SLP]Check for the whole vector vectorizat...
Florian Mayer via All-commits
all-commits at lists.llvm.org
Tue Sep 3 23:51:55 PDT 2024
Branch: refs/heads/users/fmayer/spr/reapply2-hwasan-remove-incorrectly-inferred-attributes-106622
Home: https://github.com/llvm/llvm-project
Commit: 884d7c137a587fdd7549bd8a26f887bbeda0cc86
https://github.com/llvm/llvm-project/commit/884d7c137a587fdd7549bd8a26f887bbeda0cc86
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
R llvm/test/Transforms/SLPVectorizer/RISCV/unique-loads-insert-non-power-of-2.ll
Log Message:
-----------
Revert "[SLP]Check for the whole vector vectorization in unique scalars analysis"
This reverts commit b74e09cb20e6218320013b54c9ba2f5c069d44b9 after
post-commit review. The number of parts is calculated incorrectly.
Commit: 571c8c2c88122d318ed84cd9e948613e3f1aac5f
https://github.com/llvm/llvm-project/commit/571c8c2c88122d318ed84cd9e948613e3f1aac5f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
Log Message:
-----------
Revert "[SLP]Initial support for non-power-of-2 (but still whole register) number of elements in operands."
This reverts commit a3ea90ffbbe47d9a1b3eab03324f09d7b8e0dcb3 after the
post commit review. The number of parts is calculated incorrectly.
Commit: 126940bde3e48ad9bf0a6966fc473e22d4dade7d
https://github.com/llvm/llvm-project/commit/126940bde3e48ad9bf0a6966fc473e22d4dade7d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] Use DenseMap::{find,try_emplace} (NFC) (#107123)
I'm planning to deprecate and eventually remove
DenseMap::FindAndConstruct in favor of operator[].
Commit: 15fa3ba547bc3ee04af5c32b8f723a97e3feefd8
https://github.com/llvm/llvm-project/commit/15fa3ba547bc3ee04af5c32b8f723a97e3feefd8
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M bolt/lib/Profile/YAMLProfileReader.cpp
A bolt/test/X86/yaml-unknown-keys.test
M bolt/tools/merge-fdata/merge-fdata.cpp
Log Message:
-----------
[BOLT][YAML] Allow unknown keys in the input (#100824)
This ensures forward compatibility, where old BOLT versions can consume
the profile created by newer versions with extra keys.
Test Plan: added yaml-unknown-keys.test
Commit: eec1fac9b51d06c8afafe9952a20ba7cd4c3ce1c
https://github.com/llvm/llvm-project/commit/eec1fac9b51d06c8afafe9952a20ba7cd4c3ce1c
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
Log Message:
-----------
[Clang] Fix handling of placeholder variables name in init captures (#107055)
We were incorrectly not deduplicating results when looking up `_` which,
for a lambda init capture, would result in an ambiguous lookup.
The same bug caused some diagnostic notes to be emitted twice.
Fixes #107024
Commit: 1fbb6b4efc9e9d257f0f7e5065f40f9b9677ca7c
https://github.com/llvm/llvm-project/commit/1fbb6b4efc9e9d257f0f7e5065f40f9b9677ca7c
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
Log Message:
-----------
[LV] Prefer FLT_MIN/MAX for fmin/fmax reductions with ninf (#107141)
Analogous to 2c7786e94a1058bd4f96794a1d4f70dcb86e5cc5, cleanup a case
where the vectorizer is emitting a non-canonical identity value given
the available flags. We use largest/smallest value during ISEL, and VP
expansion, but not during vectorization.
Since the fmin/fmax/fminimum/fmaximum intrinsics don't require a start
value, this difference is only visible when masking of inactive lanes is
required.
Primary motivation of this change is simply to remove a difference
between version of code which reason about the identity value of a
reduction so I can kill all but one off.
In review, it was pointed out that this is actually a functional fix as well.
The old code used inf on a noinf reduction instruction - whose
result is poison! That wasn't the intent of the code.
Commit: 451a3135a7afece0b6e7605376ce208435605934
https://github.com/llvm/llvm-project/commit/451a3135a7afece0b6e7605376ce208435605934
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/DominanceFrontier.h
M llvm/include/llvm/Analysis/DominanceFrontierImpl.h
M llvm/include/llvm/CodeGen/MachineDominanceFrontier.h
Log Message:
-----------
[DominanceFrontier] Remove unused functions (#106913)
Commit: eb05e8fde1ebc4cda2106b1236620a8a89b36b7c
https://github.com/llvm/llvm-project/commit/eb05e8fde1ebc4cda2106b1236620a8a89b36b7c
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/www/c_status.html
Log Message:
-----------
[clang] [docs] Clarify the issue with compiler-rt on Windows/MSVC (#106875)
Compiler-rt does support Windows just fine, even if outdated docs pages
didn't list it as one of the supported OSes, this is being rectified in
https://github.com/llvm/llvm-project/pull/106874.
MinGW is another environment configuration on Windows, where compiler-rt
or libgcc is linked in automatically, so there's no issue with having
such builtins functions available.
For MSVC style environments, compiler-rt builtins do work just fine, but
Clang doesn't automatically link them in. See e.g.
https://discourse.llvm.org/t/improve-autolinking-of-compiler-rt-and-libc-on-windows-with-lld-link/71392
for a discussion on how to improve this situation. But none of that
issue is that compiler-rt itself wouldn't support Windows.
Commit: fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10
https://github.com/llvm/llvm-project/commit/fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] Don't add DWARF debug info when assembling .s with clang-cl /Z7 (#106686)
This fixes a regression from f58330cbe44598eb2de0cca3b812f67fea0a71ca.
That commit changed the clang-cl options /Zi and /Z7 to be implemented
as aliases of -g rather than having separate handling.
This had the unintended effect, that when assembling .s files with
clang-cl, the /Z7 option (which implies using CodeView debug info) was
treated as a -g option, which causes `ClangAs::ConstructJob` to pick up
the option as part of `Args.getLastArg(options::OPT_g_Group)`, which
sets the `WantDebug` variable.
Within `Clang::ConstructJob`, we check for whether explicit `-gdwarf` or
`-gcodeview` options have been set, and if not, we pick the default
debug format for the current toolchain. However, in `ClangAs`, if debug
info has been enabled, it always adds DWARF debug info.
Add similar logic in `ClangAs` - check if the user has explicitly
requested either DWARF or CodeView, otherwise look up the toolchain
default. If we (either implicitly or explicitly) should be producing
CodeView, don't enable the default `ClangAs` DWARF generation.
This fixes the issue, where assembling a single `.s` file with clang-cl,
with the /Z7 option, causes the file to contain some DWARF sections.
This causes the output executable to contain DWARF, in addition to the
separate intended main PDB file.
By having the output executable contain DWARF sections, LLDB only looks
at the (very little) DWARF info in the executable, rather than looking
for a separate standalone PDB file. This caused an issue with LLDB's
tests, https://github.com/llvm/llvm-project/issues/101710.
Commit: 3bd161e98d89d31696002994771b7761f1c74859
https://github.com/llvm/llvm-project/commit/3bd161e98d89d31696002994771b7761f1c74859
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
Log Message:
-----------
[LV] Honor forced scalars in setVectorizedCallDecision.
Similarly to dd94537b4, setVectorizedCallDecision also did not consider
ForcedScalars. This lead to VPlans not reflecting the decision by the
legacy cost model (cost computation would use scalar cost, VPlan would
have VPWidenCallRecipe).
To fix this, check if the call has been forced to scalar in
setVectorizedCallDecision.
Note that this requires moving setVectorizedCallDecision after
collectLoopUniforms (which sets ForcedScalars). collectLoopUniforms does
not depend on call decisions and can safely be moved.
Fixes https://github.com/llvm/llvm-project/issues/107051.
Commit: 70f3511adaea4d3a9f8fadb23e84f518cc0654ab
https://github.com/llvm/llvm-project/commit/70f3511adaea4d3a9f8fadb23e84f518cc0654ab
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] [test] Fix the debug-options-as.c test on macOS
Separate the path, which may begin with e.g. /Users, with "--" from
the other options, to make it clear that it is a path, not an
option.
This fixes a test from fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10.
Commit: ec8e1c623a78536b956cc2c1d42ae75c4024ad66
https://github.com/llvm/llvm-project/commit/ec8e1c623a78536b956cc2c1d42ae75c4024ad66
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
Log Message:
-----------
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
This avoids having isel patterns that emit two instrutions. It also
allows us to remove sext.w and slli+srli pairs by using fcvt.s.w(u) on
RV64.
Commit: 319e8cd201e6744199da377fba237dd276063e49
https://github.com/llvm/llvm-project/commit/319e8cd201e6744199da377fba237dd276063e49
Author: Ian Anderson <iana at apple.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/Sema/SemaAvailability.cpp
M clang/test/FixIt/fixit-availability-maccatalyst.m
M clang/test/FixIt/fixit-availability.mm
Log Message:
-----------
[Clang][Sema] clang generates incorrect fix-its for API_AVAILABLE (#105855)
Apple's API_AVAILABLE macro has its own notion of platform names which
are supported by \_\_API_AVAILABLE_PLATFORM_<name> macros. They don't
follow a consistent naming convention, but there's at least one that
matches a valid availability attribute platform name. Instead of
lowercasing the source spelling name, search for a defined macro and use
that in the fix-it.
Commit: cdab6ffd6d32566277f71d9733e4b21750ea38c8
https://github.com/llvm/llvm-project/commit/cdab6ffd6d32566277f71d9733e4b21750ea38c8
Author: weiguozhi <57237827+weiguozhi at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
Log Message:
-----------
[X86] Don't save/restore fp/bp around terminator (#106462)
In function spillFPBP we already try to skip terminator, but there is a
logic error, so when there is only terminator instruction in the MBB, it
still tries to save/restore fp/bp around it if the terminator clobbers
fp/bp, for example a tail call with ghc calling convention.
Now this patch really skips terminator even if it is the only
instruction in the MBB.
Commit: cbb5f03f5042aa6d7c5d17963eba192861c9165c
https://github.com/llvm/llvm-project/commit/cbb5f03f5042aa6d7c5d17963eba192861c9165c
Author: Martin Storsjö <martin at martin.st>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/test/Driver/debug-options-as.c
Log Message:
-----------
[clang] [test] Fix the debug-options-as.c test on PowerPC
Use an explicit MSVC triple with an architecture that does
have proper handling for MSVC style targets.
This fixes a test from fcb7b390ccd5b4cfc71f13b5e16a846f3f400c10.
Commit: 0ef7b1d21ca7ce55f1c8d3ec739e64775572e9cc
https://github.com/llvm/llvm-project/commit/0ef7b1d21ca7ce55f1c8d3ec739e64775572e9cc
Author: Joshua Baehring <98630690+JoshuaMBa at users.noreply.github.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/secondary.h
Log Message:
-----------
[scudo] Update secondary cache released pages bound. (#106466)
`MaxReleasedCachePages` has been set to 4. Initially, in #105009 , we
set `MaxReleasedCachePages` to 0 so that the partial chunk heuristic
could be introduced incrementally as we observed its impact on retrieval
order and more generally, performance.
Co-authored-by: Joshua Baehring <josh.baehring at yale.edu>
Commit: 334d1238aafa8ca017d433caaf8f6e00f2622111
https://github.com/llvm/llvm-project/commit/334d1238aafa8ca017d433caaf8f6e00f2622111
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
Log Message:
-----------
[HLSL] Adjust resource binding diagnostic flags code (#106657)
Adjust register binding diagnostic flags code in a couple of ways:
- Store the resource class in the Flags struct to avoid duplicated
scanning for HLSLResourceClassAttribute
- Avoid unnecessary indirection when converting resource class to
register type
- Remove recursion and reduce duplicated code
Also fixes a case where struct with an array was incorrectly diagnosed
unfit for `c` register binding.
This will also simplify work that is needed to be done in this area for
llvm/llvm-project#104861.
Commit: dfc21acdfa0eb7f6f6bb563445959fb18ea863da
https://github.com/llvm/llvm-project/commit/dfc21acdfa0eb7f6f6bb563445959fb18ea863da
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] Convert global allocation for pinned variable (#106807)
ALLOCATE/DEALLOCATE statements for module allocatable variable with the
pinned attribute can be lowered to the standard runtime call and do not
need further action since these variables will have a unique descriptor
that is on the host.
Commit: b2dabd2b06cb0ca5ea534bafe33c5cff5521be18
https://github.com/llvm/llvm-project/commit/b2dabd2b06cb0ca5ea534bafe33c5cff5521be18
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[Sema] Fix warnings
This patch fixes:
clang/lib/Sema/SemaHLSL.cpp:838:12: error: unused variable
'TheVarDecl' [-Werror,-Wunused-variable]
clang/lib/Sema/SemaHLSL.cpp:840:19: error: unused variable
'CBufferOrTBuffer' [-Werror,-Wunused-variable]
Commit: d966d4708fe5084e47ca3d9d411935d6870aefff
https://github.com/llvm/llvm-project/commit/d966d4708fe5084e47ca3d9d411935d6870aefff
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/SupportFile.h
Log Message:
-----------
[lldb] Make SupportFile's FileSpec and Checksum const (NFC)
Commit: 98bde7fd872c10e49035d5dc5d2f2b44489f6a07
https://github.com/llvm/llvm-project/commit/98bde7fd872c10e49035d5dc5d2f2b44489f6a07
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Symbol/LineTable.cpp
Log Message:
-----------
[lldb] Avoid FileSpec indirection where we can use SupportFiles directly
Now that more parts of LLDB know about SupportFiles, avoid going through
FileSpec (and losing the Checksum in the process). Instead, use the
SupportFile directly.
Commit: 53d3d1ab9abf28e92a27fce0a99ae83720d27d75
https://github.com/llvm/llvm-project/commit/53d3d1ab9abf28e92a27fce0a99ae83720d27d75
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] Avoid two successive hash lookups on the same key (#107143)
This patch replaces the find-try_emplace sequence with just one call
to try_emplace, thereby avoiding two successive hash lookups on the
same key. I am not using the "inserted" boolean from try_emplace to
preserve the original behavior (that is, before PR 107123) that checks
to see if the value is nullptr or not.
Commit: db8ca88f578c2270ab2d461fa0dd5e7a1d1bad43
https://github.com/llvm/llvm-project/commit/db8ca88f578c2270ab2d461fa0dd5e7a1d1bad43
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/utils/TableGen/VTEmitter.cpp
Log Message:
-----------
[TableGen] Print all arguments to GET_VT_ATTR in the comment in GenVT.inc. NFC
Commit: 18cf14efe3e82b2343817fd174bcac48244c8f50
https://github.com/llvm/llvm-project/commit/18cf14efe3e82b2343817fd174bcac48244c8f50
Author: Scott Linder <Scott.Linder at amd.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/docs/conf.py
M llvm/docs/conf.py
Log Message:
-----------
[Docs] Use cacheable myst_heading_slug_func value
Avoid creating an uncacheable conf variable by using a string instead of
a function reference. Also has the effect of avoiding triggering the
"config.cache" sphinx warning.
Requires myst_parser 0.19.0 (specifically
https://github.com/executablebooks/MyST-Parser/pull/696) which is over a
year old by now. Do we mandate any minimum version for these
dependencies?
Commit: db3792b87a4fd759e336c44946a3e2ec0008c993
https://github.com/llvm/llvm-project/commit/db3792b87a4fd759e336c44946a3e2ec0008c993
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
Log Message:
-----------
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
All of the test changes are because integer type legalization prefers to promote
fp_to_uint to fp_to_sint if neither is "Legal".
Commit: 7d3b81d06f96bc27673f31a7bd7d141ce4a2777b
https://github.com/llvm/llvm-project/commit/7d3b81d06f96bc27673f31a7bd7d141ce4a2777b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb] Bump the lldb-dap version number
Bump the lldb-dap version number so that we can publish and updated
version in the Visual Studio Marketplace.
Commit: 98bb354a0add4aeb614430f48a23f87992166239
https://github.com/llvm/llvm-project/commit/98bb354a0add4aeb614430f48a23f87992166239
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
Log Message:
-----------
[SLP]Fix PR107037: correctly track origonal/modified after vectorizations reduced values
Need to correctly track reduced values with multiple uses in the same
reduction emission attempt. Otherwise, the number of the reuses might be
calculated incorrectly, and may cause compiler crash.
Fixes https://github.com/llvm/llvm-project/issues/107037
Commit: d3c10b51a99d4476261f57ceaa7db60960cd5493
https://github.com/llvm/llvm-project/commit/d3c10b51a99d4476261f57ceaa7db60960cd5493
Author: Peter Lafreniere <peter at n8pjl.ca>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/test/CodeGen/M68k/Arith/add.ll
R llvm/test/CodeGen/M68k/Arith/sext-i1.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
A llvm/test/CodeGen/M68k/Data/link-unlnk.ll
A llvm/test/CodeGen/M68k/Data/load-extend.ll
A llvm/test/CodeGen/M68k/Data/load-imm.ll
A llvm/test/CodeGen/M68k/Data/sext-i1.ll
R llvm/test/CodeGen/M68k/link-unlnk.ll
R llvm/test/CodeGen/M68k/load-extend.ll
Log Message:
-----------
[M68k] Introduce more MOVI cases (#98377)
Add three more special cases for loading registers with immediates.
The first allows values in the range of [-255, 255] to be loaded with
MOVEQ, even if the register is more than 8 bits and the sign extention
is unwanted. This is done by loading the bitwise complement of the
desired value, then performing a NOT instruction on the loaded register.
This special case is only used when a simple MOVEQ cannot be used, and
is only used for 32 bit data registers. Address registers cannot support
MOVEQ, and the two-instruction sequence is no faster or smaller than a
plain MOVE instruction when loading 16 bit immediates on the 68000, and
likely slower for more sophisticated microarchitectures. However, the
instruction sequence is both smaller and faster than the corresponding
MOVE instruction for 32 bit register widths.
The second special case is for zeroing address registers. This simply
expands to subtracting a register with itself, consuming one instruction
word rather than 2-3, with a small improvement in speed as well.
The last special case is for assigning sign-extended 16-bit values to a
full address register. This takes advantage of the fact that the movea.w
instruction sign extends the output, permitting the immediate to be
smaller. This is similar to using lea with a 16-bit address, which is
not added in this patch as 16-bit absolute addressing is not yet
implemented.
This is a v2 submission of #90817. It also creates a 'Data' test
directory to better align with the backend's tablegen layout.
Commit: 1c874bbbd67c5795113fa307512ea514f06dac29
https://github.com/llvm/llvm-project/commit/1c874bbbd67c5795113fa307512ea514f06dac29
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/half-select-icmp.ll
Log Message:
-----------
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
Select only needs branches and moves so we don't need to promote it.
Promoting would canonicalize NaNs which select shouldn't do.
Commit: b24a304435632710bb54a0cd9cda1757abb8c160
https://github.com/llvm/llvm-project/commit/b24a304435632710bb54a0cd9cda1757abb8c160
Author: Daniel Bertalan <dani at danielbertalan.dev>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
Log Message:
-----------
[lld-macho] Always store symbol name length eagerly (NFC) (#106906)
The only instance where we weren't already passing a `StringRef` with a
known length to `Symbol`'s constructor is where the argument is a string
literal. Even in that case, lazy `strlen` calls don't make sense, as the
compiler can constant-evaluate the `StringRef(const char*)` constructor.
For symbols that go into the symbol table we need the length when
calculating the hash anyway. We could get away with not calling
`getName()` for local symbols, but the total contribution of `strlen` to
the run time is already below 1%, so that would just complicate the code
for a negligible benefit.
Commit: 3209766608d14fbb0add96916a28c3f98fed9460
https://github.com/llvm/llvm-project/commit/3209766608d14fbb0add96916a28c3f98fed9460
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Transforms/IPO/ModuleInliner.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
A llvm/test/Analysis/CtxProfAnalysis/inline.ll
A llvm/test/Analysis/CtxProfAnalysis/json_equals.py
M llvm/test/Analysis/CtxProfAnalysis/load.ll
M llvm/unittests/Transforms/Utils/CallPromotionUtilsTest.cpp
Log Message:
-----------
[ctx_prof] Add Inlining support (#106154)
Add an overload of `InlineFunction` that updates the contextual profile. If there is no contextual profile, this overload is equivalent to the non-contextual profile variant.
Post-inlining, the update mainly consists of:
- making the PGO instrumentation of the callee "the caller's": the owner function (the "name" parameter of the instrumentation instructions) becomes the caller, and new index values are allocated for each of the callee's indices (this happens for both increment and callsite instrumentation instructions)
- in the contextual profile:
- each context corresponding to the caller has its counters updated to incorporate the counters inherited from the callee at the inlined callsite. Counter values are copied as-is because no scaling is required since the profile is contextual.
- the contexts of the callee (at the inlined callsite) are moved to the caller.
- the callee context at the inlined callsite is deleted.
Commit: dce73e115e11cf75c0e50fb96a9ba046c880838e
https://github.com/llvm/llvm-project/commit/dce73e115e11cf75c0e50fb96a9ba046c880838e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
R llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
Log Message:
-----------
Revert "[SLP]Fix PR107037: correctly track origonal/modified after vectorizations reduced values"
This reverts commit 98bb354a0add4aeb614430f48a23f87992166239 to fix
buildbots https://lab.llvm.org/buildbot/#/builders/155/builds/2056 and https://lab.llvm.org/buildbot/#/builders/11/builds/4407
Commit: 18263c319092b878f25dd4025830f8e6691245d4
https://github.com/llvm/llvm-project/commit/18263c319092b878f25dd4025830f8e6691245d4
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_context.cpp
Log Message:
-----------
[compiler-rt][rtsan] Add scoped reporting lock (#107167)
Uses a static lock to ensure multiple threads reporting issues at the
same time don't have printing collisions. This isn't so important now,
but will be with continue mode in the future.
Commit: b076f6640e3c2781410588f4a8e4ccfeed8eb606
https://github.com/llvm/llvm-project/commit/b076f6640e3c2781410588f4a8e4ccfeed8eb606
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M lldb/source/Target/TargetProperties.td
M lldb/test/API/functionalities/memory/big-read/TestMemoryReadMaximumSize.py
Log Message:
-----------
[lldb] Remove limit on max memory read size (#105765)
`memory read` will return an error if you try to read more than 1k bytes
in a single command, instructing you to set
`target.max-memory-read-size` or use `--force` if you intended to read
more than that. This is a safeguard for a command where people are being
explicit about how much memory they would like lldb to read (either to
display, or save to a file) and is an annoyance every time you need to
read more than a small amount. If someone confuses the --count argument
with the start address, lldb may begin dumping gigabytes of data but I'd
rather that behavior than requiring everyone to special-case their way
around a common use case.
I don't want to remove the setting because many people have added (much
larger) default max read sizes to their ~/.lldbinit files after hitting
this behavior. Another option would be to stop reading/using the value
in Target.cpp, but I see no harm in leaving the setting if someone
really does prefer to have a small cap on their memory read size.
Commit: 3e8840ba71bfcceeb598c2ca28d2d8784e24ba1e
https://github.com/llvm/llvm-project/commit/3e8840ba71bfcceeb598c2ca28d2d8784e24ba1e
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/VectorBuilder.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/IR/VectorBuilder.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
Remove "Target" from createXReduction naming [nfc]
Despite the stale comments, none of these actually use TTI, and they're
solely generating standard LLVM IR.
Commit: eaa95a1c2bd38332c1a4e634595f29d22b28ffea
https://github.com/llvm/llvm-project/commit/eaa95a1c2bd38332c1a4e634595f29d22b28ffea
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/test/CXX/drs/cwg24xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add test for CWG2486 (`noexcept` and function pointer conversion) (#107131)
[CWG2486](https://cplusplus.github.io/CWG/issues/2486.html) "Call to
`noexcept` function via `noexcept(false)` pointer/lvalue" allows
`noexcept` functions to be called via `noexcept(false)` pointers or
values. There appears to be no implementation divergence whatsoever:
https://godbolt.org/z/3afTfeEM8. That said, in C++14 and earlier we do
not issue all the diagnostics we issue in C++17 and newer, so I'm
specifying the status of the issue accordingly.
Commit: 83ad644afaac23577e3563d3ec1fac1b1fde37f4
https://github.com/llvm/llvm-project/commit/83ad644afaac23577e3563d3ec1fac1b1fde37f4
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.def
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10_2_512bf16intrin.h
A clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c
A clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
A llvm/test/CodeGen/X86/avx10.2-fma-commute.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt
A llvm/test/MC/X86/avx10.2-bf16-32-att.s
A llvm/test/MC/X86/avx10.2-bf16-32-intel.s
A llvm/test/MC/X86/avx10.2-bf16-64-att.s
A llvm/test/MC/X86/avx10.2-bf16-64-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86][AVX10.2] Support AVX10.2-BF16 new instructions. (#101603)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
Commit: 814aa432abf8e9f644903061029e6e27f6a418a8
https://github.com/llvm/llvm-project/commit/814aa432abf8e9f644903061029e6e27f6a418a8
Author: vporpo <vporpodas at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantAggregate (#107136)
This patch implements sandboxir:: ConstantAggregate, ConstantStruct,
ConstantArray and ConstantVector, mirroring LLVM IR.
Commit: 48bc8b0f7f49f5b23884a0d9d21056ec0bfffe24
https://github.com/llvm/llvm-project/commit/48bc8b0f7f49f5b23884a0d9d21056ec0bfffe24
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 83ad644afaac
Commit: ff0f2011e475141454028bce9cf7c6ff37a49620
https://github.com/llvm/llvm-project/commit/ff0f2011e475141454028bce9cf7c6ff37a49620
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
Log Message:
-----------
[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)
Previously, if Zfbfmin/Zfhmin were enabled, we only handled
build_vectors that could be turned into splat_vectors. We promoted them
to f32 splats by extending in the scalar domain and narrowing in the
vector domain.
This patch fixes a crash where we failed to account for whether the f32
vector type fit in LMUL<=8.
Because the new lowering occurs after type legalization, we have to be
careful to use XLenVT for the scalar integer type and use custom cast
nodes.
Commit: f1615e32379ff1ea125a8b3ac8792c3e0b5e6f2c
https://github.com/llvm/llvm-project/commit/f1615e32379ff1ea125a8b3ac8792c3e0b5e6f2c
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
Log Message:
-----------
[WebAssembly] Remove Kind argument from WebAssemblyOperand (NFC) (#107157)
The `Kind` argument does not need to passed separately.
Commit: c8763f04bf2162d3f0f4f967dfeb2f0feda0c75b
https://github.com/llvm/llvm-project/commit/c8763f04bf2162d3f0f4f967dfeb2f0feda0c75b
Author: Yun-Fly <yunfei.song at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
[mlir][tensor] Fix consumer fusion for `tensor.pack` without explicit `outer_dims_perm` attribute (#106687)
Commit: 99f02a874984f2b79c3fbd8ae6bbceb7366521ad
https://github.com/llvm/llvm-project/commit/99f02a874984f2b79c3fbd8ae6bbceb7366521ad
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
A clang/test/CXX/drs/cwg1818.cpp
M clang/test/CXX/drs/cwg18xx.cpp
A clang/test/CXX/drs/cwg563.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add tests for CWG issues about language linkage (#107019)
This patch covers Core issues about language linkage during declaration
matching resolved in
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html),
namely [CWG563](https://cplusplus.github.io/CWG/issues/563.html) and
[CWG1818](https://cplusplus.github.io/CWG/issues/1818.html).
[CWG563](https://cplusplus.github.io/CWG/issues/563.html) "Linkage
specification for objects"
-----------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
> [CWG563](https://cplusplus.github.io/CWG/issues/563.html) is resolved
by simplifications that follow its suggestions.
Wording ([[dcl.link]/5](https://eel.is/c++draft/dcl.link#5)):
> In a
[linkage-specification](https://eel.is/c++draft/dcl.link#nt:linkage-specification),
the specified language linkage applies to the function types of all
function declarators and to all functions and variables whose names have
external linkage[.](https://eel.is/c++draft/dcl.link#5.sentence-5)
Now the wording clearly says that linkage-specification applies to
variables with external linkage.
[CWG1818](https://cplusplus.github.io/CWG/issues/1818.html) "Visibility
and inherited language linkage"
------------
[P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html):
>
[CWG386](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#386),
[CWG1839](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1839),
[CWG1818](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1818),
[CWG2058](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#2058),
[CWG1900](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_active.html#1900),
and Richard’s observation in [“are non-type names ignored in a
class-head-name or
enum-head-name?”](http://lists.isocpp.org/core/2017/01/1604.php) are
resolved by describing the limited lookup that occurs for a
declarator-id, including the changes in Richard’s [proposed resolution
for
CWG1839](http://wiki.edg.com/pub/Wg21cologne2019/CoreWorkingGroup/cwg1839.html)
(which also resolves CWG1818 and what of CWG2058 was not resolved along
with CWG2059) and rejecting the example from
[CWG1477](http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#1477).
Wording ([[dcl.link]/6](https://eel.is/c++draft/dcl.link#6)):
> A redeclaration of an entity without a linkage specification inherits
the language linkage of the entity and (if applicable) its
type[.](https://eel.is/c++draft/dcl.link#6.sentence-2).
Answer to the question in the example is `extern "C"`, and not linkage
mismatch. Further analysis of the example is provided as inline comments
in the test itself. Note that https://eel.is/c++draft/dcl.link#7 does
NOT apply in this example, as it's focused squarely at declarations that
are already known to have C language linkage, and declarations of
variables in the global scope.
Commit: b057e16740311b9c690c0c991c48b5087bf24d9a
https://github.com/llvm/llvm-project/commit/b057e16740311b9c690c0c991c48b5087bf24d9a
Author: Reid Kleckner <rnk at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemorySSA.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/OperandTraits.h
M llvm/include/llvm/IR/Operator.h
M llvm/include/llvm/IR/User.h
M llvm/lib/IR/ConstantsContext.h
Log Message:
-----------
[IR] Remove unused MINARITY operand trait tpl args, NFC (#107165)
These don't look like they've been used since the original 'use-diet'
branch was merged in 2008 ( f6caff66a1bfa6464e6a17c0bcfcf06a09a9b909)
Commit: ed220e15718498d0f854f1044ddcbfee00739aa7
https://github.com/llvm/llvm-project/commit/ed220e15718498d0f854f1044ddcbfee00739aa7
Author: Elvis Wang <110374989+ElvisWang123 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan][NFC] Implement `VPWidenMemoryRecipe::computeCost()`. (#105614)
In this patch, we implement the `computeCost()` function in
`VPWidenMemoryRecipe`.
Commit: 9b5971ad0355d43a9bd37b1067d93ff8b08eba81
https://github.com/llvm/llvm-project/commit/9b5971ad0355d43a9bd37b1067d93ff8b08eba81
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-extmul.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
[AArch64][GlobalISel] Lower G_BUILD_VECTOR to G_INSERT_VECTOR_ELT (#105686)
The lowering happens in post-legalizer lowering if any source registers
from G_BUILD_VECTOR are not constants.
Add pattern pragment setting `scalar_to_vector ($src)` asequivalent to
`vector_insert (undef), ($src), (i61 0)`
Commit: 12c0823d67a8d5a61d6430aac609ef5e468267a6
https://github.com/llvm/llvm-project/commit/12c0823d67a8d5a61d6430aac609ef5e468267a6
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/tools/clang-format/git-clang-format.bat
Log Message:
-----------
[clang-format] Handle spaces in file paths in git-clang-format.bat (#107041)
This patch is provided by @jeliebig.
Fixes #107017.
Commit: a27ff17034d66d852ba83be7d237d6a623cb4ff4
https://github.com/llvm/llvm-project/commit/a27ff17034d66d852ba83be7d237d6a623cb4ff4
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a regression in annotating ObjCBlockLParen (#107021)
Fixes #106994.
Commit: b55186eefd73b3848e01c8471c47a9354969d652
https://github.com/llvm/llvm-project/commit/b55186eefd73b3848e01c8471c47a9354969d652
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/test/Preprocessor/init-ppc.c
M clang/test/Preprocessor/init-ppc64.c
Log Message:
-----------
[clang][Driver] Define soft float macros for PPC. (#106012)
Fixes #105972.
Co-authored-by: Qiu Chaofan <qcf at ecnelises.com>
Commit: 8d0816615f920b0783bafa903804b9e2a2fa4e91
https://github.com/llvm/llvm-project/commit/8d0816615f920b0783bafa903804b9e2a2fa4e91
Author: yifeizh2 <yifei.zhang at intel.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[MLIR][Tensor] Fix source/dest type check in UnPackOp canonicalize (#106094)
Fix `RankedTensorType` equality check in unpack op canonicalization.
Commit: 812c96e8b9354e5e84d513f5b03172db5ad3b491
https://github.com/llvm/llvm-project/commit/812c96e8b9354e5e84d513f5b03172db5ad3b491
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Handle pointer/reference in macro definitions (#107074)
A macro definition needs its own scope stack in the annotator, so we add
the MacroBodyScopes stack and use ScopeStack to refer to it when in the
macro definition body.
Also, we need to have a scope type for a child block because its parent
line is parsed (and thus the scope type for the braces is popped off the
scope stack) before the lines in the child block are.
Fixes #99271.
Commit: f4b9839d6f7c9ec2967a42f2d5546a2a2ae77ca4
https://github.com/llvm/llvm-project/commit/f4b9839d6f7c9ec2967a42f2d5546a2a2ae77ca4
Author: Longsheng Mou <moulongsheng at huawei.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/lib/Conversion/TensorToSPIRV/TensorToSPIRV.cpp
M mlir/test/Conversion/TensorToSPIRV/tensor-ops-to-spirv.mlir
Log Message:
-----------
[mlir][TensorToSPIRV] Add type check for `tensor.extract` in TensorToSPIRV (#107110)
This patch add a type check for `tensor.extract` in TensorToSPIRV.
Only convert `tensor.extract` with supported element type. Fix #74466.
Commit: 37263b6c6741894ffbc0f61979c5c85db515ef2d
https://github.com/llvm/llvm-project/commit/37263b6c6741894ffbc0f61979c5c85db515ef2d
Author: Longsheng Mou <moulongsheng at huawei.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
[mlir][tosa] Add verifier for `tosa.pad` (#106351)
This patch adds verifier to `tosa.pad` which fixes a crash. `tosa.pad`
expect:
- same input and output tensor rank.
- 'padding' tensor rank equal to 2.
Fix #106168.
Commit: a628bc3c2e7314e4b7c9af0d10cf39a70c731d15
https://github.com/llvm/llvm-project/commit/a628bc3c2e7314e4b7c9af0d10cf39a70c731d15
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
Log Message:
-----------
[AArch64] Fix a warning
This patch fixes:
lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc:506:14:
error: unused variable 'GIMatchData_matchinfo'
[-Werror,-Wunused-variable]
Commit: 9a17a6016d02afa6e973f141ab1cada68571f2d2
https://github.com/llvm/llvm-project/commit/9a17a6016d02afa6e973f141ab1cada68571f2d2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Log Message:
-----------
[PowerPC] Use DenseMap::operator[] (NFC) (#107044)
Commit: f15e3e58c59b4d31eee24fa9debc5dfad0c20028
https://github.com/llvm/llvm-project/commit/f15e3e58c59b4d31eee24fa9debc5dfad0c20028
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
[CGOpenMPRuntime] Use DenseMap::operator[] (NFC) (#107158)
I'm planning to deprecate DenseMap::FindAndConstruct in favor of
DenseMap::operator[].
Commit: 86627149f6fd5148311b7b0aa1c7195a05a5d6a8
https://github.com/llvm/llvm-project/commit/86627149f6fd5148311b7b0aa1c7195a05a5d6a8
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
A llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
A llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
Log Message:
-----------
[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)
Any SGPR read by a VALU can potentially obscure SALU writes to the same
register.
Insert s_wait_alu instructions to mitigate the hazard on affected paths.
Compute a global cache of SGPRs with any VALU reads and use this to
avoid inserting mitigation for SGPRs never accessed by VALUs.
To avoid excessive search when compile time is priority implement
secondary mode where all SALU writes are mitigated.
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: a5ce66423bfff6f2185e5fe48bc6ffc0ade7df4d
https://github.com/llvm/llvm-project/commit/a5ce66423bfff6f2185e5fe48bc6ffc0ade7df4d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
Log Message:
-----------
[RISCV] Remove RISCVISD::FP_ROUND_BF16.
Use isel patterns on regular FP_ROUND. For double->bf16 we need
to emit two instructions. Note the double->bf16 conversion does
double rounding, but I don't know a good way to fix that.
Commit: 0ad6cee926865d7210eed9e67bfb20dce19c6633
https://github.com/llvm/llvm-project/commit/0ad6cee926865d7210eed9e67bfb20dce19c6633
Author: Elvis Wang <110374989+ElvisWang123 at users.noreply.github.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/cast.ll
Log Message:
-----------
[RISCV] Fix missing `i64` to `double` tests in the cast.ll. (NFC) (#106972)
Commit: 8b28e2ebb36d72cfffe04904e3e1b9fdfa36ef94
https://github.com/llvm/llvm-project/commit/8b28e2ebb36d72cfffe04904e3e1b9fdfa36ef94
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
Log Message:
-----------
[WebAssembly] Rename legacy EH tests (#107166)
Give each test in `cfg-stackify-eh-legacy.ll` a name rather than
something like `test5`, because I plan to copy many of these test into a
new file that tests for the new EH (exnref) and some of the tests here
are not applicable to the new EH so the numbering will be different,
which can make things confusing.
Also this removes `test_` prefixes in the test function names in
`exception-legacy.ll`, because, well, we all know they are tests.
Commit: 9fef09fd2918e7d8c357b98a9a798fe207941f73
https://github.com/llvm/llvm-project/commit/9fef09fd2918e7d8c357b98a9a798fe207941f73
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
M clang/test/CodeGen/X86/x86-atomic-double.c
M clang/test/CodeGen/X86/x86-atomic-long_double.c
Log Message:
-----------
[Clang][CodeGen] Fix type for atomic float incdec operators (#107075)
`llvm::ConstantFP::get(llvm::LLVMContext&, APFloat(float))` always
returns a f32 constant.
Fix https://github.com/llvm/llvm-project/issues/107054.
Commit: 6c607cfb2c2d8acd2b92d7ed8106ab1e4fc0d79d
https://github.com/llvm/llvm-project/commit/6c607cfb2c2d8acd2b92d7ed8106ab1e4fc0d79d
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
Log Message:
-----------
[RISCV] Preserve tail agnostic policy in foldVMV_V_V (#105788)
This patch helps avoid regressions in an upcoming patch by making sure
we don't accidentally lose a tail agnostic policy when folding a vmv.v.v
into its source.
The previous comment about RISCVInsertVSETVLI relaxing the policy didn't
take into account the fact that there's a policy operand on vmv.v.v,
which can be tail agnostic.
If the tail is agnostic (via either the policy operand or the passthru
being undef) and vmv.v.v's VL <= Src's VL, then Src's tail can be made
agnostic.
Commit: c94bd96c277e0b48e198fdc831bb576d9a04aced
https://github.com/llvm/llvm-project/commit/c94bd96c277e0b48e198fdc831bb576d9a04aced
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGStmt.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
Log Message:
-----------
[Clang][CodeGen] Don't emit assumptions if current block is unreachable. (#106936)
Fixes https://github.com/llvm/llvm-project/issues/106898.
When emitting an infinite loop, clang codegen will delete the whole
block and leave builder's current block as nullptr:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/clang/lib/CodeGen/CGStmt.cpp#L597-L600
Then clang will create `zext (icmp slt %a, %b)` without parent block for
`a < b`. It will crash here:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/clang/lib/CodeGen/CGExprScalar.cpp#L416-L420
Even if we disabled this optimization, it still crashes in
`Builder.CreateAssumption`:
https://github.com/llvm/llvm-project/blob/837ee5b46a5f7f898f0de7e46a19600b896a0a1f/llvm/lib/IR/IRBuilder.cpp#L551-L561
This patch disables assumptions emission if current block is null.
Commit: 3e798476de466e8a051d3e753db379731a8d9705
https://github.com/llvm/llvm-project/commit/3e798476de466e8a051d3e753db379731a8d9705
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
Log Message:
-----------
[LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32 when we don't have Zvfh. (#106652)
The fp_extend will canonicalize NaNs which is not the semantics of
FNEG/FABS/FCOPYSIGN.
For fixed vectors I'm scalarizing due to test changes on other targets
where the scalarization is expected. I will try to address in a follow
up.
For scalable vectors, we bitcast to integer and use integer logic ops.
Commit: 41402c6a8aa3a4336122bdb4530fb05538efedba
https://github.com/llvm/llvm-project/commit/41402c6a8aa3a4336122bdb4530fb05538efedba
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
Log Message:
-----------
[RISCV][GISel] Use CCValAssign::getCustomReg for converting f16/f32<->GPR. (#105700)
This gives us much better control of the generated code for GISel. I've
tried to closely match the current gisel code, but it looks like we had
2 layers of G_ANYEXT in some cases before.
SelectionDAG now checks needsCustom() instead of detecting the special
cases in the Bitcast handler.
Unfortunately, IRTranslator for bitcast still generates copies between
register classes of different sizes. Because of this we can't handle
i16<->f16 bitcasts without crashing. Not sure if I should teach
RISCVInstrInfo::copyPhysReg to allow copies between FPR16 and GPR or if
I should convert the copies to instructions in GISel.
Commit: 4a44898be5d46694b59aa411f2b45a52f2ce8411
https://github.com/llvm/llvm-project/commit/4a44898be5d46694b59aa411f2b45a52f2ce8411
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
Log Message:
-----------
[RISCV] Add passthru to vmv.v.v intrinsic tests. NFC
This prevents them from being optimized away in an upcoming peephole
Commit: 3449ed8dece600f387357b71ff74ae4bc46828b6
https://github.com/llvm/llvm-project/commit/3449ed8dece600f387357b71ff74ae4bc46828b6
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
Revert "[clang-format] Correctly annotate braces in macro definition (#106662)"
This reverts commit 0fa78b6c7bd43c2498700a98c47a02cf4fd06388 due to
regression.
Fixes #107096.
Commit: 7deda4ed0c712fb830d25f4e3090ff04f7adbcf9
https://github.com/llvm/llvm-project/commit/7deda4ed0c712fb830d25f4e3090ff04f7adbcf9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Use MCRegister for variables returned from AllocateReg. NFC
Avoids a cast from Register to MCRegister for the CCValAssign
functions.
Commit: 06286832db0c4ee1899f9cee1b8f6234e45f16c7
https://github.com/llvm/llvm-project/commit/06286832db0c4ee1899f9cee1b8f6234e45f16c7
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-04 (Wed, 04 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
Reland "Revert "AtomicExpand: Allow incrementally legalizing atomicrmw"" (#106793)
Reverts llvm/llvm-project#106792
The first commit of PR is pure revert, the rest is a possible fix.
Commit: ddd0116f8190dc64051d2fa48dba8693a861a0bd
https://github.com/llvm/llvm-project/commit/ddd0116f8190dc64051d2fa48dba8693a861a0bd
Author: Florian Mayer <fmayer at google.com>
Date: 2024-09-03 (Tue, 03 Sep 2024)
Changed paths:
M bolt/lib/Profile/YAMLProfileReader.cpp
A bolt/test/X86/yaml-unknown-keys.test
M bolt/tools/merge-fdata/merge-fdata.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/BuiltinsX86.def
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10_2_512bf16intrin.h
A clang/lib/Headers/avx10_2bf16intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaAvailability.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaX86.cpp
A clang/test/CXX/drs/cwg1818.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg24xx.cpp
A clang/test/CXX/drs/cwg563.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
A clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c
A clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M clang/test/CodeGen/X86/x86-atomic-double.c
M clang/test/CodeGen/X86/x86-atomic-long_double.c
M clang/test/Driver/debug-options-as.c
M clang/test/FixIt/fixit-availability-maccatalyst.m
M clang/test/FixIt/fixit-availability.mm
M clang/test/Preprocessor/init-ppc.c
M clang/test/Preprocessor/init-ppc64.c
M clang/test/SemaCXX/cxx23-assume.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
M clang/tools/clang-format/git-clang-format.bat
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/www/c_status.html
M clang/www/cxx_dr_status.html
M compiler-rt/lib/rtsan/rtsan_context.cpp
M compiler-rt/lib/scudo/standalone/secondary.h
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
M lldb/docs/conf.py
M lldb/include/lldb/Utility/SupportFile.h
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/Target/TargetProperties.td
M lldb/test/API/functionalities/memory/big-read/TestMemoryReadMaximumSize.py
M lldb/tools/lldb-dap/package.json
M llvm/docs/conf.py
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Analysis/DominanceFrontier.h
M llvm/include/llvm/Analysis/DominanceFrontierImpl.h
M llvm/include/llvm/Analysis/MemorySSA.h
M llvm/include/llvm/CodeGen/MachineDominanceFrontier.h
M llvm/include/llvm/IR/Constants.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/OperandTraits.h
M llvm/include/llvm/IR/Operator.h
M llvm/include/llvm/IR/User.h
M llvm/include/llvm/IR/VectorBuilder.h
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/VectorBuilder.cpp
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Transforms/IPO/ModuleInliner.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/CostModel/RISCV/cast.ll
M llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
A llvm/test/Analysis/CtxProfAnalysis/inline.ll
A llvm/test/Analysis/CtxProfAnalysis/json_equals.py
M llvm/test/Analysis/CtxProfAnalysis/load.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-extmul.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
A llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
A llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
M llvm/test/CodeGen/M68k/Arith/add.ll
R llvm/test/CodeGen/M68k/Arith/sext-i1.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
A llvm/test/CodeGen/M68k/Data/link-unlnk.ll
A llvm/test/CodeGen/M68k/Data/load-extend.ll
A llvm/test/CodeGen/M68k/Data/load-imm.ll
A llvm/test/CodeGen/M68k/Data/sext-i1.ll
R llvm/test/CodeGen/M68k/link-unlnk.ll
R llvm/test/CodeGen/M68k/load-extend.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/half-select-icmp.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
A llvm/test/CodeGen/X86/avx10.2-fma-commute.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2bf16-arith.ll
A llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
M llvm/test/CodeGen/X86/clobber_frame_ptr.ll
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
A llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt
A llvm/test/MC/X86/avx10.2-bf16-32-att.s
A llvm/test/MC/X86/avx10.2-bf16-32-intel.s
A llvm/test/MC/X86/avx10.2-bf16-64-att.s
A llvm/test/MC/X86/avx10.2-bf16-64-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-whole-regs-loads.ll
R llvm/test/Transforms/SLPVectorizer/RISCV/unique-loads-insert-non-power-of-2.ll
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
M llvm/unittests/Transforms/Utils/CallPromotionUtilsTest.cpp
M llvm/utils/TableGen/VTEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/TensorToSPIRV/TensorToSPIRV.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TensorToSPIRV/tensor-ops-to-spirv.mlir
M mlir/test/Dialect/Tensor/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/19c3293d1d99...ddd0116f8190
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