[all-commits] [llvm/llvm-project] 9b5971: [AArch64][GlobalISel] Lower G_BUILD_VECTOR to G_IN...

[chuongg3 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9b5971ad0355d43a9bd37b1067d93ff8b08eba81
      https://github.com/llvm/llvm-project/commit/9b5971ad0355d43a9bd37b1067d93ff8b08eba81
  Author: chuongg3 <chuong.goh at arm.com>
  Date:   2024-09-03 (Tue, 03 Sep 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
    M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll
    M llvm/test/CodeGen/AArch64/abs.ll
    M llvm/test/CodeGen/AArch64/add.ll
    M llvm/test/CodeGen/AArch64/andorxor.ll
    M llvm/test/CodeGen/AArch64/arm64-dup.ll
    M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
    M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
    M llvm/test/CodeGen/AArch64/arm64-tbl.ll
    M llvm/test/CodeGen/AArch64/bitcast.ll
    M llvm/test/CodeGen/AArch64/bswap.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/fabs.ll
    M llvm/test/CodeGen/AArch64/faddsub.ll
    M llvm/test/CodeGen/AArch64/fcmp.ll
    M llvm/test/CodeGen/AArch64/fcopysign.ll
    M llvm/test/CodeGen/AArch64/fcvt.ll
    M llvm/test/CodeGen/AArch64/fdiv.ll
    M llvm/test/CodeGen/AArch64/fexplog.ll
    M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
    M llvm/test/CodeGen/AArch64/fminimummaximum.ll
    M llvm/test/CodeGen/AArch64/fminmax.ll
    M llvm/test/CodeGen/AArch64/fmla.ll
    M llvm/test/CodeGen/AArch64/fmul.ll
    M llvm/test/CodeGen/AArch64/fneg.ll
    M llvm/test/CodeGen/AArch64/fpow.ll
    M llvm/test/CodeGen/AArch64/fpowi.ll
    M llvm/test/CodeGen/AArch64/fptoi.ll
    M llvm/test/CodeGen/AArch64/fptrunc.ll
    M llvm/test/CodeGen/AArch64/frem.ll
    M llvm/test/CodeGen/AArch64/fsincos.ll
    M llvm/test/CodeGen/AArch64/fsqrt.ll
    M llvm/test/CodeGen/AArch64/icmp.ll
    M llvm/test/CodeGen/AArch64/insertextract.ll
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/llvm.exp10.ll
    M llvm/test/CodeGen/AArch64/load.ll
    M llvm/test/CodeGen/AArch64/mul.ll
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
    M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
    M llvm/test/CodeGen/AArch64/neon-extadd.ll
    M llvm/test/CodeGen/AArch64/neon-extmul.ll
    M llvm/test/CodeGen/AArch64/neon-perm.ll
    M llvm/test/CodeGen/AArch64/ptradd.ll
    M llvm/test/CodeGen/AArch64/rem.ll
    M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/sext.ll
    M llvm/test/CodeGen/AArch64/shift.ll
    M llvm/test/CodeGen/AArch64/shufflevector.ll
    M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
    M llvm/test/CodeGen/AArch64/sub.ll
    M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll
    M llvm/test/CodeGen/AArch64/xtn.ll
    M llvm/test/CodeGen/AArch64/zext.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Lower G_BUILD_VECTOR to G_INSERT_VECTOR_ELT (#105686)

The lowering happens in post-legalizer lowering if any source registers
from G_BUILD_VECTOR are not constants.

Add pattern pragment setting `scalar_to_vector ($src)` asequivalent to
`vector_insert (undef), ($src), (i61 0)`



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