[all-commits] [llvm/llvm-project] d3c10b: [M68k] Introduce more MOVI cases (#98377)

[Peter Lafreniere via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d3c10b51a99d4476261f57ceaa7db60960cd5493
      https://github.com/llvm/llvm-project/commit/d3c10b51a99d4476261f57ceaa7db60960cd5493
  Author: Peter Lafreniere <peter at n8pjl.ca>
  Date:   2024-09-03 (Tue, 03 Sep 2024)

  Changed paths:
    M llvm/lib/Target/M68k/M68kInstrInfo.cpp
    M llvm/test/CodeGen/M68k/Arith/add.ll
    R llvm/test/CodeGen/M68k/Arith/sext-i1.ll
    M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
    A llvm/test/CodeGen/M68k/Data/link-unlnk.ll
    A llvm/test/CodeGen/M68k/Data/load-extend.ll
    A llvm/test/CodeGen/M68k/Data/load-imm.ll
    A llvm/test/CodeGen/M68k/Data/sext-i1.ll
    R llvm/test/CodeGen/M68k/link-unlnk.ll
    R llvm/test/CodeGen/M68k/load-extend.ll

  Log Message:
  -----------
  [M68k] Introduce more MOVI cases (#98377)

Add three more special cases for loading registers with immediates.

The first allows values in the range of [-255, 255] to be loaded with
MOVEQ, even if the register is more than 8 bits and the sign extention
is unwanted. This is done by loading the bitwise complement of the
desired value, then performing a NOT instruction on the loaded register.

This special case is only used when a simple MOVEQ cannot be used, and
is only used for 32 bit data registers. Address registers cannot support
MOVEQ, and the two-instruction sequence is no faster or smaller than a
plain MOVE instruction when loading 16 bit immediates on the 68000, and
likely slower for more sophisticated microarchitectures. However, the
instruction sequence is both smaller and faster than the corresponding
MOVE instruction for 32 bit register widths.

The second special case is for zeroing address registers. This simply
expands to subtracting a register with itself, consuming one instruction
word rather than 2-3, with a small improvement in speed as well.

The last special case is for assigning sign-extended 16-bit values to a
full address register. This takes advantage of the fact that the movea.w
instruction sign extends the output, permitting the immediate to be
smaller. This is similar to using lea with a 16-bit address, which is
not added in this patch as 16-bit absolute addressing is not yet
implemented.

This is a v2 submission of #90817. It also creates a 'Data' test
directory to better align with the backend's tablegen layout.



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