[all-commits] [llvm/llvm-project] ec8e1c: [RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ec8e1c623a78536b956cc2c1d42ae75c4024ad66
      https://github.com/llvm/llvm-project/commit/ec8e1c623a78536b956cc2c1d42ae75c4024ad66
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-03 (Tue, 03 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll

  Log Message:
  -----------
  [RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)

This avoids having isel patterns that emit two instrutions. It also
allows us to remove sext.w and slli+srli pairs by using fcvt.s.w(u) on
RV64.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications