[all-commits] [llvm/llvm-project] 7852eb: [BPF] Make -mcpu=v3 as the default (#107008)

[yonghong-song via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7852ebc088b925ef1c1940cbd56a93d9f8e3e330
      https://github.com/llvm/llvm-project/commit/7852ebc088b925ef1c1940cbd56a93d9f8e3e330
  Author: yonghong-song <yhs at fb.com>
  Date:   2024-09-03 (Tue, 03 Sep 2024)

  Changed paths:
    M clang/lib/Basic/Targets/BPF.cpp
    M clang/test/Preprocessor/bpf-predefined-macros.c
    M llvm/lib/Target/BPF/BPFSubtarget.cpp
    M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
    M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1-bpfeb.ll
    M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll
    M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2-bpfeb.ll
    M llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-1.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-2.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-byte-size-3.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-1.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-2.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-3.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1-bpfeb.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-1.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-lshift-2.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-1.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-2.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-rshift-3.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-1.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-2.ll
    M llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-signedness-3.ll
    M llvm/test/CodeGen/BPF/CORE/no-narrow-load.ll
    M llvm/test/CodeGen/BPF/CORE/offset-reloc-end-load.ll
    M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll
    M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2-bpfeb.ll
    M llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll
    M llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll
    M llvm/test/CodeGen/BPF/adjust-opt-icmp2.ll
    M llvm/test/CodeGen/BPF/adjust-opt-icmp3.ll
    M llvm/test/CodeGen/BPF/adjust-opt-icmp4.ll
    M llvm/test/CodeGen/BPF/adjust-opt-icmp5.ll
    M llvm/test/CodeGen/BPF/adjust-opt-icmp6.ll
    M llvm/test/CodeGen/BPF/adjust-opt-speculative1.ll
    M llvm/test/CodeGen/BPF/adjust-opt-speculative2.ll
    M llvm/test/CodeGen/BPF/alu8.ll
    M llvm/test/CodeGen/BPF/atomics.ll
    M llvm/test/CodeGen/BPF/basictest.ll
    M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
    M llvm/test/CodeGen/BPF/cc_args.ll
    M llvm/test/CodeGen/BPF/cc_args_be.ll
    M llvm/test/CodeGen/BPF/cc_ret.ll
    M llvm/test/CodeGen/BPF/cmp.ll
    M llvm/test/CodeGen/BPF/cttz-ctlz.ll
    M llvm/test/CodeGen/BPF/ex1.ll
    M llvm/test/CodeGen/BPF/fi_ri.ll
    M llvm/test/CodeGen/BPF/i128.ll
    M llvm/test/CodeGen/BPF/intrinsics.ll
    M llvm/test/CodeGen/BPF/load.ll
    M llvm/test/CodeGen/BPF/loops.ll
    M llvm/test/CodeGen/BPF/many_args1.ll
    M llvm/test/CodeGen/BPF/objdump_atomics.ll
    M llvm/test/CodeGen/BPF/objdump_cond_op.ll
    M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
    M llvm/test/CodeGen/BPF/objdump_imm_hex.ll
    M llvm/test/CodeGen/BPF/objdump_intrinsics.ll
    M llvm/test/CodeGen/BPF/objdump_nop.ll
    M llvm/test/CodeGen/BPF/objdump_static_var.ll
    M llvm/test/CodeGen/BPF/objdump_trivial.ll
    M llvm/test/CodeGen/BPF/pr57872.ll
    M llvm/test/CodeGen/BPF/reloc-2.ll
    M llvm/test/CodeGen/BPF/remove_truncate_1.ll
    M llvm/test/CodeGen/BPF/remove_truncate_2.ll
    M llvm/test/CodeGen/BPF/remove_truncate_3.ll
    M llvm/test/CodeGen/BPF/remove_truncate_6.ll
    M llvm/test/CodeGen/BPF/remove_truncate_8.ll
    M llvm/test/CodeGen/BPF/rodata_1.ll
    M llvm/test/CodeGen/BPF/rodata_2.ll
    M llvm/test/CodeGen/BPF/rodata_3.ll
    M llvm/test/CodeGen/BPF/rodata_4.ll
    M llvm/test/CodeGen/BPF/rodata_6.ll
    M llvm/test/CodeGen/BPF/rodata_7.ll
    M llvm/test/CodeGen/BPF/sanity.ll
    M llvm/test/CodeGen/BPF/setcc.ll
    M llvm/test/CodeGen/BPF/shifts.ll
    M llvm/test/CodeGen/BPF/sockex2.ll
    M llvm/test/CodeGen/BPF/undef.ll
    M llvm/test/CodeGen/BPF/xadd.ll
    M llvm/test/CodeGen/BPF/xadd_legal.ll
    M llvm/test/tools/llvm-objdump/BPF/interleaved-source-test.ll

  Log Message:
  -----------
  [BPF] Make -mcpu=v3 as the default (#107008)

Before llvm20, (void)__sync_fetch_and_add(...) always generates locked
xadd insns. In linux kernel upstream discussion [1], it is found that
for arm64 architecture, the original semantics of
(void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is
preferred in order for jit to emit proper native barrier insns.

In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will
generate the following insns:
  - for cpu v1/v2: locked xadd insns to keep backward compatibility
  - for cpu v3/v4: __atomic_fetch_add() insns

To ensure proper barrier semantics for (void)__sync_fetch_and_add(...),
cpu v3/v4 is recommended.

This patch enables cpu=v3 as the default cpu version. For users wanting
to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc
command line.

  [1]
https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f
  [2] https://github.com/llvm/llvm-project/pull/101428
  [3] https://github.com/llvm/llvm-project/pull/106494



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