[all-commits] [llvm/llvm-project] 9cf686: [ARM] Fix failure to register-allocate CMP_SWAP_64...

[Oliver Stannard via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9cf68679c4f45e79d67c94ef1f968c7c1213b610
      https://github.com/llvm/llvm-project/commit/9cf68679c4f45e79d67c94ef1f968c7c1213b610
  Author: Oliver Stannard <oliver.stannard at arm.com>
  Date:   2024-09-02 (Mon, 02 Sep 2024)

  Changed paths:
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    A llvm/test/CodeGen/ARM/atomic-64bit-fast-regalloc.ll
    M llvm/test/CodeGen/ARM/atomic-load-store.ll
    M llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
    M llvm/test/CodeGen/ARM/cmpxchg-O0.ll
    M llvm/test/CodeGen/ARM/cmpxchg.mir
    M llvm/test/CodeGen/Thumb2/cmpxchg.mir

  Log Message:
  -----------
  [ARM] Fix failure to register-allocate CMP_SWAP_64 pseudo-inst (#106721)

This test case was failing to compile with a "ran out of registers
during register allocation" error at -O0. This was because CMP_SWAP_64
has 3 operands which must be an even-odd register pair, and two other
GPR operands. All of the def operands are also early-clobber, so
registers can't be shared between uses and defs. Because the function
has an over-aligned alloca it needs frame and base pointers, so r6 and
r11 are both reserved. That leaves r0/r1, r2/r3, r4/r5 and r8/r9 as the
only valid register pairs, and if the two individual GPR operands happen
to get allocated to registers in different pairs then only 2 pairs will
be available for the three GPRPair operands.

To fix this, I've merged the two GPR operands into a single GPRPair
operand. This means that the instruction now has 4 GPRPair operands,
which can always be allocated without relying on luck. This does
constrain register allocation a bit more, but this pseudo instruction is
only used at -O0, so I don't think that's a problem.



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