[all-commits] [llvm/llvm-project] 3bdec3: [RISCV] Custom legalize f16/bf16 FNEG/FABS with Zf...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3bdec313160918c908ea469713764174d8a7d17c
      https://github.com/llvm/llvm-project/commit/3bdec313160918c908ea469713764174d8a7d17c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-31 (Sat, 31 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/bfloat-arith.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/half-arith-strict.ll
    M llvm/test/CodeGen/RISCV/half-arith.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

  Log Message:
  -----------
  [RISCV] Custom legalize f16/bf16 FNEG/FABS with Zfhmin/Zbfmin. (#106886)

The LegalizeDAG expansion will go through memory since i16 isn't a legal
type. Avoid this by using FMV nodes.



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