[all-commits] [llvm/llvm-project] 0efa38: [RISCV] Check VL dominates and potentially move in...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0efa38699a4988793cdd51426fe27f00b5e5ce37
      https://github.com/llvm/llvm-project/commit/0efa38699a4988793cdd51426fe27f00b5e5ce37
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-08-31 (Sat, 31 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    A llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.ll
    A llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir

  Log Message:
  -----------
  [RISCV] Check VL dominates and potentially move in tryReduceVL (#106753)

Similar to what we do in foldVMV_V_V with the passthru, if we end up
changing the Src's VL in tryReduceVL we need to make sure it dominates.

Fixes #106735



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