[all-commits] [llvm/llvm-project] aa91d9: [LegalizeVectorOps][PowerPC] Use xor to expand fne...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa91d90cb07d72b32176a966fe798ab71ecb0a76
      https://github.com/llvm/llvm-project/commit/aa91d90cb07d72b32176a966fe798ab71ecb0a76
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-29 (Thu, 29 Aug 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/test/CodeGen/PowerPC/fma-negate.ll
    M llvm/test/CodeGen/PowerPC/fp-strict.ll
    M llvm/test/CodeGen/PowerPC/vec_abs.ll
    M llvm/test/CodeGen/PowerPC/vec_fneg.ll

  Log Message:
  -----------
  [LegalizeVectorOps][PowerPC] Use xor to expand fneg. (#106595)

This preserves the semantis of fneg and matches what we do in
LegalizeDAG.

I kept the legal FSUB check to force unrolling for some targets that
don't have FSUB but have XOR. On Aarch64, using xor broke some tests that
expected to see a (v1f64 (fma (insertvector_elt (f64 (fneg
(extractvectorelt X)))))) pattern.



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