[all-commits] [llvm/llvm-project] 619efd: [RISCV] Fix v[f]slide1down.vx having VL changed (#...
Alexander Richardson via All-commits
all-commits at lists.llvm.org
Thu Aug 29 09:33:48 PDT 2024
Branch: refs/heads/users/arichardson/spr/compiler-rt-work-around-incompatible-windows-definitions-of-ssize_t
Home: https://github.com/llvm/llvm-project
Commit: 619efd75da77415e016c79c37a0fabe573ce1845
https://github.com/llvm/llvm-project/commit/619efd75da77415e016c79c37a0fabe573ce1845
Author: Luke Lau <luke at igalia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
A llvm/test/CodeGen/RISCV/rvv/pr106109.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
Log Message:
-----------
[RISCV] Fix v[f]slide1down.vx having VL changed (#106110)
v[f]slide1down.vx uses VL to determine where the element is inserted
into, so changing the VL changes the result.
This fixes this by setting ActiveElementsAffectsResult, but it's overly
conservative. We should relax this later by modelling that it's ok to
change the mask, just not VL.
Fixes #106109
Commit: 051054e6f74303bc880221e88671745f363964cc
https://github.com/llvm/llvm-project/commit/051054e6f74303bc880221e88671745f363964cc
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
Log Message:
-----------
[clang][RISCV] Remove `experimental` for vector crypto intrinsics (#106359)
The C intrinsic spec is ratified:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234.
Commit: 572d2fd327b3a55fe57f712813321a3c40c895cd
https://github.com/llvm/llvm-project/commit/572d2fd327b3a55fe57f712813321a3c40c895cd
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
A llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
Log Message:
-----------
[Attributor] Fix an issue that could potentially cause `AccessList` and `OffsetBins` out of sync (#106187)
The implementation of `AAPointerInfo::RangeList::set_difference` doesn't
consider the case where two ranges have the same offset but different
sizes.
This could cause `AccessList` and `OffsetBins` out of sync because a
range has
been already updated in `AccessList` but missing in `ToRemove`.
I do have a reproducer but the reproducer itself is 248kb. `llvm-reduce`
can't
further reduce it. Not sure how I can make a smaller reproducer.
Fixes: SWDEV-479757.
Commit: 9d81e7e36e33aecdee05fef551c0652abafaa052
https://github.com/llvm/llvm-project/commit/9d81e7e36e33aecdee05fef551c0652abafaa052
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
Log Message:
-----------
workflows/release-tasks: Pass required secrets to all called workflows (#106286)
Called workflows don't have access to secrets by default, so we need to
explicitly pass secrets that we use.
Commit: 95361cf3306760378c4798963405ed4cd6410f15
https://github.com/llvm/llvm-project/commit/95361cf3306760378c4798963405ed4cd6410f15
Author: Christopher Bate <cbate at nvidia.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M mlir/lib/Conversion/SCFToControlFlow/CMakeLists.txt
Log Message:
-----------
[mlir] fix missing LLVMDialect dependency for MLIRSCFToControlFlow
This is a fix-forward for 8bf69ceb00bb56dd5c7357f192846518a6893f3c.
The SCF-to-ControlFlow pass has an explicit LLVMDialect dependency.
Commit: 62c5de36e8a523cc81950a782a4b6182393681c4
https://github.com/llvm/llvm-project/commit/62c5de36e8a523cc81950a782a4b6182393681c4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-28 (Wed, 28 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Log Message:
-----------
[RISCV] Fix a place that convert an immediate to MCRegister and back to immediate.
This dropped the upper 32 bits of the immediate, but I'm not sure
it is ever non-zero.
Commit: 2adc94cd6c3dd1fc713a6ba8301fc04f21908700
https://github.com/llvm/llvm-project/commit/2adc94cd6c3dd1fc713a6ba8301fc04f21908700
Author: Akshat Oke <76596238+Akshat-Oke at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
A llvm/lib/Target/AMDGPU/SIFoldOperands.h
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
M llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
Log Message:
-----------
AMDGPU/NewPM: Port SIFoldOperands to new pass manager (#105801)
Commit: 3b64ede096ce0a0230c4d3f77782e6fa18f2943a
https://github.com/llvm/llvm-project/commit/3b64ede096ce0a0230c4d3f77782e6fa18f2943a
Author: Luke Lau <luke at igalia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
Log Message:
-----------
[RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv (#104574)
As far as I'm aware, vrgather.vv is quadratic in LMUL on most
microarchitectures today due to each output register needing to read
from each input register in the group.
For example, the reciprocal throughput for vrgather.vv on the
spacemit-x60 is listed on
https://camel-cdr.github.io/rvv-bench-results/bpi_f3 as:
LMUL1 LMUL2 LMUL4 LMUL8
4.0 16.0 64.0 256.1
Vector reverses are commonly emitted by the loop vectorizer and are
lowered as vrgather.vvs, but since the loop vectorizer uses LMUL 2 by
default they end up being quadratic.
The output registers in a reverse only need to read from one input
register though, so we can decompose this into LMUL * M1 vrgather.vvs to
get linear performance.
This gives a 0.43% runtime improvement on 526.blender_r at rva22u64_v O3
on the Banana Pi F3.
Commit: 8f96be921c1a97594ee94c2789cee9b131525f63
https://github.com/llvm/llvm-project/commit/8f96be921c1a97594ee94c2789cee9b131525f63
Author: Lang Hames <lhames at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/tools/bugpoint/CMakeLists.txt
Log Message:
-----------
[bugpoint] Fix bugpoint for LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES=Off.
Building with -DLLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES=Off should not
prevent use of bugpoint plugins.
This fix uses the approach implemented in
https://github.com/llvm/llvm-project/pull/101741.
Commit: c7a4efa4294789b1116f0c4a320c16fcb27cb62c
https://github.com/llvm/llvm-project/commit/c7a4efa4294789b1116f0c4a320c16fcb27cb62c
Author: Patryk Wychowaniec <pwychowaniec at pm.me>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
A llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
A llvm/test/CodeGen/AVR/std-immediate-overflow.ll
Log Message:
-----------
[AVR] Fix 16-bit LDDs with immediate overflows (#104923)
16-bit loads are expanded into a pair of 8-bit loads, so the maximum
offset of such 16-bit loads must be 62, not 63.
Commit: 7f59264d469d690fcd1cead0a2dfc02739d17db4
https://github.com/llvm/llvm-project/commit/7f59264d469d690fcd1cead0a2dfc02739d17db4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/test/Transforms/SCCP/pointer-nonnull.ll
M llvm/test/Transforms/SCCP/range-attribute.ll
Log Message:
-----------
[IPSCCP] Intersect attribute info for interprocedural args (#106397)
IPSCCP can currently return worse results than SCCP for arguments that
are tracked interprocedurally, because information from attributes is
not used for them.
Fix this by intersecting in the attribute information when propagating
lattice values from calls.
Commit: c954306ef763eb25f06432324889bde98735963d
https://github.com/llvm/llvm-project/commit/c954306ef763eb25f06432324889bde98735963d
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_console.py
Log Message:
-----------
[lldb][lldb-dap][test] Enable more tests on Windows
These tests "just work" on our Windows On Arm machine.
Commit: 47615ff2347a8be429404285de3b1c03b411e7af
https://github.com/llvm/llvm-project/commit/47615ff2347a8be429404285de3b1c03b411e7af
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/pr106483.cppm
Log Message:
-----------
[C++20] [Modules] Don't insert class not in named modules to PendingEmittingVTables (#106501)
Close https://github.com/llvm/llvm-project/issues/102933
The root cause of the issue is an oversight in
https://github.com/llvm/llvm-project/pull/102287 that I didn't notice
that PendingEmittingVTables should only accept classes in named modules.
Commit: e5b55e606796bac0e28e2f0fdc6fb39a419f6b15
https://github.com/llvm/llvm-project/commit/e5b55e606796bac0e28e2f0fdc6fb39a419f6b15
Author: Lang Hames <lhames at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/tools/clang-repl/CMakeLists.txt
Log Message:
-----------
[clang-repl] Fix clang-repl for LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES=Off.
clang-repl should stil work when LLVM is built with
-DLLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES=Off.
This fix uses the approach implemented in
https://github.com/llvm/llvm-project/pull/101741.
rdar://134910110
Commit: 2eeeff842f993a694159183a2834b4d305549cad
https://github.com/llvm/llvm-project/commit/2eeeff842f993a694159183a2834b4d305549cad
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/test/Modules/no-local-decl-in-reduced-bmi.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview-std.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview.cppm
M clang/test/Modules/unreached-static-entities.cppm
Log Message:
-----------
[C++20] [Modules] Embed all source files for C++20 Modules (#102444)
Close https://github.com/llvm/llvm-project/issues/72383
The implementation rationale is, I don't want to pass
`-fmodules-embed-all-files` all the time since we can't test it in lit
tests (we're using `clang_cc1`). So I tried to set it in FrontendActions
for modules.
Commit: b822b69ff54bcd2f08445bd02b8dad0584422874
https://github.com/llvm/llvm-project/commit/b822b69ff54bcd2f08445bd02b8dad0584422874
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
M clang/test/Driver/print-multi-selection-flags.c
Log Message:
-----------
[Driver] Add -mbranch-protection to ARM and AArch64 multilib flags (#106391)
This adds the `-mbranch-protection` command line option to the set of
flags used by the multilib selection for ARM and AArch64 targets.
Commit: b7981a78f0aaea1500d79a519c0be03c69d9b1ac
https://github.com/llvm/llvm-project/commit/b7981a78f0aaea1500d79a519c0be03c69d9b1ac
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/MeshShardingInterfaceImpl.cpp
Log Message:
-----------
[mlir] Apply ClangTidyPerformance finding (NFC).
Use const reference for loop variable.
Commit: efad561890ad3584c38adae913f9939384eb804c
https://github.com/llvm/llvm-project/commit/efad561890ad3584c38adae913f9939384eb804c
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/Chunks.h
M lld/COFF/Writer.cpp
A lld/test/COFF/arm64ec-range-thunks.s
Log Message:
-----------
[LLD][COFF] Add support for range extension thunks for ARM64EC targets. (#106289)
Thunks themselves are the same as regular ARM64 thunks; they just need
to report the correct machine type. When processing the code, we also
need to use the current chunk's machine type instead of the global one:
we don't want to treat x86_64 thunks as ARM64EC, and we need to report
the correct machine type in hybrid binaries.
Commit: f9ee9f5b39b3840e5fd6bb54ebb7830a98f8f0af
https://github.com/llvm/llvm-project/commit/f9ee9f5b39b3840e5fd6bb54ebb7830a98f8f0af
Author: VisdaVokhshoori <31481804+VisdaVokhshoori at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/docs/TestSuiteGuide.md
Log Message:
-----------
[llvm][Docs] Update TestSuiteGuide.md (#79613)
Update svn to git & virtualenv to venv
Commit: ae34257e9015a366ea63cd461535b35bc9837c57
https://github.com/llvm/llvm-project/commit/ae34257e9015a366ea63cd461535b35bc9837c57
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
Log Message:
-----------
[lldb][lldb-dap][test] Skip logpoint test on Windows again
This one snuck into the previous patch. The test program needs
updating if it's ever going to work on Windows.
Commit: c9b6e01b2e4fc930dac91dd44c0592ad7e36d967
https://github.com/llvm/llvm-project/commit/c9b6e01b2e4fc930dac91dd44c0592ad7e36d967
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize-with-call.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize.ll
R llvm/test/tools/llvm-split/AMDGPU/debug-name-hiding.ll
R llvm/test/tools/llvm-split/AMDGPU/debug-non-kernel-root.ll
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-alias-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-cost-ranking.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-external.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-overridable.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables-noexternal.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependency-indirect.ll
A llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
A llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
Log Message:
-----------
[AMDGPU] Graph-based Module Splitting Rewrite (#104763)
Major rewrite of the AMDGPUSplitModule pass in order to better support
it long-term.
Highlights:
- Removal of the "SML" logging system in favor of just using CL options
and LLVM_DEBUG, like any other pass in LLVM.
- The SML system started from good intentions, but it was too flawed and
messy to be of any real use. It was also a real pain to use and made the
code more annoying to maintain.
- Graph-based module representation with DOTGraph printing support
- The graph represents the module accurately, with bidirectional, typed
edges between nodes (a node usually represents one function).
- Nodes are assigned IDs starting from 0, which allows us to represent a
set of nodes as a BitVector. This makes comparing 2 sets of nodes to
find common dependencies a trivial task. Merging two clusters of nodes
together is also really trivial.
- No more defaulting to "P0" for external calls
- Roots that can reach non-copyable dependencies (such as external
calls) are now grouped together in a single "cluster" that can go into
any partition.
- No more defaulting to "P0" for indirect calls
- New representation for module splitting proposals that can be graded
and compared.
- Graph-search algorithm that can explore multiple branches/assignments
for a cluster of functions, up to a maximum depth.
- With the default max depth of 8, we can create up to 256 propositions
to try and find the best one.
- We can still fall back to a greedy approach upon reaching max depth.
That greedy approach uses almost identical heuristics to the previous
version of the pass.
All of this gives us a lot of room to experiment with new heuristics or
even entirely different splitting strategies if we need to. For
instance, the graph representation has room for abstract nodes, e.g. if
we need to represent some global variables or external constraints. We
could also introduce more edge types to model other type of relations
between nodes, etc.
I also designed the graph representation & the splitting strategies to
be as fast as possible, and it seems to have paid off. Some quick tests
showed that we spend pretty much all of our time in the CloneModule
function, with the actual splitting logic being >1% of the runtime.
Commit: e37d6d2a74d76fdc95f5c5d625e282ce600aad55
https://github.com/llvm/llvm-project/commit/e37d6d2a74d76fdc95f5c5d625e282ce600aad55
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir
M mlir/test/Dialect/ArmSME/tile-zero-masks.mlir
Log Message:
-----------
[mlir][ArmSME] Merge consecutive `arm_sme.intr.zero` ops (#106215)
This merges consecutive SME zero intrinsics within a basic block, which
avoids the backend eventually emitting multiple zero instructions when
it could just use one.
Note: This kind of peephole optimization could be implemented in the
backend too.
Commit: 31684c676a9983277666df2ac845a563f4d68e19
https://github.com/llvm/llvm-project/commit/31684c676a9983277666df2ac845a563f4d68e19
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
R llvm/test/tools/llvm-split/AMDGPU/declarations-debug.ll
Log Message:
-----------
[AMDGPU][llvm-split] Remove declarations-debug
Test didn't have a FileCheck line and is obsolete after #104763
Commit: b9f4afa1674fe6f101b298d4893cde2ab2d16877
https://github.com/llvm/llvm-project/commit/b9f4afa1674fe6f101b298d4893cde2ab2d16877
Author: Daniel Grumberg <dgrumberg at apple.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/include/clang/ExtractAPI/API.h
M clang/lib/ExtractAPI/API.cpp
Log Message:
-----------
[clang][ExtractAPI] Fix iteration order of TopLevelRecords (#106411)
Fixes #106355
Commit: 575be3efb056b298bd4cbf9a04c324893e208488
https://github.com/llvm/llvm-project/commit/575be3efb056b298bd4cbf9a04c324893e208488
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
Log Message:
-----------
[AMDGPU][llvm-split] Make declarations test more stable
Delete the previous files if present, to ensure it won't fail if the output directory of the tests wasn't cleared.
Commit: fdca2c33a1f33f4886d969ea0f0219764c7b6b59
https://github.com/llvm/llvm-project/commit/fdca2c33a1f33f4886d969ea0f0219764c7b6b59
Author: Akshat Oke <76596238+Akshat-Oke at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
A llvm/lib/Target/AMDGPU/GCNDPPCombine.h
M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
Log Message:
-----------
AMDGPU/NewPM Port GCNDPPCombine to NPM (#105816)
Co-authored-by: Akshat Oke <Akshat.Oke at amd.com>
Commit: 60e9fb9dae0e041cb468210f5795e9d59e70cccf
https://github.com/llvm/llvm-project/commit/60e9fb9dae0e041cb468210f5795e9d59e70cccf
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
Log Message:
-----------
[Flang][OpenMP] Don't expect block arguments using early privatization (#105842)
There are some spots where all symbols to privatize collected by a
`DataSharingProcessor` instance are expected to have corresponding entry
block arguments associated regardless of whether delayed privatization
was enabled.
This can result in compiler crashes if a `DataSharingProcessor` instance
created with `useDelayedPrivatization=false` is queried in this way. The
solution proposed by this patch is to provide another public method to
query specifically delayed privatization symbols, which will either be
empty or point to the complete set of symbols to privatize accordingly.
Commit: c28b84e30b7bb5816c71c72546a8e4167d1e1b5d
https://github.com/llvm/llvm-project/commit/c28b84e30b7bb5816c71c72546a8e4167d1e1b5d
Author: JoelWee <32009741+JoelWee at users.noreply.github.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Update BUILD.bazel after e37d6d2a74d7
Commit: 2505546aee8b35d03d7755b0f8e6cd960295928e
https://github.com/llvm/llvm-project/commit/2505546aee8b35d03d7755b0f8e6cd960295928e
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/riscv.c
Log Message:
-----------
[compiler-rt][RISCV][NFC] Update code_model with latest spec (#106498)
The spec could be found here
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74
This patch updates the following symbol:
```
mVendorID -> mvendorid
mArchID -> marchid
mImplID -> mimpid
```
Commit: 911b96058a94a10a3897a56af703992c4509965b
https://github.com/llvm/llvm-project/commit/911b96058a94a10a3897a56af703992c4509965b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
PPC: Custom lower ppcf128 is_fpclass if is_fpclass is custom (#105540)
Unfortunately expandIS_FPCLASS is called directly in SelectionDAGBuilder
depending on whether IS_FPCLASS is custom or not. This helps avoid ppc test
regressions in a future patch where the custom lowering would be bypassed.
Commit: 7b7b0b95b2bb8e72fb60438409b12d8eabf484a2
https://github.com/llvm/llvm-project/commit/7b7b0b95b2bb8e72fb60438409b12d8eabf484a2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/PowerPC/is_fpclass.ll
Log Message:
-----------
DAG: Check if is_fpclass is custom, instead of isLegalOrCustom (#105577)
For some reason, isOperationLegalOrCustom is not the same as
isOperationLegal || isOperationCustom. Unfortunately, it checks
if the type is legal which makes it uesless for custom lowering
on non-legal types (which is always ppcf128).
Really the DAG builder shouldn't be going to expand this in the
builder, it makes it difficult to work with. It's only here to work
around the DAG requiring legal integer types the same size as
the FP type after type legalization.
Commit: fcb3a0485857c749d04ea234a8c3d629c62ab211
https://github.com/llvm/llvm-project/commit/fcb3a0485857c749d04ea234a8c3d629c62ab211
Author: Luke Shingles <luke.shingles at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Support/Z3Solver.cpp
Log Message:
-----------
[analyzer] Add missing include <unordered_map> to llvm/lib/Support/Z3Solver.cpp (#106410)
Resolves #106361. Adding #include <unordered_map> to
llvm/lib/Support/Z3Solver.cpp fixes compilation errors for homebrew
build on macOS with Xcode 14.
https://github.com/Homebrew/homebrew-core/actions/runs/10604291631/job/29390993615?pr=181351
shows that this is resolved when the include is patched in (Linux CI
failure is due to unrelated timeout).
Commit: 36b7c30b292f853c09b80f8bc2c5f233f68c9e7b
https://github.com/llvm/llvm-project/commit/36b7c30b292f853c09b80f8bc2c5f233f68c9e7b
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
A llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
M llvm/utils/TableGen/X86DisassemblerTables.cpp
Log Message:
-----------
[X86, MC] Recognize OSIZE=64b when EVEX.W = 1, EVEX.pp = 01 (#103816)
In the legacy space, if both the 66 prefix and REX.W=1 are present, the
REX.W=1 takes precedence and makes OSIZE=64b. EVEX map 4 inherits this
convention, with EVEX.pp=01 and EVEX.W playing the roles of the 66
prefix and REX.W. So if EVEX.pp=00, the OSIZE can only be 64b or 32b,
depending on whether EVEX.W=1 or not. But if EVEX.pp=01, then OSIZE is
either 64b or 16b depending on whether EVEX.W=1 or not.
Commit: ddbc8f331a708dacfbf0a41e8ae6b8f6d9605407
https://github.com/llvm/llvm-project/commit/ddbc8f331a708dacfbf0a41e8ae6b8f6d9605407
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
R llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred-parent.ll
R llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-sindle-bv.ll
R llvm/test/Transforms/SLPVectorizer/X86/arith-div-undef.ll
R llvm/test/Transforms/SLPVectorizer/X86/bool-logical-op-reduction-with-poison.ll
R llvm/test/Transforms/SLPVectorizer/X86/buildvector-insert-mask-size.ll
R llvm/test/Transforms/SLPVectorizer/X86/buildvector-nodes-dependency.ll
R llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/catchswitch.ll
R llvm/test/Transforms/SLPVectorizer/X86/crash_exceed_scheduling.ll
R llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast.ll
A llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
A llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
A llvm/test/Transforms/SLPVectorizer/arith-div-undef.ll
A llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
A llvm/test/Transforms/SLPVectorizer/buildvector-insert-mask-size.ll
A llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
A llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/catchswitch.ll
A llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
A llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
Log Message:
-----------
[SLP] Move some of X86 tests to common directory (#106401)
Some of the tests from X86 directory can be generalized for AArch64 to
improve its coverage.
Commit: 3ef37e2f8f672393ee409fde8309198df0981735
https://github.com/llvm/llvm-project/commit/3ef37e2f8f672393ee409fde8309198df0981735
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/CodeGen/Thumb2/pr52817.ll
M llvm/test/CodeGen/X86/fsafdo_test1.ll
M llvm/test/CodeGen/X86/fsafdo_test4.ll
A llvm/test/DebugInfo/Generic/is_stmt-at-block-start.ll
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
M llvm/test/DebugInfo/X86/discriminator.ll
Log Message:
-----------
[DebugInfo][DWARF] Set is_stmt on first non-line-0 instruction in BB (#105524)
Fixes: https://github.com/llvm/llvm-project/issues/104695
This patch adds the is_stmt flag to line table entries for the first
instruction with a non-0 line location in each basic block, to ensure
that it will be used for stepping even if the last instruction in the
previous basic block had the same line number; this is important for
cases where the new BB is reachable from BBs other than the preceding
block.
Commit: 2784060c167d86a05f20a0ab1892f96e69a2da20
https://github.com/llvm/llvm-project/commit/2784060c167d86a05f20a0ab1892f96e69a2da20
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[MLIR][Flang][OpenMP] Remove omp.parallel from loop wrapper ops (#105833)
This patch updates the `omp.parallel` operation according to the results
of the discussion in [this
RFC](https://discourse.llvm.org/t/rfc-disambiguation-between-loop-and-block-associated-omp-parallelop/79972).
It is removed from the set of loop wrapper operations, changing the
expected MLIR representation for composite `distribute parallel do/for`
into the following:
```mlir
omp.parallel {
...
omp.distribute {
omp.wsloop {
omp.loop_nest ... { ... }
omp.terminator
}
omp.terminator
}
...
omp.terminator
}
```
MLIR verifiers for operations impacted by this representation change are
updated, as well as related tests. The `LoopWrapperInterface` is also
updated, since it's no longer representing an optional "role" of an
operation but a mandatory set of restrictions instead.
Commit: 0f206b19c3303aeb8e527b4977da2bd301464a9b
https://github.com/llvm/llvm-project/commit/0f206b19c3303aeb8e527b4977da2bd301464a9b
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
Log Message:
-----------
[Flang][OpenMP] Move loop privatization out of dispatch (#106066)
This patch moves the creation of `DataSharingProcessor` instances for
loop constructs out of `genOMPDispatch()` and into their corresponding
codegen functions. This is a necessary first step to enable a proper
handling of privatization on composite constructs.
Some tests are updated due to a change of order between clause
processing and privatization.
Commit: 113806d187901ec3ca202ffa22ef94c80770a760
https://github.com/llvm/llvm-project/commit/113806d187901ec3ca202ffa22ef94c80770a760
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes-cvt.ll
Log Message:
-----------
[AArch64] optimise SVE cvt intrinsics with no active lanes (#104809)
This patch extends https://github.com/llvm/llvm-project/pull/73964 and
optimises SVE cvt intrinsics away when predicate is zero.
Commit: 9c8ce5fac8a05e27cca832fb3913ec986b120211
https://github.com/llvm/llvm-project/commit/9c8ce5fac8a05e27cca832fb3913ec986b120211
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/distribute-parallel-do.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-compound.f90
Log Message:
-----------
[Flang][OpenMP] DISTRIBUTE PARALLEL DO lowering (#106207)
This patch adds PFT to MLIR lowering support for `distribute parallel
do` composite constructs.
Commit: 57726c440c30b3f0b5ebfaf345b0237df4430259
https://github.com/llvm/llvm-project/commit/57726c440c30b3f0b5ebfaf345b0237df4430259
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-compound.f90
Log Message:
-----------
[Flang][OpenMP] DISTRIBUTE PARALLEL DO SIMD lowering (#106211)
This patch adds PFT to MLIR lowering support for `distribute parallel do
simd` composite constructs.
Commit: fdf72c992b2781de3f6c78698164e55a031a268e
https://github.com/llvm/llvm-project/commit/fdf72c992b2781de3f6c78698164e55a031a268e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/cmp-in-bv-node-type-cost.ll
Log Message:
-----------
[SLP]Fix a crash when requestin the cost for buildvector cmp nodes types.
Need to use original cmp type i1 when estimating the cost for the
buildvector node, not its operand types to prevent compiler crash upon
TTI cost estimation.
Commit: c3cb27370af40e491446164840766478d3258429
https://github.com/llvm/llvm-project/commit/c3cb27370af40e491446164840766478d3258429
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
Log Message:
-----------
Fix MSVC "not all control paths return a value" warning. NFC.
Commit: 616f7d3d4f6d9bea6f776e357c938847e522a681
https://github.com/llvm/llvm-project/commit/616f7d3d4f6d9bea6f776e357c938847e522a681
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
R llvm/test/DebugInfo/Generic/is_stmt-at-block-start.ll
A llvm/test/DebugInfo/X86/is_stmt-at-block-start.ll
Log Message:
-----------
[DebugInfo][NFC] Make is_stmt-at-block-start test X86-specific
Fixes failure on the llvm-clang-aarch64-darwin buildbot:
https://lab.llvm.org/buildbot/#/builders/190/builds/4660/
The test mentioned does not rely on any unique property of X86, but does
rely on the layout of the basic blocks produced by llc, which varies
between targets. Although the test could be duplicated for other targets,
it seems unnecessary since the behaviour being tested is not
target-specific.
Commit: 0a272d3a1703415abca42dc2e2cc2b57cb30734e
https://github.com/llvm/llvm-project/commit/0a272d3a1703415abca42dc2e2cc2b57cb30734e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
Log Message:
-----------
[LV] Use SCEV to analyze second operand for cost query.
Improve operand analysis using SCEV for cost purposes. This fixes a
divergence between legacy and VPlan-based cost-modeling after
533e6bbd0d34.
Fixes https://github.com/llvm/llvm-project/issues/106248.
Commit: 926f0979af4f6172d4ed3dea5603aa97c800bef1
https://github.com/llvm/llvm-project/commit/926f0979af4f6172d4ed3dea5603aa97c800bef1
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/CodeGen/Thumb2/pr52817.ll
M llvm/test/CodeGen/X86/fsafdo_test1.ll
M llvm/test/CodeGen/X86/fsafdo_test4.ll
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
M llvm/test/DebugInfo/X86/discriminator.ll
R llvm/test/DebugInfo/X86/is_stmt-at-block-start.ll
Log Message:
-----------
Revert "[DebugInfo][DWARF] Set is_stmt on first non-line-0 instruction in BB (#105524)"
Reverted (along with the NFC followup fix) due to buildbot failure:
https://lab.llvm.org/buildbot/#/builders/160/builds/4142
This reverts commit 3ef37e2f8f672393ee409fde8309198df0981735, and commit
616f7d3d4f6d9bea6f776e357c938847e522a681.
Commit: 606a9342f1083eef1475c2a97eabb04db9338bdd
https://github.com/llvm/llvm-project/commit/606a9342f1083eef1475c2a97eabb04db9338bdd
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
A llvm/test/Analysis/LoopAccessAnalysis/evaluate-at-symbolic-max-backedge-taken-count-may-wrap.ll
Log Message:
-----------
[LAA] Add test cases where evaluating AddRecs at symbolic max BTC wraps.
The underlying issue was discovered by an assert added in
a80053322b765eec939 by a test case provided by @mstorsjo.
Commit: 50515db57f1a8b3d7fd61c1df946a29971f65428
https://github.com/llvm/llvm-project/commit/50515db57f1a8b3d7fd61c1df946a29971f65428
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Format canVectorizeLoads after previous NFC patches.
Commit: 9167667b5c3cd1b166452c984f0c6448688c22a0
https://github.com/llvm/llvm-project/commit/9167667b5c3cd1b166452c984f0c6448688c22a0
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
M llvm/test/Transforms/SLPVectorizer/arith-div-undef.ll
M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-insert-mask-size.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
M llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/catchswitch.ll
M llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
Log Message:
-----------
[SLP] Fix REQUIRES line for failing tests (#106531)
Commit: cb608cc5f62baa01fe106a14ef41971337c2c030
https://github.com/llvm/llvm-project/commit/cb608cc5f62baa01fe106a14ef41971337c2c030
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
A clang/test/AST/ByteCode/cxx11-pedantic.cpp
Log Message:
-----------
[clang][bytecode] Properly diagnose non-const reads (#106514)
If the global variable is constant (but not constexpr), we need to
diagnose, but keep evaluating.
Commit: 25c9410fed7da0bc83bb0390f6e8d83470536fa0
https://github.com/llvm/llvm-project/commit/25c9410fed7da0bc83bb0390f6e8d83470536fa0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
Log Message:
-----------
[InstCombine][X86] Add vpermilpd/vpermilps test coverage for #106413
Commit: d57c04647e6f0a6f0cd79e280c257f570e8f30f4
https://github.com/llvm/llvm-project/commit/d57c04647e6f0a6f0cd79e280c257f570e8f30f4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
Log Message:
-----------
[InstCombine][X86] Only demand used bits for VPERMILPD/VPERMILPS mask values
VPERMILPS lower bits0-3 (to index per-lane i32/f32 0-3)
VPERMILPD uses bit1 (to index per-lane i64/f64 0-1)
Use SimplifyDemandedBits to ignore anything touching the remaining bits.
Part of #106413
Commit: 2a28df66dc3f7ff5b6233241837854acefb68d77
https://github.com/llvm/llvm-project/commit/2a28df66dc3f7ff5b6233241837854acefb68d77
Author: Hans <hans at hanshq.net>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/utils/release/build_llvm_release.bat
Log Message:
-----------
Restrict LLVM_TARGETS_TO_BUILD in Windows release packaging (#106059)
When including all targets, some files become too large for the NSIS
installer to handle.
Fixes #101994
Commit: b2a820faea960e99123f309d6a7bccb3cd1bcc12
https://github.com/llvm/llvm-project/commit/b2a820faea960e99123f309d6a7bccb3cd1bcc12
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/launch/main.c
Log Message:
-----------
[lldb][lldb-dap][test] Enable Launch tests
Add Windows include equivalents for includes and shell command.
Commit: 0a484820e1d34b051831624cbe237bba578ac2d8
https://github.com/llvm/llvm-project/commit/0a484820e1d34b051831624cbe237bba578ac2d8
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/docs/CodeOfConduct.rst
Log Message:
-----------
Restore missing link in CodeOfConduct.rst (#106385)
Link restored from the original policy outlined here
https://discourse.llvm.org/t/code-of-conduct-changes-related-to-llvm-project-policy-changes/64197
Commit: 73ef397fcba35b7b4239c00bf3e0b4e689ca0add
https://github.com/llvm/llvm-project/commit/73ef397fcba35b7b4239c00bf3e0b4e689ca0add
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libc/src/string/memory_utils/x86_64/inline_memcpy.h
Log Message:
-----------
[libc][x86] Use prefetch for write for memcpy (#90450)
Currently when `LIBC_COPT_MEMCPY_X86_USE_SOFTWARE_PREFETCHING` is set we
prefetch memory for read on the source buffer. This patch adds prefetch
for write on the destination buffer.
Commit: acff429191a27a164a0941346ce0c73e953d4638
https://github.com/llvm/llvm-project/commit/acff429191a27a164a0941346ce0c73e953d4638
Author: kadir çetinkaya <kadircet at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang-tools-extra/include-cleaner/lib/WalkAST.cpp
M clang-tools-extra/include-cleaner/unittests/WalkASTTest.cpp
Log Message:
-----------
[include-cleaner] Mark RecordDecls referenced in UsingDecls as explicit (#106430)
We were reporting ambigious references from using declarations as user
can be depending on different overloads of a function just because they
are visible in the TU.
This doesn't apply to records, or primary templates as declaration being
referenced in such cases is unambigious, the ambiguity applies to
specializations though.
Hence this patch returns an explicit reference to record decls and
primary templates of those.
Commit: 7955760bc82c792b84a4d97913f5b8e0f4902108
https://github.com/llvm/llvm-project/commit/7955760bc82c792b84a4d97913f5b8e0f4902108
Author: Koakuma <koachan at protonmail.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/Sparc/SparcInstrAliases.td
M llvm/test/MC/Sparc/sparc-misc-instructions.s
Log Message:
-----------
[SPARC][IAS] Add `illtrap` alias for `unimp` (#105928)
This follows Solaris behavior of allowing both mnemonics all the time.
Fixes https://github.com/llvm/llvm-project/issues/105639.
Commit: ba52a09abe3f3a2323dd7df3fe1739630e054077
https://github.com/llvm/llvm-project/commit/ba52a09abe3f3a2323dd7df3fe1739630e054077
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/SCCP/pointer-nonnull.ll
Log Message:
-----------
[IPSCCP] Add test for returning nonnull pointer (NFC)
Commit: 43661a1214353ea1773a711f403f8d1118e9ca0f
https://github.com/llvm/llvm-project/commit/43661a1214353ea1773a711f403f8d1118e9ca0f
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
Log Message:
-----------
[RemoveDIs] Fix spliceDebugInfo splice-to-end edge case (#105671)
Fix #105571 which demonstrates an end() iterator dereference when
performing a non-empty splice to end() from a region that ends at
Src::end().
Rather than calling Instruction::adoptDbgRecords from Dest, create a marker
(which takes an iterator) and absorbDebugValues onto that. The "absorb" variant
doesn't clean up the source marker, which in this case we know is a trailing
marker, so we have to do that manually.
Commit: 1f8f2ed66ab742a1fbb4a84411e656cb8324e107
https://github.com/llvm/llvm-project/commit/1f8f2ed66ab742a1fbb4a84411e656cb8324e107
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
Log Message:
-----------
[NFC][AMDGPU] Autogenerate tests for uniform i32 promo in ISel (#106382)
Many tests were easy to update, but these are quite big and I think it's
better to autogenerate them to see the difference well.
Commit: df11ee213e43ae373d1357939cf14ea37d547110
https://github.com/llvm/llvm-project/commit/df11ee213e43ae373d1357939cf14ea37d547110
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBlock.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Diagnose member calls on deleted blocks (#106529)
This requires a bit of restructuring of ctor calls when checking for a
potential constant expression.
Commit: c57abc66e223393cda27760e3f2409f4a1aa895e
https://github.com/llvm/llvm-project/commit/c57abc66e223393cda27760e3f2409f4a1aa895e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
Log Message:
-----------
[LoopVectorize][X86] amdlibm-calls.ll - cleanup test checks for 2/4/8/16 vector widths
This cleans up the existing tests and shows the gaps in the test checks (for instance we're often testing VF4 + VF16 but not VF8 even though amdlibm supports it).
Commit: 2f95298727bc9b682ad2d058119862ee8b0d8ec2
https://github.com/llvm/llvm-project/commit/2f95298727bc9b682ad2d058119862ee8b0d8ec2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
Log Message:
-----------
[LoopVectorize][X86] amdlibm-calls.ll - add additional 2/4/8/16 vector widths test checks
This should cover most amdlibm functions, but still not added every VF combo (e.g. 2f32/16f64 often vectorises to the llvm intrinsic for that vector type)
Commit: f7d6dfa005ac3d136e38658f25b8c54daa1ef08c
https://github.com/llvm/llvm-project/commit/f7d6dfa005ac3d136e38658f25b8c54daa1ef08c
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/console/TestDAP_redirection_to_console.py
M lldb/test/API/tools/lldb-dap/coreFile/TestDAP_coreFile.py
Log Message:
-----------
[lldb][lldb-dap] Enable more tests on Windows
These few worked without changes.
Commit: 56152fa377302fd8124e8be2a02dcb927a041f0a
https://github.com/llvm/llvm-project/commit/56152fa377302fd8124e8be2a02dcb927a041f0a
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Analysis/CMakeLists.txt
Log Message:
-----------
[Analysis] Guard logf128 cst folding (#106543)
LLVM has a CMake variable to control whether to consider logf128
constant folding which libAnalysis ignores. This patch changes the
logf128 check to rely on the global LLVM_HAS_LOGF128 setting made in
config-ix.cmake.
Commit: 5fef40c2c477e92187bd4e5c18091eca6b8465cc
https://github.com/llvm/llvm-project/commit/5fef40c2c477e92187bd4e5c18091eca6b8465cc
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/CodeGen/Thumb2/pr52817.ll
M llvm/test/CodeGen/X86/fsafdo_test1.ll
M llvm/test/CodeGen/X86/fsafdo_test4.ll
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
M llvm/test/DebugInfo/X86/discriminator.ll
A llvm/test/DebugInfo/X86/is_stmt-at-block-start.ll
Log Message:
-----------
Reapply "[DebugInfo][DWARF] Set is_stmt on first non-line-0 instruction in BB (#105524)"
Fixes the previous buildbot error by adding an explicit triple to the test,
ensuring that llc can produce a valid object file.
This reverts commit 926f0979af4f6172d4ed3dea5603aa97c800bef1.
Commit: 8ae877a089d9c2ca5315d3b2e0144c4d9f82cf5c
https://github.com/llvm/llvm-project/commit/8ae877a089d9c2ca5315d3b2e0144c4d9f82cf5c
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M flang/include/flang/Tools/TargetSetup.h
M flang/module/ieee_arithmetic.f90
M flang/test/CMakeLists.txt
M flang/test/Evaluate/fold-out_of_range.f90
M flang/test/Evaluate/folding07.f90
M flang/test/Lower/Intrinsics/ieee_class_queries.f90
M flang/test/Lower/Intrinsics/ieee_unordered.f90
M flang/test/Lower/common-block.f90
M flang/test/Semantics/kinds03.f90
M flang/test/Semantics/modfile26.f90
M flang/test/Semantics/realkinds-aarch64-01.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/f18/CMakeLists.txt
Log Message:
-----------
Revert "[flang] Warn when F128 is unsupported" (#106561)
Reverts llvm/llvm-project#102147
It seems some systems which should support F128 are wrongly detected as
not supporting.
This might be due to checking `LDBL_MANT_DIG` instead of
`__LDBL_MANT_DIG__`. I will investigate.
Commit: 9edd998e10fabfff067b9e6e5b044f85a24d0dd5
https://github.com/llvm/llvm-project/commit/9edd998e10fabfff067b9e6e5b044f85a24d0dd5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
A llvm/test/Transforms/LoopUnroll/X86/runtime-unroll-addrec-cost.ll
Log Message:
-----------
[LoopUnroll] Add test for #53205 (NFC)
Commit: fc110202dffa06950716e0cc4535b07aaa2c439c
https://github.com/llvm/llvm-project/commit/fc110202dffa06950716e0cc4535b07aaa2c439c
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/FormatVariadicBM.cpp
M llvm/include/llvm/Support/FormatVariadic.h
M llvm/lib/Support/FormatVariadic.cpp
M llvm/unittests/Support/FormatVariadicTest.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[Support] Validate number of arguments passed to formatv() (#105745)
Change formatv() to validate that the number of arguments passed matches
number of replacement fields in the format string, and that the replacement
indices do not contain holes.
To support cases where this cannot be guaranteed, introduce a formatv()
overload that allows disabling validation with a bool flag as its first argument.
Commit: 025f03f01e8584140b7ac27422cea0c0ef7ef6c1
https://github.com/llvm/llvm-project/commit/025f03f01e8584140b7ac27422cea0c0ef7ef6c1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++][NFC] Remove unused struct in <string> (#106527)
Commit: a705e8cb5b071b3bf6d1d55629f18f6b7b9699ac
https://github.com/llvm/llvm-project/commit/a705e8cb5b071b3bf6d1d55629f18f6b7b9699ac
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M libcxx/include/cmath
M libcxx/include/complex
M libcxx/test/libcxx/numerics/c.math/constexpr-fns.pass.cpp
Log Message:
-----------
[libc++][NFC] Remove __constexpr_is{nan,finite} (#106205)
They're never used in `constexpr` functions, so we can simply use
`std::isnan` and `std::isfinite` instead.
Commit: 032c3283ab419377a1230a32d98693b528f63134
https://github.com/llvm/llvm-project/commit/032c3283ab419377a1230a32d98693b528f63134
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/TableGen/intrinsic-attrs.td
M llvm/utils/TableGen/IntrinsicEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Refactor IntrinsicEmitter code (#106479)
- Use formatv() and raw string literals to simplify emission code.
- Use range based for loops and structured bindings to simplify loops.
- Use const Pointers to Records.
- Rename `ComputeFixedEncoding` to `ComputeTypeSignature` to reflect
what the function actually does, cnd change it to return a vector.
- Use reverse() and range based for loop to pack 8 nibbles into 32-bits.
- Rename some variables to follow LLVM coding standards.
- For function memory effects, print human readable effects in comment.
Commit: 4ee2ad259812159c4f51bf2d8edcf0376302b2c3
https://github.com/llvm/llvm-project/commit/4ee2ad259812159c4f51bf2d8edcf0376302b2c3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
R llvm/test/CodeGen/AArch64/atomicrmw-fadd-fp-vector.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
AArch64: Add tests for atomicrmw fp operations (#103701)
There were only codegen tests for the fadd vector case,
so round out the test coverage for the scalar cases
and all the other operations.
Commit: 5048fabb0579f1417f69cde49221b5b9e9c15414
https://github.com/llvm/llvm-project/commit/5048fabb0579f1417f69cde49221b5b9e9c15414
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/unittests/Support/FormatVariadicTest.cpp
Log Message:
-----------
[Support] Delete FormatVariadicTest Validate sub-test (#106570)
- The subtest, if enabled correctly, will fail with assert in Debug
builds and validation is disabled in Release builds.
- Hence deleting the test to fix test failures in CI.
Commit: 26c3a8404f1b3327a0982faeeaee94b08d1ee481
https://github.com/llvm/llvm-project/commit/26c3a8404f1b3327a0982faeeaee94b08d1ee481
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
Log Message:
-----------
AArch64: Use consistent atomicrmw expansion for FP operations (#103702)
Use LLSC or cmpxchg in the same cases as for the unsupported
integer operations. This required some fixups to the LLSC
implementatation to deal with the fp128 case.
The comment about floating-point exceptions was wrong,
because floating-point exceptions are not really exceptions at all.
Commit: b5a1b45fe321cdf57d1b6155ecbbc18b6f95502f
https://github.com/llvm/llvm-project/commit/b5a1b45fe321cdf57d1b6155ecbbc18b6f95502f
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Early return in getReorderingData [nfc]
Commit: a9ffb719bc323588b6b60fbf227db8104a81310e
https://github.com/llvm/llvm-project/commit/a9ffb719bc323588b6b60fbf227db8104a81310e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
Log Message:
-----------
[RISCV] Don't promote f16 FNEG/FABS with Zfhmin/Zhinxmin. (#106474)
fneg/fabs are not supposed to canonicalize nans. Promoting to f32 will
go through an fp_extend which will canonicalize. The generic Promote
handler needs to be removed from LegalizeDAG.
We need to use integer bit manip to clear the bit instead.
Unfortunately, this is going through the stack due to i16 not being a
legal type. Fixing that will require custom legalization or some other
generic SelectionDAG change.
Commit: e05c22484efb5c767115525adfa4273e48b1ae26
https://github.com/llvm/llvm-project/commit/e05c22484efb5c767115525adfa4273e48b1ae26
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
Log Message:
-----------
AArch64: Delete tests of fp128 atomicrmw fmin/fmax
These are getting different output on some build hosts for some reason.
The stack offsets of temporaries are different.
Commit: c08c6a71cfc536e22fb7ad733fb8181a9e84e62a
https://github.com/llvm/llvm-project/commit/c08c6a71cfc536e22fb7ad733fb8181a9e84e62a
Author: Hongtao Yu <hoy at meta.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/test/Dialect/SCF/loop-unroll.mlir
Log Message:
-----------
[mlir][scf] Allow unrolling loops with integer-typed IV. (#106164)
SCF loops now can operate on integer-typed IV, thus I'm changing the
loop unroller correspondingly.
Commit: 115b87636b9f84cf145c0c96859f8e9f5e76c7a1
https://github.com/llvm/llvm-project/commit/115b87636b9f84cf145c0c96859f8e9f5e76c7a1
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M llvm/lib/Support/ModRef.cpp
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/ModRefTest.cpp
Log Message:
-----------
[NFC][Support] Eliminate ',' at end of MemoryEffects print (#106545)
- Eliminate comma at end of a MemoryEffects print.
- Added basic unit test to validate that.
Commit: 29f3c85e3267480458d250f15b141eaad3386493
https://github.com/llvm/llvm-project/commit/29f3c85e3267480458d250f15b141eaad3386493
Author: Alex Richardson <alexrichardson at google.com>
Date: 2024-08-29 (Thu, 29 Aug 2024)
Changed paths:
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M clang-tools-extra/include-cleaner/lib/WalkAST.cpp
M clang-tools-extra/include-cleaner/unittests/WalkASTTest.cpp
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/ExtractAPI/API.h
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBlock.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/ExtractAPI/API.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
A clang/test/AST/ByteCode/cxx11-pedantic.cpp
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/Modules/no-local-decl-in-reduced-bmi.cppm
A clang/test/Modules/pr106483.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview-std.cppm
M clang/test/Modules/reduced-bmi-empty-module-purview.cppm
M clang/test/Modules/unreached-static-entities.cppm
M clang/tools/clang-repl/CMakeLists.txt
M compiler-rt/lib/builtins/cpu_model/riscv.c
M compiler-rt/lib/interception/interception_type_test.cpp
M flang/include/flang/Tools/TargetSetup.h
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/module/ieee_arithmetic.f90
M flang/test/CMakeLists.txt
M flang/test/Evaluate/fold-out_of_range.f90
M flang/test/Evaluate/folding07.f90
M flang/test/Lower/Intrinsics/ieee_class_queries.f90
M flang/test/Lower/Intrinsics/ieee_unordered.f90
A flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
A flang/test/Lower/OpenMP/distribute-parallel-do.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-compound.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multiple-clauses.f90
M flang/test/Lower/common-block.f90
M flang/test/Semantics/kinds03.f90
M flang/test/Semantics/modfile26.f90
M flang/test/Semantics/realkinds-aarch64-01.f90
M flang/test/lit.cfg.py
M flang/test/lit.site.cfg.py.in
M flang/tools/f18/CMakeLists.txt
M libc/src/string/memory_utils/x86_64/inline_memcpy.h
M libcxx/include/cmath
M libcxx/include/complex
M libcxx/include/string
M libcxx/test/libcxx/numerics/c.math/constexpr-fns.pass.cpp
M lld/COFF/Chunks.cpp
M lld/COFF/Chunks.h
M lld/COFF/Writer.cpp
A lld/test/COFF/arm64ec-range-thunks.s
M lldb/test/API/tools/lldb-dap/console/TestDAP_console.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_redirection_to_console.py
M lldb/test/API/tools/lldb-dap/coreFile/TestDAP_coreFile.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/launch/main.c
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/FormatVariadicBM.cpp
M llvm/docs/CodeOfConduct.rst
M llvm/docs/TestSuiteGuide.md
M llvm/include/llvm/Support/FormatVariadic.h
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Analysis/CMakeLists.txt
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/Support/FormatVariadic.cpp
M llvm/lib/Support/ModRef.cpp
M llvm/lib/Support/Z3Solver.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
A llvm/lib/Target/AMDGPU/GCNDPPCombine.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
A llvm/lib/Target/AMDGPU/SIFoldOperands.h
M llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/Sparc/SparcInstrAliases.td
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Analysis/LoopAccessAnalysis/evaluate-at-symbolic-max-backedge-taken-count-may-wrap.ll
R llvm/test/CodeGen/AArch64/atomicrmw-fadd-fp-vector.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
A llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
M llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
A llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
A llvm/test/CodeGen/AVR/std-immediate-overflow.ll
M llvm/test/CodeGen/PowerPC/is_fpclass.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
A llvm/test/CodeGen/RISCV/rvv/pr106109.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/Thumb2/pr52817.ll
M llvm/test/CodeGen/X86/fsafdo_test1.ll
M llvm/test/CodeGen/X86/fsafdo_test4.ll
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
M llvm/test/DebugInfo/X86/discriminator.ll
A llvm/test/DebugInfo/X86/is_stmt-at-block-start.ll
A llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
M llvm/test/MC/Sparc/sparc-misc-instructions.s
M llvm/test/TableGen/intrinsic-attrs.td
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes-cvt.ll
M llvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
A llvm/test/Transforms/LoopUnroll/X86/runtime-unroll-addrec-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
A llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
M llvm/test/Transforms/SCCP/pointer-nonnull.ll
M llvm/test/Transforms/SCCP/range-attribute.ll
R llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred-parent.ll
R llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-sindle-bv.ll
R llvm/test/Transforms/SLPVectorizer/X86/arith-div-undef.ll
R llvm/test/Transforms/SLPVectorizer/X86/bool-logical-op-reduction-with-poison.ll
R llvm/test/Transforms/SLPVectorizer/X86/buildvector-insert-mask-size.ll
R llvm/test/Transforms/SLPVectorizer/X86/buildvector-nodes-dependency.ll
R llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/catchswitch.ll
A llvm/test/Transforms/SLPVectorizer/X86/cmp-in-bv-node-type-cost.ll
R llvm/test/Transforms/SLPVectorizer/X86/crash_exceed_scheduling.ll
R llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast.ll
A llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
A llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
A llvm/test/Transforms/SLPVectorizer/arith-div-undef.ll
A llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
A llvm/test/Transforms/SLPVectorizer/buildvector-insert-mask-size.ll
A llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
A llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/catchswitch.ll
A llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
A llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize-with-call.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize.ll
R llvm/test/tools/llvm-split/AMDGPU/debug-name-hiding.ll
R llvm/test/tools/llvm-split/AMDGPU/debug-non-kernel-root.ll
R llvm/test/tools/llvm-split/AMDGPU/declarations-debug.ll
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-alias-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-cost-ranking.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-external.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-overridable.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables-noexternal.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependency-indirect.ll
A llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
A llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
M llvm/tools/bugpoint/CMakeLists.txt
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
M llvm/unittests/Support/CMakeLists.txt
M llvm/unittests/Support/FormatVariadicTest.cpp
A llvm/unittests/Support/ModRefTest.cpp
M llvm/utils/TableGen/IntrinsicEmitter.cpp
M llvm/utils/TableGen/X86DisassemblerTables.cpp
M llvm/utils/release/build_llvm_release.bat
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/lib/Conversion/SCFToControlFlow/CMakeLists.txt
M mlir/lib/Dialect/Linalg/Transforms/MeshShardingInterfaceImpl.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir
M mlir/test/Dialect/ArmSME/tile-zero-masks.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SCF/loop-unroll.mlir
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
fix win64 build
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/69cd4a7f3af9...29f3c85e3267
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