[all-commits] [llvm/llvm-project] 36b7c3: [X86, MC] Recognize OSIZE=64b when EVEX.W = 1, EVE...

[Freddy Ye via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 36b7c30b292f853c09b80f8bc2c5f233f68c9e7b
      https://github.com/llvm/llvm-project/commit/36b7c30b292f853c09b80f8bc2c5f233f68c9e7b
  Author: Freddy Ye <freddy.ye at intel.com>
  Date:   2024-08-29 (Thu, 29 Aug 2024)

  Changed paths:
    A llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
    M llvm/utils/TableGen/X86DisassemblerTables.cpp

  Log Message:
  -----------
  [X86, MC] Recognize OSIZE=64b when EVEX.W = 1, EVEX.pp = 01 (#103816)

In the legacy space, if both the 66 prefix and REX.W=1 are present, the
REX.W=1 takes precedence and makes OSIZE=64b. EVEX map 4 inherits this
convention, with EVEX.pp=01 and EVEX.W playing the roles of the 66
prefix and REX.W. So if EVEX.pp=00, the OSIZE can only be 64b or 32b,
depending on whether EVEX.W=1 or not. But if EVEX.pp=01, then OSIZE is
either 64b or 16b depending on whether EVEX.W=1 or not.



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