[all-commits] [llvm/llvm-project] e37d6d: [mlir][ArmSME] Merge consecutive `arm_sme.intr.zer...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e37d6d2a74d76fdc95f5c5d625e282ce600aad55
      https://github.com/llvm/llvm-project/commit/e37d6d2a74d76fdc95f5c5d625e282ce600aad55
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-08-29 (Thu, 29 Aug 2024)

  Changed paths:
    M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
    M mlir/test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir
    M mlir/test/Dialect/ArmSME/tile-zero-masks.mlir

  Log Message:
  -----------
  [mlir][ArmSME] Merge consecutive `arm_sme.intr.zero` ops (#106215)

This merges consecutive SME zero intrinsics within a basic block, which
avoids the backend eventually emitting multiple zero instructions when
it could just use one.

Note: This kind of peephole optimization could be implemented in the
backend too.



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