[all-commits] [llvm/llvm-project] 95d2d1: Move stepvector intrinsic out of experimental name...

[Maciej Gabka via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 95d2d1cba0e1428718bbdce0504292f62b212920
      https://github.com/llvm/llvm-project/commit/95d2d1cba0e1428718bbdce0504292f62b212920
  Author: Maciej Gabka <maciej.gabka at arm.com>
  Date:   2024-08-28 (Wed, 28 Aug 2024)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/IR/AutoUpgrade.cpp
    M llvm/lib/IR/IRBuilder.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
    M llvm/test/Analysis/CostModel/AArch64/neon-stepvector.ll
    M llvm/test/Analysis/CostModel/AArch64/sve-stepvector.ll
    M llvm/test/Analysis/CostModel/RISCV/stepvector.ll
    A llvm/test/Bitcode/upgrade-stepvector-intrinsic.ll
    M llvm/test/CodeGen/AArch64/neon-stepvector.ll
    M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
    M llvm/test/CodeGen/AArch64/sve-stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
    M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
    M llvm/test/Transforms/InstCombine/vscale_extractelement.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
    M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
    M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
    M llvm/test/Verifier/stepvector-intrinsic.ll
    M llvm/unittests/IR/IRBuilderTest.cpp
    M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
    M mlir/test/Conversion/VectorToLLVM/vector-mask-to-llvm.mlir
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-scalable-deinterleave.mlir
    M mlir/test/Target/LLVMIR/llvmir-invalid.mlir

  Log Message:
  -----------
  Move stepvector intrinsic out of experimental namespace (#98043)

This patch is moving out stepvector intrinsic from the experimental
namespace.

This intrinsic exists in LLVM for several years now, and is widely used.



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