[all-commits] [llvm/llvm-project] 77fccb: [AArch64] Replace AND with LSL#2 for LDR target (#...

[hanbeom via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 77fccb35ac08f66d52bb152735e27572bf9f3f93
      https://github.com/llvm/llvm-project/commit/77fccb35ac08f66d52bb152735e27572bf9f3f93
  Author: hanbeom <kese111 at gmail.com>
  Date:   2024-08-24 (Sat, 24 Aug 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/arm64-fold-lshr.ll

  Log Message:
  -----------
  [AArch64] Replace AND with LSL#2 for LDR target (#34101) (#89531)

Currently, process of replacing bitwise operations consisting of
`LSR`/`LSL` with `And` is performed by `DAGCombiner`.

However, in certain cases, the `AND` generated by this process
can be removed.

Consider following case:
```
        lsr x8, x8, #56
        and x8, x8, #0xfc
        ldr w0, [x2, x8]
        ret
```

In this case, we can remove the `AND` by changing the target of `LDR`
to `[X2, X8, LSL #2]` and right-shifting amount change to 56 to 58.

after changed:
```
        lsr x8, x8, #58
        ldr w0, [x2, x8, lsl #2]
        ret
```

This patch checks to see if the `SHIFTING` + `AND` operation on load
target can be optimized and optimizes it if it can.



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