[all-commits] [llvm/llvm-project] 646478: [AArch64] Scalarize i128 add/sub/mul/and/or/xor ve...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 646478f38b03cbc861ae17533c641c2a944118b3
      https://github.com/llvm/llvm-project/commit/646478f38b03cbc861ae17533c641c2a944118b3
  Author: David Green <david.green at arm.com>
  Date:   2024-08-23 (Fri, 23 Aug 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/add.ll
    M llvm/test/CodeGen/AArch64/andorxor.ll
    M llvm/test/CodeGen/AArch64/mul.ll
    M llvm/test/CodeGen/AArch64/sub.ll

  Log Message:
  -----------
  [AArch64] Scalarize i128 add/sub/mul/and/or/xor vectors

This mirrors what we do for SDAG, scalarizing i128 vectors with
add/sub/mul/and/or/xor operators.



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