[all-commits] [llvm/llvm-project] cb4efe: [VPlan] Don't trigger VF assertion if VPlan has ex...

[Florian Hahn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cb4efe1d078144a72306732a56afea3885650e8d
      https://github.com/llvm/llvm-project/commit/cb4efe1d078144a72306732a56afea3885650e8d
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-08-22 (Thu, 22 Aug 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll

  Log Message:
  -----------
  [VPlan] Don't trigger VF assertion if VPlan has extra simplifications.

There are cases where VPlans contain some simplifications that are very
hard to accurately account for up-front in the legacy cost model. Those
cases are caused by un-simplified inputs, which trigger the assert
ensuring both the legacy and VPlan-based cost model agree on the VF.

To avoid false positives due to missed simplifications in general, only
trigger the assert if the chosen VPlan doesn't contain any additional
simplifications.

Fixes https://github.com/llvm/llvm-project/issues/104714.
Fixes https://github.com/llvm/llvm-project/issues/105713.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications