[all-commits] [llvm/llvm-project] 7bcf4d: [AMDGPU] Correctly insert s_nops for dst forwardin...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7bcf4d63cf3b7bcc789808ea4e9c8369e94467dc
      https://github.com/llvm/llvm-project/commit/7bcf4d63cf3b7bcc789808ea4e9c8369e94467dc
  Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
  Date:   2024-08-22 (Thu, 22 Aug 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/lib/Target/AMDGPU/VOPInstructions.td
    A llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll

  Log Message:
  -----------
  [AMDGPU] Correctly insert s_nops for dst forwarding hazard (#100276)

MI300 ISA section 4.5 states there is a hazard between "VALU op which
uses OPSEL or SDWA with changes the result’s bit position" and "VALU op
consumes result of that op"

This includes the case where the second op is SDWA with same dest and
dst_sel != DWORD && dst_unused == UNUSED_PRESERVE. In this case, there
is an implicit read of the first op dst and the compiler needs to
resolve this hazard. Confirmed with HW team.

We model dst_unused == UNUSED_PRESERVE as tied-def of implicit operand,
so this PR checks for that.

MI300_SP_MAS section 1.3.9.2 specifies that CVT_SR_FP8_F32 and
CVT_SR_BF8_F32 with opsel[3:2] !=0 have dest forwarding issue.
Currently, we only add check for CVT_SR_FP8_F32 with opsel[3] != 0 --
this PR adds support opsel[2] != 0 as well



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