[all-commits] [llvm/llvm-project] f67388: [X86] Allow speculative BSR/BSF instructions on ta...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f67388232384682fb442d6e5501d9259c41fd714
      https://github.com/llvm/llvm-project/commit/f67388232384682fb442d6e5501d9259c41fd714
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-08-22 (Thu, 22 Aug 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/ctlz-codesize.ll
    M llvm/test/Analysis/CostModel/X86/ctlz-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/ctlz.ll
    M llvm/test/Analysis/CostModel/X86/cttz-codesize.ll
    M llvm/test/Analysis/CostModel/X86/cttz-sizelatency.ll
    M llvm/test/CodeGen/X86/atomic-bit-test.ll
    M llvm/test/CodeGen/X86/bit_ceil.ll
    M llvm/test/CodeGen/X86/combine-or.ll
    M llvm/test/CodeGen/X86/ctlo.ll
    M llvm/test/CodeGen/X86/ctlz.ll
    M llvm/test/CodeGen/X86/cttz.ll
    M llvm/test/CodeGen/X86/known-never-zero.ll
    M llvm/test/CodeGen/X86/lzcnt-cmp.ll
    M llvm/test/CodeGen/X86/pr57673.ll
    M llvm/test/CodeGen/X86/pr89877.ll
    M llvm/test/CodeGen/X86/pr92569.ll
    M llvm/test/Transforms/CodeGenPrepare/X86/cttz-ctlz.ll
    M llvm/test/Transforms/SLPVectorizer/X86/ctlz.ll

  Log Message:
  -----------
  [X86] Allow speculative BSR/BSF instructions on targets with CMOV (#102885)

Currently targets without LZCNT/TZCNT won't speculate with BSR/BSF instructions in case they have a zero value input, meaning we always insert a test+branch for the zero-input case.

This patch proposes we allow speculation if the target has CMOV, and perform a branchless select instead to handle the zero input case. This will predominately help x86-64 targets where we haven't set any particular cpu target. We already always perform BSR/BSF instructions if we were lowering a CTLZ/CTTZ_ZERO_UNDEF instruction.



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