[all-commits] [llvm/llvm-project] 67d3ef: [SPIR-V] Rework usage of virtual registers' types ...

Thu Aug 22 00:40:49 PDT 2024

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 67d3ef74b31e1517d4f679e754cc2b3041c95901
      https://github.com/llvm/llvm-project/commit/67d3ef74b31e1517d4f679e754cc2b3041c95901
  Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
  Date:   2024-08-22 (Thu, 22 Aug 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
    M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
    M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
    M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
    M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
    M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
    M llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
    M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
    M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
    M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
    M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
    M llvm/lib/Target/SPIRV/SPIRVSubtarget.h
    M llvm/test/CodeGen/SPIRV/constant/global-constants.ll
    M llvm/test/CodeGen/SPIRV/constant/local-aggregate-constant.ll
    M llvm/test/CodeGen/SPIRV/constant/local-bool-constants.ll
    M llvm/test/CodeGen/SPIRV/constant/local-float-point-constants.ll
    M llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll
    M llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll
    M llvm/test/CodeGen/SPIRV/constant/local-vector-matrix-constants.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_integers.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/decorate-prefetch-w-cache-controls.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_fpga_decorations/global-var-decorations.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_global_variable_host_access/global-var-host-access.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_optnone.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/builtin-op-wrappers.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/builtin_alloca.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_no_integer_wrap_decoration.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
    M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions-but-one.ll
    M llvm/test/CodeGen/SPIRV/extensions/enable-all-extensions.ll
    M llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll
    M llvm/test/CodeGen/SPIRV/function/identity-function.ll
    M llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll
    M llvm/test/CodeGen/SPIRV/function/trivial-function-definition.ll
    M llvm/test/CodeGen/SPIRV/function/trivial-function-with-attributes.ll
    M llvm/test/CodeGen/SPIRV/function/trivial-function-with-call.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll
    M llvm/test/CodeGen/SPIRV/image/sampler.ll
    M llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll
    M llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
    M llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
    M llvm/test/CodeGen/SPIRV/instructions/call-complex-function.ll
    M llvm/test/CodeGen/SPIRV/instructions/call-trivial-function.ll
    M llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
    M llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
    M llvm/test/CodeGen/SPIRV/instructions/float-fast-flags.ll
    M llvm/test/CodeGen/SPIRV/instructions/icmp.ll
    M llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
    M llvm/test/CodeGen/SPIRV/instructions/nested-composites.ll
    M llvm/test/CodeGen/SPIRV/instructions/scalar-bitwise-operations.ll
    M llvm/test/CodeGen/SPIRV/instructions/scalar-floating-point-arithmetic.ll
    M llvm/test/CodeGen/SPIRV/instructions/scalar-integer-arithmetic.ll
    M llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll
    M llvm/test/CodeGen/SPIRV/instructions/select.ll
    M llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll
    M llvm/test/CodeGen/SPIRV/instructions/undef-simple-composite-store.ll
    M llvm/test/CodeGen/SPIRV/instructions/unreachable.ll
    M llvm/test/CodeGen/SPIRV/instructions/vector-bitwise-operations.ll
    M llvm/test/CodeGen/SPIRV/instructions/vector-floating-point-arithmetic.ll
    M llvm/test/CodeGen/SPIRV/instructions/vector-integer-arithmetic.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/lifetime.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/nearbyint.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ptr-annotation.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/sqrt.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/umul.with.overflow.ll
    M llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll
    M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll
    M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll
    M llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll
    M llvm/test/CodeGen/SPIRV/pointers/complex.ll
    M llvm/test/CodeGen/SPIRV/pointers/custom-kernel-arg-type.ll
    M llvm/test/CodeGen/SPIRV/pointers/duplicate-type-ptr-def.ll
    M llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll
    M llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll
    M llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll
    M llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
    M llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll
    M llvm/test/CodeGen/SPIRV/pointers/global-zeroinitializer.ll
    M llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll
    M llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll
    M llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll
    M llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll
    M llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll
    M llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll
    M llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll
    M llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll
    M llvm/test/CodeGen/SPIRV/pointers/nested-struct-opaque-pointers.ll
    M llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll
    M llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll
    M llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll
    M llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll
    M llvm/test/CodeGen/SPIRV/pointers/store-operand-ptr-to-struct.ll
    M llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll
    M llvm/test/CodeGen/SPIRV/pointers/two-bitcast-or-param-users.ll
    M llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll
    M llvm/test/CodeGen/SPIRV/pointers/type-deduce-args-rev.ll
    M llvm/test/CodeGen/SPIRV/pointers/type-deduce-args.ll
    M llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll
    M llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-complex.ll
    M llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-rev.ll
    M llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call.ll
    M llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll
    M llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll
    M llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll
    M llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll

  Log Message:
  -----------
  [SPIR-V] Rework usage of virtual registers' types and classes (#104104)

This PR continues https://github.com/llvm/llvm-project/pull/101732
changes in virtual register processing aimed to improve correctness of
emitted MIR between passes from the perspective of MachineVerifier.
Namely, the following changes are introduced:
* register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and
instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected
and simplified (by removing unnecessary sophisticated options) -- e.g.,
this PR gets rid of duplicating 32/64 bits patterns, removes ANYID
register class and simplifies definition of the rest of register
classes,
* hardcoded LLT scalar types in passes before instruction selection are
corrected -- the goal is to have correct bit width before instruction
selection, and use 64 bits registers for pattern matching in the
instruction selection pass; 32-bit registers remain where they are
described in such terms by SPIR-V specification (like, for example,
creation of virtual registers for scope/mem semantics operands),
* rework virtual register type/class assignment for calls/builtins
lowering,
* a series of minor changes to fix validity of emitted code between
passes:
  - ensure that that bitcast changes the type,
  - fix the pattern for instruction selection for OpExtInst,
  - simplify inline asm operands usage,
  - account for arbitrary integer sizes / update legalizer rules;
* add '-verify-machineinstrs' to existed test cases.

See also https://github.com/llvm/llvm-project/issues/88129 that this PR
may resolve.

This PR fixes a great number of issues reported by MachineVerifier and,
as a result, reduces a number of failed test cases for the mode with
expensive checks set on from ~200 to ~57.

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