[all-commits] [llvm/llvm-project] f3bf46: [RISCV][GISel] Correct registers classes in vector...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3bf46f5308a9684f4a5493268d6a96396130871
      https://github.com/llvm/llvm-project/commit/f3bf46f5308a9684f4a5493268d6a96396130871
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-21 (Wed, 21 Aug 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir

  Log Message:
  -----------
  [RISCV][GISel] Correct registers classes in vector anyext.mir test. NFC



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