[all-commits] [llvm/llvm-project] 886368: [RISCV][GISel] Correct registers classes in vector...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 88636854b007affdbe324369b26c9ded66934b22
      https://github.com/llvm/llvm-project/commit/88636854b007affdbe324369b26c9ded66934b22
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-21 (Wed, 21 Aug 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir

  Log Message:
  -----------
  [RISCV][GISel] Correct registers classes in vector sext/zext.mir tests. NFC

The liveins were always for an LMUL=1 register class even if the
first instruction used a larger regsister class.

One test in zext.mir used the wrong class for the first instruction.



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