[all-commits] [llvm/llvm-project] 0ca77f: [RISCV] Add CSRs and an instruction for Smctr and ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0ca77f6656a772624a591261957f6b313a0d544e
      https://github.com/llvm/llvm-project/commit/0ca77f6656a772624a591261957f6b313a0d544e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-21 (Wed, 21 Aug 2024)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/MC/RISCV/hypervisor-csr-names.s
    M llvm/test/MC/RISCV/machine-csr-names.s
    A llvm/test/MC/RISCV/smctr-ssctr-valid.s
    M llvm/test/MC/RISCV/supervisor-csr-names.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3



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