[all-commits] [llvm/llvm-project] 9fa238: [RISCV] Add Hazard3 Core as taped out for RP2350 (...

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9fa2386ff13289d46ebf31656f4be7859f501468
      https://github.com/llvm/llvm-project/commit/9fa2386ff13289d46ebf31656f4be7859f501468
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2024-08-21 (Wed, 21 Aug 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Hazard3 Core as taped out for RP2350 (#102452)

Luke Wren's Hazard3 is a configurable, open-source 32-bit RISC-V core.
The core's source code and docs are available on github:
https://github.com/wren6991/hazard3

This is the RISC-V core used in the RP2350, a recently announced SoC by
Raspberry Pi (which also contains Arm cores):
https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf

We have agreed to name this `-mcpu` option `rp2350-hazard3`, and it
reflects exactly the options configured in the RP2350 chips. Notably,
the Zbc is not configured, and nor is B because the `misa.B` bit is not
either.



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