[all-commits] [llvm/llvm-project] 91b423: [DAG][RISCV] Use vp.<binop> when widening illegal ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 91b423d955ff1da6cfbe82436ffee280fa25cd02
      https://github.com/llvm/llvm-project/commit/91b423d955ff1da6cfbe82436ffee280fa25cd02
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-08-20 (Tue, 20 Aug 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/MatchContext.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

  Log Message:
  -----------
  [DAG][RISCV] Use vp.<binop> when widening illegal types for binops which can trap (#105214)

This allows the use a single wider operation with a restricted EVL
instead of having to split and cover via decreasing powers-of-two sizes.

On RISCV, this avoids the need for a bunch of vslidedown and vslideup
instructions to extract subvectors, and VL toggles to switch between the
various widths.

Note there is a potential downside of using vp nodes; we loose any
generic DAG combines which might have applied to the split form.



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