[all-commits] [llvm/llvm-project] 2599d6: [RISCV][GISel] Remove s32 support on RV64 for DIV, ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2599d695128381e6932b43f0e95649c533308d6d
      https://github.com/llvm/llvm-project/commit/2599d695128381e6932b43f0e95649c533308d6d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-20 (Tue, 20 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir

  Log Message:
  -----------
  [RISCV][GISel] Remove s32 support on RV64 for DIV, and REM. (#102519)

Based on experience with SelectionDAG and experimental-rv64-legal-i32, I
don't believe making s32 a legal type is viable without introducing an
invariant that s32 values are always sign extended like Mips64 does.
Mips64 does this with a separate 32-bit register class.

`experimental-rv64-legal-i32` was removed in ##102509.

This patch is part of a series to remove s32 support so we can remove
the isel patterns that SelectionDAG is no longer using. To restore code
quality, we will need to add custom W nodes like SelectionDAG.



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