[all-commits] [llvm/llvm-project] 7efa06: [RISCV] Add vector and vector crypto to SiFiveP400...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7efa068f7a7ed4f42ba09cce73e8c09bb8b4e8ce
      https://github.com/llvm/llvm-project/commit/7efa068f7a7ed4f42ba09cce73e8c09bb8b4e8ce
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-08-19 (Mon, 19 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbb.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkg.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkned.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvknhb.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksed.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksh.s

  Log Message:
  -----------
  [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155)

The SiFiveP400 scheduler model did not support vector or vector crypto.
With the addition of the sifive-p470 processor, this model needs to support
these extensions.

The processors who use this model but do not have vector or vector
crypto will never produce these instructions, so there is no impact to these
processors.

Co-authored-by: Min Hsu <min.hsu at sifive.com>



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