[all-commits] [llvm/llvm-project] a80a90: [RISCV][MC] Support experimental extensions Zvbc32...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a80a90e34b1f26422ebf56e922abe2c193607c81
      https://github.com/llvm/llvm-project/commit/a80a90e34b1f26422ebf56e922abe2c193607c81
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-08-19 (Mon, 19 Aug 2024)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/rvv/zvbc.s
    A llvm/test/MC/RISCV/rvv/zvkgs.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.



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