[all-commits] [llvm/llvm-project] ebe726: [Mips] Fix fast isel for i16 bswap. (#103398)

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ebe7265b142f370f0a563fece5db22f57383ba2d
      https://github.com/llvm/llvm-project/commit/ebe7265b142f370f0a563fece5db22f57383ba2d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-16 (Fri, 16 Aug 2024)

  Changed paths:
    M llvm/lib/Target/Mips/MipsFastISel.cpp
    M llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll

  Log Message:
  -----------
  [Mips] Fix fast isel for i16 bswap. (#103398)

We need to mask the SRL result to 8 bits before ORing in the SLL. This
is needed in case bits 23:16 of the input aren't zero. They will have
been shifted into bits 15:8.

We don't need to AND the result with 0xffff. It's ok if the upper 16
bits of the register are garbage.

Fixes #103035.



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