[all-commits] [llvm/llvm-project] ce88ca: [TableGen] Sign extend constants based on size for...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ce88ca928a29748f5fd179a3ab7f7039b3a311c4
      https://github.com/llvm/llvm-project/commit/ce88ca928a29748f5fd179a3ab7f7039b3a311c4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-16 (Fri, 16 Aug 2024)

  Changed paths:
    M llvm/utils/TableGen/Common/DAGISelMatcher.h

  Log Message:
  -----------
  [TableGen] Sign extend constants based on size for EmitIntegerMatcher. (#104550)

I'm planning to add a getSignedConstant to SelectionDAG and use it for
EmitInteger in SelectionDAGISel which already uses int64_t.
getSignedConstant will assert that the constant has the correct number
of significant bits for the VT.

This patch ensures that tablegen emits constants in this form.



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