[all-commits] [llvm/llvm-project] d7aeea: [AArch64] optimise SVE prefetch intrinsics with no...

[Lukacma via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d7aeea626dac64449fc67cf8ddf8f326a0157d91
      https://github.com/llvm/llvm-project/commit/d7aeea626dac64449fc67cf8ddf8f326a0157d91
  Author: Lukacma <Marian.Lukac at arm.com>
  Date:   2024-08-15 (Thu, 15 Aug 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes-prf.ll

  Log Message:
  -----------
  [AArch64] optimise SVE prefetch intrinsics with no active lanes (#103052)

This patch extends https://github.com/llvm/llvm-project/pull/73964 and
optimises away SVE prefetch intrinsics when predicate is zero.



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