[all-commits] [llvm/llvm-project] 4f7ce1: [RISCV] Don't combine (sext_inreg (fmv_x_anyexth X...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f7ce107de0c3ae0fb5748f98bc696b6eec7aad9
      https://github.com/llvm/llvm-project/commit/4f7ce107de0c3ae0fb5748f98bc696b6eec7aad9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-14 (Wed, 14 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
    M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll

  Log Message:
  -----------
  [RISCV] Don't combine (sext_inreg (fmv_x_anyexth X), i16) with Zhinx.

With Zfh and Zfhmin this combine creates a fmv_x_signexth node so we can
remember that the result is sign extended. This become a fmv.x.h
instruction which sign extends its result.

With Zhinx, fmv_x_signexth becomes a COPY_TO_REGCLASS. In order for
this to guarantee the result is properly sign extended we need all
producers of a GPRF16 register class to guarantee the rest of the
GPR is sign extended. I don't think we've done that. bitcasts from i16
to f16 definitely don't do it.

The safest thing to do is to not do this combine so the sign_extend_inreg
will emit a shift pair. This is also consistent with the code generated
for Zfinx on RV64, we don't assume the upper 32 bits are sign extended.



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